AJA NTV2 SDK  18.0.0.2717
NTV2 SDK 18.0.0.2717
ntv2registerexpert.cpp
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1 /* SPDX-License-Identifier: MIT */
7 #include "ntv2registerexpert.h"
8 #include "ntv2devicefeatures.hh"
9 #include "ntv2utils.h"
10 #include "ntv2debug.h"
11 #include "ntv2endian.h"
12 #include "ntv2vpid.h"
13 #include "ntv2bitfile.h"
14 #include "ntv2signalrouter.h"
15 #include "ajabase/common/common.h"
16 #include "ajabase/system/lock.h"
17 #include "ajabase/common/ajarefptr.h"
18 #include "ajabase/system/debug.h"
19 #include <algorithm>
20 #include <sstream>
21 #include <iterator>
22 #include <iomanip>
23 #include <map>
24 #include <math.h>
25 #include <ctype.h> // for isprint()
26 #if !defined(AJA_WINDOWS)
27 #include <unistd.h>
28 #endif
29 
30 
31 using namespace std;
32 
33 #define LOGGING_MAPPINGS (AJADebug::IsActive(AJA_DebugUnit_Enumeration))
34 #define HEX16(__x__) "0x" << hex << setw(16) << setfill('0') << uint64_t(__x__) << dec
35 #define INSTP(_p_) HEX16(uint64_t(_p_))
36 #define REiFAIL(__x__) AJA_sERROR (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
37 #define REiWARN(__x__) AJA_sWARNING(AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
38 #define REiNOTE(__x__) AJA_sNOTICE (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
39 #define REiINFO(__x__) AJA_sINFO (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
40 #define REiDBG(__x__) AJA_sDEBUG (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
41 
42 #define DEF_REGNAME(_num_) DefineRegName(_num_, #_num_)
43 #define DEF_REG(_num_, _dec_, _rw_, _c1_, _c2_, _c3_) DefineRegister((_num_), #_num_, _dec_, _rw_, _c1_, _c2_, _c3_)
44 
45 
46 static const string gChlClasses[] = { kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3, kRegClass_Channel4,
47  kRegClass_Channel5, kRegClass_Channel6, kRegClass_Channel7, kRegClass_Channel8 };
48 static const string sSpace(" ");
49 static const string sNull;
50 
51 typedef enum
52 {
53  regNTV4FS_FIRST,
54  regNTV4FS_LineLengthPitch = regNTV4FS_FIRST, // Reg 0 - Raster bytes/line[31:16] & pitch[15:0]
55  regNTV4FS_ROIVHSize, // Reg 1 - ROI size: vert[27:16] horz[11:0]
56  regNTV4FS_ROIF1StartAddr, // Reg 2 - ROI F1 start address [31:0]
57  regNTV4FS_ROIF2StartAddr, // Reg 3 - ROI F2 end address [31:0]
58  regNTV4FS_ROIF1VHOffsets, // Reg 4 - ROI F1 byte offsets: vert[26:16] horz[11:0]
59  regNTV4FS_ROIF2VHOffsets, // Reg 5 - ROI F2 byte offsets: vert[26:16] horz[11:0]
60  regNTV4FS_DisplayHorzPixelsPerLine, // Reg 6 - Horiz display: total[27:16] active[11:0]
61  regNTV4FS_DisplayFID, // Reg 7 - FID bit transition lines: FID lo[26:16] hi[10:0]
62  regNTV4FS_F1ActiveLines, // Reg 8 - Disp F1 active lines: end[26:16] start[10:0]
63  regNTV4FS_F2ActiveLines, // Reg 9 - Disp F2 active lines: end[26:16] start[10:0]
64  regNTV4FS_RasterControl, // Reg 10 - Control: sync[21:20] pixclk[18:16] pixfmt[12:8] p[6] rgb8cvt[5] dither[4] fill[3] DRT[2] disable[1] capture[0]
65  regNTV4FS_RasterPixelSkip, // Reg 11 - Raster pixel skip (or unpacker H offset?)
66  regNTV4FS_RasterVideoFill_YCb_GB, // Reg 12 - Raster video fill YorG[31:16] CbOrB[15:0]
67  regNTV4FS_RasterVideoFill_Cr_AR, // Reg 13 - Raster video fill A[31:16] CrOrR[15:0]
68  regNTV4FS_RasterROIFillAlpha, // Reg 14 - ROI Fill Alpha[15:0]
69  regNTV4FS_Status, // Reg 15 - Status lineCount[31:16] oddField[0]
70  regNTV4FS_RasterOutputTimingPreset, // Reg 16 - Output timing preset[23:0]
71  regNTV4FS_RasterVTotalLines, // Reg 17 - Total lines
72  regNTV4FS_RasterSmpteFramePulse, // Reg 18 - SMPTE frame pulse
73  regNTV4FS_RasterOddLineStartAddress, // Reg 19 - UHD odd line start addr | Green playback component offset (int12_t)
74  regNTV4FS_RasterOffsetBlue, // Reg 20 - Blue playback component offset[12:0] (int12_t)
75  regNTV4FS_RasterOffsetRed, // Reg 21 - Red playback component offset[12:0] (int12_t)
76  regNTV4FS_RasterOffsetAlpha, // Reg 22 - Alpha playback component offset[12:0] (int12_t)
77  regNTV4FS_InputSourceSelect = 63, // Reg 63 - Input source select[7:0]
78  regNTV4FS_LAST = regNTV4FS_InputSourceSelect,
79  regNTV4FS_REGISTER_COUNT
80 } NTV4FrameStoreRegs;
81 
82 static const std::string sNTV4FrameStoreRegNames[] = { "LineLengthPitch",
83  "ROIVHSize",
84  "ROIF1StartAddr",
85  "ROIF2StartAddr",
86  "ROIF1VHOffsets",
87  "ROIF2VHOffsets",
88  "DisplayHorzPixelsPerLine",
89  "DisplayFID",
90  "F1ActiveLines",
91  "F2ActiveLines",
92  "RasterControl",
93  "RasterPixelSkip",
94  "RasterVideoFill_YCb_GB",
95  "RasterVideoFill_Cr_AR",
96  "RasterROIFillAlpha",
97  "Status",
98  "RasterOutputTimingPreset",
99  "RasterVTotalLines",
100  "RasterSmpteFramePulse",
101  "RasterOddLineStartAddress",
102  "RasterOffsetBlue",
103  "RasterOffsetRed",
104  "RasterOffsetAlpha"};
105 static const ULWord kNTV4FrameStoreFirstRegNum (0x0000D000 / sizeof(ULWord)); // First FS reg num 13,312
106 static const ULWord kNumNTV4FrameStoreRegisters(regNTV4FS_REGISTER_COUNT); // 64 registers
107 
108 
109 class RegisterExpert;
110 typedef AJARefPtr<RegisterExpert> RegisterExpertPtr;
111 static uint32_t gInstanceTally(0);
112 static uint32_t gLivingInstances(0);
113 
114 
122 class RegisterExpert
123 {
124 public:
125  static RegisterExpertPtr GetInstance(const bool inCreateIfNecessary = true);
126  static bool DisposeInstance(void);
127 
128 private:
129  RegisterExpert()
130  {
131  AJAAutoLock lock(&mGuardMutex);
132  AJAAtomic::Increment(&gInstanceTally);
133  AJAAtomic::Increment(&gLivingInstances);
134  // Name "Classic" registers using NTV2RegisterNameString...
135  for (ULWord regNum (0); regNum < kRegNumRegisters; regNum++)
136  DefineRegName (regNum, ::NTV2RegisterNameString(regNum));
137  // Now the rest...
138  SetupBasicRegs(); // Basic registers
139  SetupVPIDRegs(); // VPIDs
140  SetupAncInsExt(); // Anc Ins/Ext
141  SetupAuxInsExt(); // Aux Ins/Ext
142  SetupXptSelect(); // Xpt Select
143  SetupDMARegs(); // DMA
144  SetupTimecodeRegs(); // Timecode
145  SetupAudioRegs(); // Audio
146  SetupMRRegs(); // MultiViewer/MultiRaster
147  SetupMixerKeyerRegs(); // Mixer/Keyer
148  SetupHDMIRegs(); // HDMI
149  SetupSDIErrorRegs(); // SDIError
150  SetupCSCRegs(); // CSCs
151  SetupLUTRegs(); // LUTs
152  SetupBOBRegs(); // Break Out Board
153  SetupLEDRegs(); // Bracket LEDs
154  SetupCMWRegs(); // Clock Monitor Out
155  SetupNTV4FrameStoreRegs(); // NTV4 FrameStores
156  SetupVRegs(); // Virtuals
157  REiNOTE(DEC(gLivingInstances) << " extant, " << DEC(gInstanceTally) << " total");
158  if (LOGGING_MAPPINGS)
159  {
160  REiDBG("RegsToStrsMap=" << mRegNumToStringMap.size()
161  << " RegsToDecodersMap=" << mRegNumToDecoderMap.size()
162  << " ClassToRegsMMap=" << mRegClassToRegNumMMap.size()
163  << " StrToRegsMMap=" << mStringToRegNumMMap.size()
164  << " InpXptsToXptRegInfoMap=" << mInputXpt2XptRegNumMaskIndexMap.size()
165  << " XptRegInfoToInpXptsMap=" << mXptRegNumMaskIndex2InputXptMap.size()
166  << " RegClasses=" << mAllRegClasses.size());
167  }
168  } // constructor
169 public:
170  ~RegisterExpert()
171  {
172  AJAAtomic::Decrement(&gLivingInstances);
173  REiNOTE(DEC(gLivingInstances) << " extant, " << DEC(gInstanceTally) << " total");
174  } // destructor
175 
176 private:
177  // This class implements a functor that returns a string that contains a human-readable decoding
178  // of a register value, given its number and the ID of the device it came from.
179  struct Decoder
180  {
181  // The default reg decoder functor returns an empty string.
182  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
183  {
184  (void) inRegNum;
185  (void) inRegValue;
186  (void) inDeviceID;
187  return string();
188  }
189  } mDefaultRegDecoder;
190 
191  void DefineRegName(const uint32_t regNumber, const string & regName)
192  {
193  if (!regName.empty())
194  {
195  AJAAutoLock lock(&mGuardMutex);
196  if (mRegNumToStringMap.find(regNumber) == mRegNumToStringMap.end())
197  {
198  mRegNumToStringMap.insert (RegNumToStringPair(regNumber, regName));
199  string lowerCaseRegName(regName);
200  mStringToRegNumMMap.insert (StringToRegNumPair(aja::lower(lowerCaseRegName), regNumber));
201  }
202  }
203  }
204  inline void DefineRegDecoder(const uint32_t inRegNum, const Decoder & dec)
205  {
206  AJAAutoLock lock(&mGuardMutex);
207  mRegNumToDecoderMap.insert (RegNumToDecoderPair(inRegNum, &dec));
208  }
209  inline void DefineRegClass (const uint32_t inRegNum, const string & className)
210  {
211  if (!className.empty())
212  {
213  AJAAutoLock lock(&mGuardMutex);
214  mRegClassToRegNumMMap.insert(StringToRegNumPair(className, inRegNum));
215  }
216  }
217  void DefineRegReadWrite(const uint32_t inRegNum, const int rdWrt)
218  {
219  AJAAutoLock lock(&mGuardMutex);
220  if (rdWrt == READONLY)
221  {
222  NTV2_ASSERT (!IsRegisterWriteOnly(inRegNum));
223  DefineRegClass (inRegNum, kRegClass_ReadOnly);
224  }
225  if (rdWrt == WRITEONLY)
226  {
227  NTV2_ASSERT (!IsRegisterReadOnly(inRegNum));
228  DefineRegClass (inRegNum, kRegClass_WriteOnly);
229  }
230  }
231  void DefineRegister(const uint32_t inRegNum, const string & regName, const Decoder & dec, const int rdWrt, const string & className1, const string & className2, const string & className3)
232  {
233  DefineRegName (inRegNum, regName);
234  DefineRegDecoder (inRegNum, dec);
235  DefineRegReadWrite (inRegNum, rdWrt);
236  DefineRegClass (inRegNum, className1);
237  DefineRegClass (inRegNum, className2);
238  DefineRegClass (inRegNum, className3);
239  }
240  void DefineXptReg(const uint32_t inRegNum, const NTV2InputXptID xpt0, const NTV2InputXptID xpt1, const NTV2InputXptID xpt2, const NTV2InputXptID xpt3)
241  {
242  DefineRegister (inRegNum, sNull, mDecodeXptGroupReg, READWRITE, kRegClass_Routing, kRegClass_NULL, kRegClass_NULL);
243  const NTV2InputCrosspointID indexes [4] = {xpt0, xpt1, xpt2, xpt3};
244  for (int ndx(0); ndx < 4; ndx++)
245  {
246  if (indexes[ndx] == NTV2_INPUT_CROSSPOINT_INVALID)
247  continue;
248  const XptRegNumAndMaskIndex regNumAndNdx(inRegNum, ndx);
249  if (mXptRegNumMaskIndex2InputXptMap.find(regNumAndNdx) == mXptRegNumMaskIndex2InputXptMap.end())
250  mXptRegNumMaskIndex2InputXptMap [regNumAndNdx] = indexes[ndx];
251  if (mInputXpt2XptRegNumMaskIndexMap.find(indexes[ndx]) == mInputXpt2XptRegNumMaskIndexMap.end())
252  mInputXpt2XptRegNumMaskIndexMap[indexes[ndx]] = regNumAndNdx;
253  }
254  }
255 
256  void SetupBasicRegs(void)
257  {
258  AJAAutoLock lock(&mGuardMutex);
259  DefineRegister (kRegGlobalControl, "", mDecodeGlobalControlReg, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
260  DefineRegister (kRegGlobalControl2, "", mDecodeGlobalControl2, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
261  DefineRegister (kRegGlobalControl3, "", mDecodeGlobalControl3, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
262  DefineRegister (kRegGlobalControlCh2, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
263  DefineRegister (kRegGlobalControlCh3, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
264  DefineRegister (kRegGlobalControlCh4, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
265  DefineRegister (kRegGlobalControlCh5, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
266  DefineRegister (kRegGlobalControlCh6, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
267  DefineRegister (kRegGlobalControlCh7, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
268  DefineRegister (kRegGlobalControlCh8, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
269  DefineRegister (kRegCh1Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
270  DefineRegister (kRegCh2Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
271  DefineRegister (kRegCh3Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
272  DefineRegister (kRegCh4Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
273  DefineRegister (kRegCh5Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
274  DefineRegister (kRegCh6Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
275  DefineRegister (kRegCh7Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
276  DefineRegister (kRegCh8Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
277  #if 1 // PCIAccessFrame regs are obsolete
278  DefineRegister (kRegCh1PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
279  DefineRegister (kRegCh2PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
280  DefineRegister (kRegCh3PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
281  DefineRegister (kRegCh4PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
282  DefineRegister (kRegCh5PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
283  DefineRegister (kRegCh6PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
284  DefineRegister (kRegCh7PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
285  DefineRegister (kRegCh8PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
286  #endif // PCIAccessFrame regs are obsolete
287  DefineRegister (kRegCh1InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel1, kRegClass_NULL);
288  DefineRegister (kRegCh2InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel2, kRegClass_NULL);
289  DefineRegister (kRegCh3InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel3, kRegClass_NULL);
290  DefineRegister (kRegCh4InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel4, kRegClass_NULL);
291  DefineRegister (kRegCh5InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel5, kRegClass_NULL);
292  DefineRegister (kRegCh6InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel6, kRegClass_NULL);
293  DefineRegister (kRegCh7InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel7, kRegClass_NULL);
294  DefineRegister (kRegCh8InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel8, kRegClass_NULL);
295  DefineRegister (kRegCh1OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
296  DefineRegister (kRegCh2OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
297  DefineRegister (kRegCh3OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
298  DefineRegister (kRegCh4OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
299  DefineRegister (kRegCh5OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
300  DefineRegister (kRegCh6OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
301  DefineRegister (kRegCh7OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
302  DefineRegister (kRegCh8OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
303  DefineRegister (kRegSDIOut1Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
304  DefineRegister (kRegSDIOut2Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
305  DefineRegister (kRegSDIOut3Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
306  DefineRegister (kRegSDIOut4Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
307  DefineRegister (kRegSDIOut5Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
308  DefineRegister (kRegSDIOut6Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
309  DefineRegister (kRegSDIOut7Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
310  DefineRegister (kRegSDIOut8Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
311  DefineRegister (kRegSDIOut6Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
312  DefineRegister (kRegSDIOut7Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
313  DefineRegister (kRegSDIOut8Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
314 
315  DefineRegister (kRegOutputTimingControl, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
316  DefineRegister (kRegOutputTimingControlch2, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
317  DefineRegister (kRegOutputTimingControlch3, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
318  DefineRegister (kRegOutputTimingControlch4, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
319  DefineRegister (kRegOutputTimingControlch5, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
320  DefineRegister (kRegOutputTimingControlch6, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
321  DefineRegister (kRegOutputTimingControlch7, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
322 
323  DefineRegister (kRegCh1ControlExtended, "", mDecodeChannelControlExt, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
324  DefineRegister (kRegCh2ControlExtended, "", mDecodeChannelControlExt, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
325  DefineRegister (kRegBoardID, "", mDecodeBoardID, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
326  DefineRegister (kRegFirmwareUserID, "", mDecodeFirmwareUserID, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
327 
328  DefineRegister (kRegCanDoStatus, "", mDecodeCanDoStatus, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
329  DefineRegister (kRegBitfileDate, "", mDecodeBitfileDateTime, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
330  DefineRegister (kRegBitfileTime, "", mDecodeBitfileDateTime, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
331  DefineRegister (kRegCPLDVersion, "", mDecodeCPLDVersion, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
332 
333  DefineRegister (kRegVidIntControl, "", mDecodeVidIntControl, READWRITE, kRegClass_Interrupt, kRegClass_Channel1, kRegClass_Channel2);
334  DefineRegClass (kRegVidIntControl, kRegClass_Channel3);
335  DefineRegClass (kRegVidIntControl, kRegClass_Channel4);
336  DefineRegister (kRegStatus, "", mDecodeStatusReg, READWRITE, kRegClass_Interrupt, kRegClass_Channel1, kRegClass_Channel2);
337  DefineRegClass (kRegStatus, kRegClass_Timecode);
338  DefineRegister (kRegVidIntControl2, "", mDecodeVidIntControl2, READWRITE, kRegClass_Interrupt, kRegClass_Channel5, kRegClass_Channel5);
339  DefineRegClass (kRegVidIntControl2, kRegClass_Channel7);
340  DefineRegClass (kRegVidIntControl2, kRegClass_Channel8);
341  DefineRegister (kRegStatus2, "", mDecodeStatus2Reg, READWRITE, kRegClass_Interrupt, kRegClass_Channel3, kRegClass_Channel4);
342  DefineRegClass (kRegStatus2, kRegClass_Channel5);
343  DefineRegClass (kRegStatus2, kRegClass_Channel6);
344  DefineRegClass (kRegStatus2, kRegClass_Channel7);
345  DefineRegClass (kRegStatus2, kRegClass_Channel8);
346  DefineRegister (kRegInputStatus, "", mDecodeInputStatusReg, READONLY, kRegClass_Input, kRegClass_Channel1, kRegClass_Channel2);
347  DefineRegClass (kRegInputStatus, kRegClass_Audio);
348  DefineRegister (kRegSDIInput3GStatus, "", mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel1, kRegClass_Channel2);
349  DefineRegister (kRegSDIInput3GStatus2, "", mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel3, kRegClass_Channel4);
350  DefineRegister (kRegSDI5678Input3GStatus,"",mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel5, kRegClass_Channel6);
351  DefineRegClass (kRegSDI5678Input3GStatus, kRegClass_Channel7);
352  DefineRegClass (kRegSDI5678Input3GStatus, kRegClass_Channel8);
353  DefineRegister (kRegInputStatus2, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel3, kRegClass_Channel4); // 288
354  DefineRegister (kRegInput56Status, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel5, kRegClass_Channel6); // 458
355  DefineRegister (kRegInput78Status, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel7, kRegClass_Channel8); // 459
356 
357  DefineRegister (kRegFS1ReferenceSelect, "", mDecodeFS1RefSelectReg, READWRITE, kRegClass_Input, kRegClass_Timecode, kRegClass_NULL);
358  DefineRegister (kRegSysmonVccIntDieTemp,"", mDecodeSysmonVccIntDieTemp, READONLY, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
359  DefineRegister (kRegSDITransmitControl, "", mDecodeSDITransmitCtrl, READWRITE, kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3);
360  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel4);
361  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel5);
362  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel6);
363  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel7);
364  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel8);
365 
366  DefineRegister (kRegConversionControl, "", mConvControlRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_Channel2);
367  DefineRegister (kRegSDIWatchdogControlStatus, "", mDecodeRelayCtrlStat, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
368  DefineRegister (kRegSDIWatchdogTimeout, "", mDecodeWatchdogTimeout, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
369  DefineRegister (kRegSDIWatchdogKick1, "", mDecodeWatchdogKick, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
370  DefineRegister (kRegSDIWatchdogKick2, "", mDecodeWatchdogKick, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
371  DefineRegister (kRegIDSwitch, "kRegIDSwitch", mDecodeIDSwitchStatus, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
372  DefineRegister (kRegPWMFanControl, "kRegPWMFanControl", mDecodePWMFanControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
373  DefineRegister (kRegPWMFanStatus, "kRegPWMFanStatus", mDecodePWMFanMonitor, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
374  }
375  void SetupBOBRegs(void)
376  {
377  AJAAutoLock lock(&mGuardMutex);
378  DefineRegister (kRegBOBStatus, "kRegBOBStatus", mDecodeBOBStatus, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
379  DefineRegister (kRegBOBGPIInData, "kRegBOBGPIInData", mDecodeBOBGPIIn, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
380  DefineRegister (kRegBOBGPIInterruptControl, "kRegBOBGPIInterruptControl", mDecodeBOBGPIInInterruptControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
381  DefineRegister (kRegBOBGPIOutData, "kRegBOBGPIOutData", mDecodeBOBGPIOut, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
382  DefineRegister (kRegBOBAudioControl, "kRegBOBAudioControl", mDecodeBOBAudioControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
383  }
384  void SetupLEDRegs(void)
385  {
386  AJAAutoLock lock(&mGuardMutex);
387  DefineRegister (kRegLEDReserved0, "kRegLEDReserved0", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
388  DefineRegister (kRegLEDClockDivide, "kRegLEDClockDivide", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
389  DefineRegister (kRegLEDReserved2, "kRegLEDReserved2", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
390  DefineRegister (kRegLEDReserved3, "kRegLEDReserved3", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
391  DefineRegister (kRegLEDSDI1Control, "kRegLEDSDI1Control", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
392  DefineRegister (kRegLEDSDI2Control, "kRegLEDSDI2Control", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
393  DefineRegister (kRegLEDHDMIInControl, "kRegLEDHDMIInControl", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
394  DefineRegister (kRegLEDHDMIOutControl, "kRegLEDHDMIOutControl", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
395  }
396  void SetupCMWRegs(void)
397  {
398  AJAAutoLock lock(&mGuardMutex);
399  DefineRegister (kRegCMWControl, "kRegCMWControl", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
400  DefineRegister (kRegCMW1485Out, "kRegCMW1485Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
401  DefineRegister (kRegCMW14835Out, "kRegCMW14835Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
402  DefineRegister (kRegCMW27Out, "kRegCMW27Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
403  DefineRegister (kRegCMW12288Out, "kRegCMW12288Out", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
404  DefineRegister (kRegCMWHDMIOut, "kRegCMWHDMIOut", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
405  }
406  void SetupVPIDRegs(void)
407  {
408  AJAAutoLock lock(&mGuardMutex);
409  DefineRegister (kRegSDIIn1VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel1);
410  DefineRegister (kRegSDIIn1VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel1);
411  DefineRegister (kRegSDIOut1VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
412  DefineRegister (kRegSDIOut1VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
413  DefineRegister (kRegSDIOut2VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
414  DefineRegister (kRegSDIOut2VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
415  DefineRegister (kRegSDIIn2VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel2);
416  DefineRegister (kRegSDIIn2VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel2);
417  DefineRegister (kRegSDIOut3VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel3);
418  DefineRegister (kRegSDIOut3VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel3);
419  DefineRegister (kRegSDIOut4VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel4);
420  DefineRegister (kRegSDIOut4VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel4);
421  DefineRegister (kRegSDIIn3VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel3);
422  DefineRegister (kRegSDIIn3VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel3);
423  DefineRegister (kRegSDIIn4VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel4);
424  DefineRegister (kRegSDIIn4VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel4);
425  DefineRegister (kRegSDIOut5VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel5);
426  DefineRegister (kRegSDIOut5VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel5);
427  DefineRegister (kRegSDIIn5VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel5);
428  DefineRegister (kRegSDIIn5VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel5);
429  DefineRegister (kRegSDIIn6VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel6);
430  DefineRegister (kRegSDIIn6VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel6);
431  DefineRegister (kRegSDIOut6VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel6);
432  DefineRegister (kRegSDIOut6VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel6);
433  DefineRegister (kRegSDIIn7VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel7);
434  DefineRegister (kRegSDIIn7VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel7);
435  DefineRegister (kRegSDIOut7VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel7);
436  DefineRegister (kRegSDIOut7VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel7);
437  DefineRegister (kRegSDIIn8VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel8);
438  DefineRegister (kRegSDIIn8VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel8);
439  DefineRegister (kRegSDIOut8VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel8);
440  DefineRegister (kRegSDIOut8VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel8);
441  }
442  void SetupTimecodeRegs(void)
443  {
444  AJAAutoLock lock(&mGuardMutex);
445  DefineRegister (kRegRP188InOut1DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
446  DefineRegister (kRegRP188InOut1Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
447  DefineRegister (kRegRP188InOut1Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
448  DefineRegister (kRegRP188InOut2DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
449  DefineRegister (kRegRP188InOut2Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
450  DefineRegister (kRegRP188InOut2Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
451  DefineRegister (kRegLTCOutBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Output);
452  DefineRegister (kRegLTCOutBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Output);
453  DefineRegister (kRegLTCInBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Input);
454  DefineRegister (kRegLTCInBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Input);
455  DefineRegister (kRegRP188InOut1Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
456  DefineRegister (kRegRP188InOut1Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
457  DefineRegister (kRegRP188InOut2Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
458  DefineRegister (kRegRP188InOut2Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
459  DefineRegister (kRegRP188InOut3Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
460  DefineRegister (kRegRP188InOut3Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
461  DefineRegister (kRegRP188InOut4Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
462  DefineRegister (kRegRP188InOut4Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
463  DefineRegister (kRegRP188InOut5Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
464  DefineRegister (kRegRP188InOut5Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
465  DefineRegister (kRegRP188InOut6Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
466  DefineRegister (kRegRP188InOut6Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
467  DefineRegister (kRegRP188InOut7Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
468  DefineRegister (kRegRP188InOut7Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
469  DefineRegister (kRegRP188InOut8Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
470  DefineRegister (kRegRP188InOut8Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
471  DefineRegister (kRegLTCStatusControl, "", mLTCStatusControlDecoder, READWRITE, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
472  DefineRegister (kRegLTC2EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
473  DefineRegister (kRegLTC2EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
474  DefineRegister (kRegLTC2AnalogBits0_31, "", mDefaultRegDecoder, READONLY, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
475  DefineRegister (kRegLTC2AnalogBits32_63, "", mDefaultRegDecoder, READONLY, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
476  DefineRegister (kRegRP188InOut3DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
477  DefineRegister (kRegRP188InOut3Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
478  DefineRegister (kRegRP188InOut3Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
479  DefineRegister (kRegRP188InOut4DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
480  DefineRegister (kRegRP188InOut4Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
481  DefineRegister (kRegRP188InOut4Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
482  DefineRegister (kRegLTC3EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
483  DefineRegister (kRegLTC3EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
484  DefineRegister (kRegLTC4EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
485  DefineRegister (kRegLTC4EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
486  DefineRegister (kRegRP188InOut5Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
487  DefineRegister (kRegRP188InOut5Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
488  DefineRegister (kRegRP188InOut5DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
489  DefineRegister (kRegLTC5EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
490  DefineRegister (kRegLTC5EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
491  DefineRegister (kRegRP188InOut6Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
492  DefineRegister (kRegRP188InOut6Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
493  DefineRegister (kRegRP188InOut6DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
494  DefineRegister (kRegLTC6EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
495  DefineRegister (kRegLTC6EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
496  DefineRegister (kRegRP188InOut7Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
497  DefineRegister (kRegRP188InOut7Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
498  DefineRegister (kRegRP188InOut7DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
499  DefineRegister (kRegLTC7EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
500  DefineRegister (kRegLTC7EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
501  DefineRegister (kRegRP188InOut8Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
502  DefineRegister (kRegRP188InOut8Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
503  DefineRegister (kRegRP188InOut8DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
504  DefineRegister (kRegLTC8EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
505  DefineRegister (kRegLTC8EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
506  } // SetupTimecodeRegs
507 
508  void SetupAudioRegs(void)
509  {
510  AJAAutoLock lock(&mGuardMutex);
511  DefineRegister (kRegAud1Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
512  DefineRegister (kRegAud2Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
513  DefineRegister (kRegAud3Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
514  DefineRegister (kRegAud4Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
515  DefineRegister (kRegAud5Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
516  DefineRegister (kRegAud6Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
517  DefineRegister (kRegAud7Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
518  DefineRegister (kRegAud8Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
519  DefineRegister (kRegAud1Detect, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel1, kRegClass_Channel2);
520  DefineRegister (kRegAudDetect2, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel3, kRegClass_Channel4);
521  DefineRegister (kRegAudioDetect5678, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel8, kRegClass_Channel7);
522  DefineRegClass (kRegAudioDetect5678, kRegClass_Channel6);
523  DefineRegClass (kRegAudioDetect5678, kRegClass_Channel5);
524  DefineRegister (kRegAud1SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
525  DefineRegister (kRegAud2SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
526  DefineRegister (kRegAud3SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
527  DefineRegister (kRegAud4SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
528  DefineRegister (kRegAud5SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
529  DefineRegister (kRegAud6SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
530  DefineRegister (kRegAud7SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
531  DefineRegister (kRegAud8SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
532  DefineRegister (kRegAud1Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
533  DefineRegister (kRegAud2Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
534  DefineRegister (kRegAud3Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
535  DefineRegister (kRegAud4Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
536  DefineRegister (kRegAud5Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
537  DefineRegister (kRegAud6Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
538  DefineRegister (kRegAud7Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
539  DefineRegister (kRegAud8Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
540  DefineRegister (kRegAud1OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Output);
541  DefineRegister (kRegAud2OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_Output);
542  DefineRegister (kRegAud3OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_Output);
543  DefineRegister (kRegAud4OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_Output);
544  DefineRegister (kRegAud5OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Output);
545  DefineRegister (kRegAud6OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_Output);
546  DefineRegister (kRegAud7OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_Output);
547  DefineRegister (kRegAud8OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_Output);
548  DefineRegister (kRegAud1InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Input);
549  DefineRegister (kRegAud2InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_Input);
550  DefineRegister (kRegAud3InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_Input);
551  DefineRegister (kRegAud4InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_Input);
552  DefineRegister (kRegAud5InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Input);
553  DefineRegister (kRegAud6InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_Input);
554  DefineRegister (kRegAud7InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_Input);
555  DefineRegister (kRegAud8InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_Input);
556  DefineRegister (kRegPCMControl4321, "", mDecodePCMControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Channel2);
557  DefineRegClass (kRegPCMControl4321, kRegClass_Channel3);
558  DefineRegClass (kRegPCMControl4321, kRegClass_Channel4);
559  DefineRegister (kRegPCMControl8765, "", mDecodePCMControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Channel6);
560  DefineRegClass (kRegPCMControl8765, kRegClass_Channel7);
561  DefineRegClass (kRegPCMControl8765, kRegClass_Channel8);
562  DefineRegister (kRegAud1Counter, "", mDefaultRegDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
563  DefineRegister (kRegAudioOutputSourceMap,"",mDecodeAudOutputSrcMap, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_AES);
564  DefineRegClass (kRegAudioOutputSourceMap, kRegClass_HDMI);
565 
566  DefineRegister (kRegAudioMixerInputSelects, "kRegAudioMixerInputSelects", mAudMxrInputSelDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
567  DefineRegister (kRegAudioMixerMainGain, "kRegAudioMixerMainGain", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
568  DefineRegister (kRegAudioMixerAux1GainCh1, "kRegAudioMixerAux1GainCh1", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
569  DefineRegister (kRegAudioMixerAux2GainCh1, "kRegAudioMixerAux2GainCh1", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
570  DefineRegister (kRegAudioMixerChannelSelect, "kRegAudioMixerChannelSelect", mAudMxrChanSelDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
571  DefineRegister (kRegAudioMixerMutes, "kRegAudioMixerMutes", mAudMxrMutesDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
572  DefineRegister (kRegAudioMixerAux1GainCh2, "kRegAudioMixerAux1GainCh2", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
573  DefineRegister (kRegAudioMixerAux2GainCh2, "kRegAudioMixerAux2GainCh2", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
574  DefineRegister (kRegAudioMixerAux1InputLevels, "kRegAudioMixerAux1InputLevels", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
575  DefineRegister (kRegAudioMixerAux2InputLevels, "kRegAudioMixerAux2InputLevels", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
576  DefineRegister (kRegAudioMixerMainInputLevelsPair0, "kRegAudioMixerMainInputLevelsPair0", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
577  DefineRegister (kRegAudioMixerMainInputLevelsPair1, "kRegAudioMixerMainInputLevelsPair1", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
578  DefineRegister (kRegAudioMixerMainInputLevelsPair2, "kRegAudioMixerMainInputLevelsPair2", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
579  DefineRegister (kRegAudioMixerMainInputLevelsPair3, "kRegAudioMixerMainInputLevelsPair3", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
580  DefineRegister (kRegAudioMixerMainInputLevelsPair4, "kRegAudioMixerMainInputLevelsPair4", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
581  DefineRegister (kRegAudioMixerMainInputLevelsPair5, "kRegAudioMixerMainInputLevelsPair5", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
582  DefineRegister (kRegAudioMixerMainInputLevelsPair6, "kRegAudioMixerMainInputLevelsPair6", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
583  DefineRegister (kRegAudioMixerMainInputLevelsPair7, "kRegAudioMixerMainInputLevelsPair7", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
584  DefineRegister (kRegAudioMixerMainOutputLevelsPair0, "kRegAudioMixerMainOutputLevelsPair0", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
585  DefineRegister (kRegAudioMixerMainOutputLevelsPair1, "kRegAudioMixerMainOutputLevelsPair1", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
586  DefineRegister (kRegAudioMixerMainOutputLevelsPair2, "kRegAudioMixerMainOutputLevelsPair2", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
587  DefineRegister (kRegAudioMixerMainOutputLevelsPair3, "kRegAudioMixerMainOutputLevelsPair3", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
588  DefineRegister (kRegAudioMixerMainOutputLevelsPair4, "kRegAudioMixerMainOutputLevelsPair4", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
589  DefineRegister (kRegAudioMixerMainOutputLevelsPair5, "kRegAudioMixerMainOutputLevelsPair5", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
590  DefineRegister (kRegAudioMixerMainOutputLevelsPair6, "kRegAudioMixerMainOutputLevelsPair6", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
591  DefineRegister (kRegAudioMixerMainOutputLevelsPair7, "kRegAudioMixerMainOutputLevelsPair7", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
592  }
593 
594  void SetupMRRegs(void)
595  {
596  AJAAutoLock lock(&mGuardMutex);
597  DefineRegister (kRegMRQ1Control, "kRegMRQ1Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
598  DefineRegister (kRegMRQ2Control, "kRegMRQ2Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
599  DefineRegister (kRegMRQ3Control, "kRegMRQ3Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
600  DefineRegister (kRegMRQ4Control, "kRegMRQ4Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
601  DefineRegister (kRegMROutControl, "kRegMROutControl", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
602  DefineRegister (kRegMRSupport, "kRegMRSupport", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
603  }
604 
605  void SetupDMARegs(void)
606  {
607  AJAAutoLock lock(&mGuardMutex);
608  DefineRegister (kRegDMA1HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
609  DefineRegister (kRegDMA1HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
610  DefineRegister (kRegDMA1LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
611  DefineRegister (kRegDMA1XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
612  DefineRegister (kRegDMA1NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
613  DefineRegister (kRegDMA1NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
614  DefineRegister (kRegDMA2HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
615  DefineRegister (kRegDMA2HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
616  DefineRegister (kRegDMA2LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
617  DefineRegister (kRegDMA2XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
618  DefineRegister (kRegDMA2NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
619  DefineRegister (kRegDMA2NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
620  DefineRegister (kRegDMA3HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
621  DefineRegister (kRegDMA3HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
622  DefineRegister (kRegDMA3LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
623  DefineRegister (kRegDMA3XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
624  DefineRegister (kRegDMA3NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
625  DefineRegister (kRegDMA3NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
626  DefineRegister (kRegDMA4HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
627  DefineRegister (kRegDMA4HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
628  DefineRegister (kRegDMA4LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
629  DefineRegister (kRegDMA4XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
630  DefineRegister (kRegDMA4NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
631  DefineRegister (kRegDMA4NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
632  DefineRegister (kRegDMAControl, "", mDMAControlRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
633  DefineRegister (kRegDMAIntControl, "", mDMAIntControlRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
634  }
635 
636  void SetupXptSelect(void)
637  {
638  AJAAutoLock lock(&mGuardMutex);
639  // RegNum 0-7 8-15 16-23 24-31
640  DefineXptReg (kRegXptSelectGroup1, NTV2_XptLUT1Input, NTV2_XptCSC1VidInput, NTV2_XptConversionModInput, NTV2_XptCompressionModInput);
641  DefineXptReg (kRegXptSelectGroup2, NTV2_XptFrameBuffer1Input, NTV2_XptFrameSync1Input, NTV2_XptFrameSync2Input, NTV2_XptDualLinkOut1Input);
642  DefineXptReg (kRegXptSelectGroup3, NTV2_XptAnalogOutInput, NTV2_XptSDIOut1Input, NTV2_XptSDIOut2Input, NTV2_XptCSC1KeyInput);
643  DefineXptReg (kRegXptSelectGroup4, NTV2_XptMixer1FGVidInput, NTV2_XptMixer1FGKeyInput, NTV2_XptMixer1BGVidInput, NTV2_XptMixer1BGKeyInput);
644  DefineXptReg (kRegXptSelectGroup5, NTV2_XptFrameBuffer2Input, NTV2_XptLUT2Input, NTV2_XptCSC2VidInput, NTV2_XptCSC2KeyInput);
645  DefineXptReg (kRegXptSelectGroup6, NTV2_XptWaterMarker1Input, NTV2_XptIICT1Input, NTV2_XptHDMIOutInput, NTV2_XptOEInput);
646  { // An additional input Xpt for kRegXptSelectGroup6 in mask index 2...
647  const XptRegNumAndMaskIndex regNumAndNdx (kRegXptSelectGroup6, 2);
648  if (mXptRegNumMaskIndex2InputXptMap.find (regNumAndNdx) == mXptRegNumMaskIndex2InputXptMap.end())
649  mXptRegNumMaskIndex2InputXptMap [regNumAndNdx] = NTV2_XptHDMIOutQ1Input;
650  if (mInputXpt2XptRegNumMaskIndexMap.find (NTV2_XptHDMIOutQ1Input) == mInputXpt2XptRegNumMaskIndexMap.end())
651  mInputXpt2XptRegNumMaskIndexMap[NTV2_XptHDMIOutQ1Input] = regNumAndNdx;
652  }
653  DefineXptReg (kRegXptSelectGroup7, NTV2_XptWaterMarker2Input, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptDualLinkOut2Input, NTV2_INPUT_CROSSPOINT_INVALID);
654  DefineXptReg (kRegXptSelectGroup8, NTV2_XptSDIOut3Input, NTV2_XptSDIOut4Input, NTV2_XptSDIOut5Input, NTV2_INPUT_CROSSPOINT_INVALID);
655  DefineXptReg (kRegXptSelectGroup9, NTV2_XptMixer2FGVidInput, NTV2_XptMixer2FGKeyInput, NTV2_XptMixer2BGVidInput, NTV2_XptMixer2BGKeyInput);
656  DefineXptReg (kRegXptSelectGroup10, NTV2_XptSDIOut1InputDS2, NTV2_XptSDIOut2InputDS2, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
657  DefineXptReg (kRegXptSelectGroup11, NTV2_XptDualLinkIn1Input, NTV2_XptDualLinkIn1DSInput, NTV2_XptDualLinkIn2Input, NTV2_XptDualLinkIn2DSInput);
658  DefineXptReg (kRegXptSelectGroup12, NTV2_XptLUT3Input, NTV2_XptLUT4Input, NTV2_XptLUT5Input, NTV2_Xpt3DLUT1Input);
659  DefineXptReg (kRegXptSelectGroup13, NTV2_XptFrameBuffer3Input, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptFrameBuffer4Input, NTV2_INPUT_CROSSPOINT_INVALID);
660  DefineXptReg (kRegXptSelectGroup14, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptSDIOut3InputDS2, NTV2_XptSDIOut5InputDS2, NTV2_XptSDIOut4InputDS2);
661  DefineXptReg (kRegXptSelectGroup15, NTV2_XptDualLinkIn3Input, NTV2_XptDualLinkIn3DSInput, NTV2_XptDualLinkIn4Input, NTV2_XptDualLinkIn4DSInput);
662  DefineXptReg (kRegXptSelectGroup16, NTV2_XptDualLinkOut3Input, NTV2_XptDualLinkOut4Input, NTV2_XptDualLinkOut5Input, NTV2_INPUT_CROSSPOINT_INVALID);
663  DefineXptReg (kRegXptSelectGroup17, NTV2_XptCSC3VidInput, NTV2_XptCSC3KeyInput, NTV2_XptCSC4VidInput, NTV2_XptCSC4KeyInput);
664  DefineXptReg (kRegXptSelectGroup18, NTV2_XptCSC5VidInput, NTV2_XptCSC5KeyInput, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
665  DefineXptReg (kRegXptSelectGroup19, NTV2_Xpt4KDCQ1Input, NTV2_Xpt4KDCQ2Input, NTV2_Xpt4KDCQ3Input, NTV2_Xpt4KDCQ4Input);
666  DefineXptReg (kRegXptSelectGroup20, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptHDMIOutQ2Input, NTV2_XptHDMIOutQ3Input, NTV2_XptHDMIOutQ4Input);
667  DefineXptReg (kRegXptSelectGroup21, NTV2_XptFrameBuffer5Input, NTV2_XptFrameBuffer6Input, NTV2_XptFrameBuffer7Input, NTV2_XptFrameBuffer8Input);
668  DefineXptReg (kRegXptSelectGroup22, NTV2_XptSDIOut6Input, NTV2_XptSDIOut6InputDS2, NTV2_XptSDIOut7Input, NTV2_XptSDIOut7InputDS2);
669  DefineXptReg (kRegXptSelectGroup23, NTV2_XptCSC7VidInput, NTV2_XptCSC7KeyInput, NTV2_XptCSC8VidInput, NTV2_XptCSC8KeyInput);
670  DefineXptReg (kRegXptSelectGroup24, NTV2_XptLUT6Input, NTV2_XptLUT7Input, NTV2_XptLUT8Input, NTV2_INPUT_CROSSPOINT_INVALID);
671  DefineXptReg (kRegXptSelectGroup25, NTV2_XptDualLinkIn5Input, NTV2_XptDualLinkIn5DSInput, NTV2_XptDualLinkIn6Input, NTV2_XptDualLinkIn6DSInput);
672  DefineXptReg (kRegXptSelectGroup26, NTV2_XptDualLinkIn7Input, NTV2_XptDualLinkIn7DSInput, NTV2_XptDualLinkIn8Input, NTV2_XptDualLinkIn8DSInput);
673  DefineXptReg (kRegXptSelectGroup27, NTV2_XptDualLinkOut6Input, NTV2_XptDualLinkOut7Input, NTV2_XptDualLinkOut8Input, NTV2_INPUT_CROSSPOINT_INVALID);
674  DefineXptReg (kRegXptSelectGroup28, NTV2_XptMixer3FGVidInput, NTV2_XptMixer3FGKeyInput, NTV2_XptMixer3BGVidInput, NTV2_XptMixer3BGKeyInput);
675  DefineXptReg (kRegXptSelectGroup29, NTV2_XptMixer4FGVidInput, NTV2_XptMixer4FGKeyInput, NTV2_XptMixer4BGVidInput, NTV2_XptMixer4BGKeyInput);
676  DefineXptReg (kRegXptSelectGroup30, NTV2_XptSDIOut8Input, NTV2_XptSDIOut8InputDS2, NTV2_XptCSC6VidInput, NTV2_XptCSC6KeyInput);
677  DefineXptReg (kRegXptSelectGroup32, NTV2_Xpt425Mux1AInput, NTV2_Xpt425Mux1BInput, NTV2_Xpt425Mux2AInput, NTV2_Xpt425Mux2BInput);
678  DefineXptReg (kRegXptSelectGroup33, NTV2_Xpt425Mux3AInput, NTV2_Xpt425Mux3BInput, NTV2_Xpt425Mux4AInput, NTV2_Xpt425Mux4BInput);
679  DefineXptReg (kRegXptSelectGroup34, NTV2_XptFrameBuffer1DS2Input, NTV2_XptFrameBuffer2DS2Input, NTV2_XptFrameBuffer3DS2Input, NTV2_XptFrameBuffer4DS2Input);
680  DefineXptReg (kRegXptSelectGroup35, NTV2_XptFrameBuffer5DS2Input, NTV2_XptFrameBuffer6DS2Input, NTV2_XptFrameBuffer7DS2Input, NTV2_XptFrameBuffer8DS2Input);
681  DefineXptReg (kRegXptSelectGroup36, NTV2_XptMultiLinkOut1Input, NTV2_XptMultiLinkOut1InputDS2, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
682 
683 
684  // Expose the CanConnect ROM registers:
685  for (ULWord regNum(kRegFirstValidXptROMRegister); regNum < ULWord(kRegInvalidValidXptROMRegister); regNum++)
686  { ostringstream regName; // used to synthesize reg name
687  const ULWord rawInputXpt ((regNum - ULWord(kRegFirstValidXptROMRegister)) / 4UL + ULWord(NTV2_FIRST_INPUT_CROSSPOINT));
688  const ULWord ndx ((regNum - ULWord(kRegFirstValidXptROMRegister)) % 4UL);
689  const NTV2InputXptID inputXpt (NTV2InputXptID(rawInputXpt+0));
690  if (NTV2_IS_VALID_InputCrosspointID(inputXpt))
691  {
692  string inputXptEnumName (::NTV2InputCrosspointIDToString(inputXpt,false)); // e.g. "NTV2_XptFrameBuffer1Input"
693  if (inputXptEnumName.empty())
694  regName << "kRegXptValid" << DEC0N(rawInputXpt,3) << "N" << DEC(ndx);
695  else
696  regName << "kRegXptValid" << aja::replace(inputXptEnumName, "NTV2_Xpt", "") << DEC(ndx);
697  }
698  else
699  regName << "kRegXptValue" << HEX0N(regNum,4);
700  DefineRegister (regNum, regName.str(), mDecodeXptValidReg, READONLY, kRegClass_XptROM, kRegClass_NULL, kRegClass_NULL);
701  }
702  } // SetupXptSelect
703 
704  void SetupAncInsExt(void)
705  {
706  static const string AncExtRegNames [] = { "Control", "F1 Start Address", "F1 End Address",
707  "F2 Start Address", "F2 End Address", "Field Cutoff Lines",
708  "Memory Total", "F1 Memory Usage", "F2 Memory Usage",
709  "V Blank Lines", "Lines Per Frame", "Field ID Lines",
710  "Ignore DID 1-4", "Ignore DID 5-8", "Ignore DID 9-12",
711  "Ignore DID 13-16", "Ignore DID 17-20", "Analog Start Line",
712  "Analog F1 Y Filter", "Analog F2 Y Filter", "Analog F1 C Filter",
713  "Analog F2 C Filter", "", "",
714  "", "", "",
715  "Analog Act Line Len"};
716  static const string AncInsRegNames [] = { "Field Bytes", "Control", "F1 Start Address",
717  "F2 Start Address", "Pixel Delay", "Active Start",
718  "Pixels Per Line", "Lines Per Frame", "Field ID Lines",
719  "Payload ID Control", "Payload ID", "Chroma Blank Lines",
720  "F1 C Blanking Mask", "F2 C Blanking Mask", "Field Bytes High",
721  "Reserved 15", "RTP Payload ID", "RTP SSRC",
722  "IP Channel"};
723  static const uint32_t AncExtPerChlRegBase [] = { 0x1000, 0x1040, 0x1080, 0x10C0, 0x1100, 0x1140, 0x1180, 0x11C0 };
724  static const uint32_t AncInsPerChlRegBase [] = { 0x1200, 0x1240, 0x1280, 0x12C0, 0x1300, 0x1340, 0x1380, 0x13C0 };
725 
726  NTV2_ASSERT(sizeof(AncExtRegNames[0]) == sizeof(AncExtRegNames[1]));
727  NTV2_ASSERT(size_t(regAncExt_LAST) == sizeof(AncExtRegNames)/sizeof(AncExtRegNames[0]));
728  NTV2_ASSERT(size_t(regAncIns_LAST) == sizeof(AncInsRegNames)/sizeof(string));
729 
730  AJAAutoLock lock(&mGuardMutex);
731  for (ULWord offsetNdx (0); offsetNdx < 8; offsetNdx++)
732  {
733  for (ULWord reg(regAncExtControl); reg < regAncExt_LAST; reg++)
734  {
735  if (AncExtRegNames[reg].empty()) continue;
736  ostringstream oss; oss << "Extract " << (offsetNdx+1) << " " << AncExtRegNames[reg];
737  DefineRegName (AncExtPerChlRegBase[offsetNdx] + reg, oss.str());
738  }
739  for (ULWord reg(regAncInsFieldBytes); reg < regAncIns_LAST; reg++)
740  {
741  ostringstream oss; oss << "Insert " << (offsetNdx+1) << " " << AncInsRegNames[reg];
742  DefineRegName (AncInsPerChlRegBase[offsetNdx] + reg, oss.str());
743  }
744  }
745  for (ULWord ndx (0); ndx < 8; ndx++)
746  {
747  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtControl, "", mDecodeAncExtControlReg, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
748  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
749  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
750  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
751  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
752  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFieldCutoffLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
753  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtTotalStatus, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
754  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
755  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
756  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFieldVBLStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
757  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtTotalFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
758  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFID, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
759  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_1_2_3_4, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
760  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_5_6_7_8, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
761  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_9_10_11_12, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
762  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_13_14_15_16, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
763  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_17_18_19_20, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
764  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtAnalogStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
765  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1AnalogYFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
766  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2AnalogYFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
767  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1AnalogCFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
768  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2AnalogCFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
769  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtAnalogActiveLineLength, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
770 
771  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytes, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
772  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsControl, "", mDecodeAncInsControlReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
773  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField1StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
774  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField2StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
775  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPixelDelay, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
776  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsActiveStart, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
777  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsLinePixels, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
778  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
779  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldIDLines, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
780  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadIDControl, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
781  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
782  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankCStartLine, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
783  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField1CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
784  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField2CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
785  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytesHigh, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
786  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
787  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpSSRC, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
788  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsIpChannel, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
789  }
790  } // SetupAncInsExt
791 
792  void SetupAuxInsExt(void)
793  {
794  static const string AuxExtRegNames [] = { "Control", "F1 Start Address", "F1 End Address",
795  "F2 Start Address", "", "",
796  "Memory Total", "F1 Memory Usage", "F2 Memory Usage",
797  "V Blank Lines", "Lines Per Frame", "Field ID Lines",
798  "Ignore DID 1-4", "Ignore DID 5-8", "Ignore DID 9-12",
799  "Ignore DID 13-16", "Buffer Fill"};
800  // static const string AncInsRegNames [] = { "Field Bytes", "Control", "F1 Start Address",
801  // "F2 Start Address", "Pixel Delay", "Active Start",
802  // "Pixels Per Line", "Lines Per Frame", "Field ID Lines",
803  // "Payload ID Control", "Payload ID", "Chroma Blank Lines",
804  // "F1 C Blanking Mask", "F2 C Blanking Mask", "Field Bytes High",
805  // "Reserved 15", "RTP Payload ID", "RTP SSRC",
806  // "IP Channel"};
807  static const uint32_t AuxExtPerChlRegBase [] = { 7616, 7680, 7744, 7808 };
808  static const uint32_t AuxInsPerChlRegBase [] = { 4608, 4672, 4736, 4800 };
809  NTV2_UNUSED(AuxInsPerChlRegBase);
810 
811  NTV2_ASSERT(sizeof(AuxExtRegNames[0]) == sizeof(AuxExtRegNames[1]));
812  NTV2_ASSERT(size_t(regAuxExt_LAST) == sizeof(AuxExtRegNames)/sizeof(AuxExtRegNames[0]));
813  //NTV2_ASSERT(size_t(regAncIns_LAST) == sizeof(AncInsRegNames)/sizeof(string));
814 
815  AJAAutoLock lock(&mGuardMutex);
816  for (ULWord offsetNdx (0); offsetNdx < 4; offsetNdx++)
817  {
818  for (ULWord reg(regAuxExtControl); reg < regAuxExt_LAST; reg++)
819  {
820  if (AuxExtRegNames[reg].empty()) continue;
821  ostringstream oss; oss << "Extract " << (offsetNdx+1) << " " << AuxExtRegNames[reg];
822  DefineRegName (AuxExtPerChlRegBase[offsetNdx] + reg, oss.str());
823  }
824  // for (ULWord reg(regAncInsFieldBytes); reg < regAncIns_LAST; reg++)
825  // {
826  // ostringstream oss; oss << "Insert " << (offsetNdx+1) << " " << AncInsRegNames[reg];
827  // DefineRegName (AncInsPerChlRegBase[offsetNdx] + reg, oss.str());
828  // }
829  }
830  for (ULWord ndx (0); ndx < 4; ndx++)
831  {
832  // Some of the decoders are shared with Anc
833  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtControl, "", mDecodeAuxExtControlReg, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
834  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
835  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
836  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField2StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
837  // DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExt4, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
838  // DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExt5, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
839  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtTotalStatus, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
840  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
841  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField2Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
842  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFieldVBLStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
843  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtTotalFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
844  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFID, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
845  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask0, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
846  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask1, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
847  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask2, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
848  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask3, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
849  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFillData, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
850 
851 
852  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytes, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
853  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsControl, "", mDecodeAncInsControlReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
854  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField1StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
855  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField2StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
856  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPixelDelay, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
857  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsActiveStart, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
858  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsLinePixels, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
859  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
860  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldIDLines, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
861  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadIDControl, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
862  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
863  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankCStartLine, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
864  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField1CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
865  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField2CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
866  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytesHigh, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
867  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
868  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpSSRC, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
869  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsIpChannel, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
870  }
871  } // SetupAuxInsExt
872 
873  void SetupHDMIRegs(void)
874  {
875  AJAAutoLock lock(&mGuardMutex);
876  DefineRegister (kRegHDMIOutControl, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
877  DefineRegister (kRegHDMIInputStatus, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
878  DefineRegister (kRegHDMIInputControl, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
879  DefineRegister (kRegHDMIHDRGreenPrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
880  DefineRegister (kRegHDMIHDRBluePrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
881  DefineRegister (kRegHDMIHDRRedPrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
882  DefineRegister (kRegHDMIHDRWhitePoint, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
883  DefineRegister (kRegHDMIHDRMasteringLuminence, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
884  DefineRegister (kRegHDMIHDRLightLevel, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
885  DefineRegister (kRegHDMIHDRControl, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
886  DefineRegister (kRegMRQ1Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
887  DefineRegister (kRegMRQ2Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
888  DefineRegister (kRegMRQ3Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
889  DefineRegister (kRegMRQ4Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
890  DefineRegister (kRegHDMIV2I2C1Control, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
891  DefineRegister (kRegHDMIV2I2C1Data, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
892  DefineRegister (kRegHDMIV2VideoSetup, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
893  DefineRegister (kRegHDMIV2HSyncDurationAndBackPorch, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
894  DefineRegister (kRegHDMIV2HActive, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
895  DefineRegister (kRegHDMIV2VSyncDurationAndBackPorchField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
896  DefineRegister (kRegHDMIV2VSyncDurationAndBackPorchField2, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
897  DefineRegister (kRegHDMIV2VActiveField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
898  DefineRegister (kRegHDMIV2VActiveField2, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
899  DefineRegister (kRegHDMIV2VideoStatus, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
900  DefineRegister (kRegHDMIV2HorizontalMeasurements, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
901  DefineRegister (kRegHDMIV2HBlankingMeasurements, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
902  DefineRegister (kRegHDMIV2HBlankingMeasurements1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
903  DefineRegister (kRegHDMIV2VerticalMeasurementsField0, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
904  DefineRegister (kRegHDMIV2VerticalMeasurementsField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
905  DefineRegister (kRegHDMIV2i2c2Control, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
906  DefineRegister (kRegHDMIV2i2c2Data, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
907 
908  DefineRegister (kVRegHDMIOutControl1, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
909  DefineRegister (kVRegHDMIInputStatus1, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
910  DefineRegister (kVRegHDMIInputControl1, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
911  DefineRegister (kVRegHDMIOutStatus1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
912  DefineRegister (kVRegHDMIOutHDRGreenPrimary1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
913  DefineRegister (kVRegHDMIOutHDRBluePrimary1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
914  DefineRegister (kVRegHDMIOutHDRRedPrimary1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
915  DefineRegister (kVRegHDMIOutHDRWhitePoint1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
916  DefineRegister (kVRegHDMIOutHDRMasterLuminance1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
917  DefineRegister (kVRegHDMIOutHDRLightLevel1, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
918  DefineRegister (kVRegHDMIOutHDRControl1, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
919 
920  DefineRegister (kVRegHDMIOutControl2, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
921  DefineRegister (kVRegHDMIInputStatus2, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
922  DefineRegister (kVRegHDMIInputControl2, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
923  DefineRegister (kVRegHDMIOutStatus2, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
924  DefineRegister (kVRegHDMIOutHDRGreenPrimary2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
925  DefineRegister (kVRegHDMIOutHDRBluePrimary2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
926  DefineRegister (kVRegHDMIOutHDRRedPrimary2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
927  DefineRegister (kVRegHDMIOutHDRWhitePoint2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
928  DefineRegister (kVRegHDMIOutHDRMasterLuminance2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
929  DefineRegister (kVRegHDMIOutHDRLightLevel2, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
930  DefineRegister (kVRegHDMIOutHDRControl2, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
931 
932  DefineRegister (kVRegHDMIOutControl3, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
933  DefineRegister (kVRegHDMIInputStatus3, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
934  DefineRegister (kVRegHDMIInputControl3, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
935  DefineRegister (kVRegHDMIOutStatus3, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
936  DefineRegister (kVRegHDMIOutHDRGreenPrimary3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
937  DefineRegister (kVRegHDMIOutHDRBluePrimary3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
938  DefineRegister (kVRegHDMIOutHDRRedPrimary3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
939  DefineRegister (kVRegHDMIOutHDRWhitePoint3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
940  DefineRegister (kVRegHDMIOutHDRMasterLuminance3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
941  DefineRegister (kVRegHDMIOutHDRLightLevel3, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
942  DefineRegister (kVRegHDMIOutHDRControl3, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
943 
944  DefineRegister (kVRegHDMIOutControl4, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
945  DefineRegister (kVRegHDMIInputStatus4, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
946  DefineRegister (kVRegHDMIInputControl4, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
947  DefineRegister (kVRegHDMIOutStatus4, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
948  DefineRegister (kVRegHDMIOutHDRGreenPrimary4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
949  DefineRegister (kVRegHDMIOutHDRBluePrimary4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
950  DefineRegister (kVRegHDMIOutHDRRedPrimary4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
951  DefineRegister (kVRegHDMIOutHDRWhitePoint4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
952  DefineRegister (kVRegHDMIOutHDRMasterLuminance4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
953  DefineRegister (kVRegHDMIOutHDRLightLevel4, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
954  DefineRegister (kVRegHDMIOutHDRControl4, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
955 
956  DefineRegister (0x1d00, "reg_hdmiin4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
957  DefineRegister (0x1d01, "reg_hdmiin4_videodetect0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
958  DefineRegister (0x1d02, "reg_hdmiin4_videodetect1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
959  DefineRegister (0x1d03, "reg_hdmiin4_videodetect2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
960  DefineRegister (0x1d04, "reg_hdmiin4_videodetect3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
961  DefineRegister (0x1d05, "reg_hdmiin4_videodetect4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
962  DefineRegister (0x1d06, "reg_hdmiin4_videodetect5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
963  DefineRegister (0x1d07, "reg_hdmiin4_videodetect6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
964  DefineRegister (0x1d08, "reg_hdmiin4_videodetect7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
965  DefineRegister (0x1d09, "reg_hdmiin4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
966  DefineRegister (0x1d0a, "reg_hdmiin4_receiverstatus", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
967  DefineRegister (0x1d0b, "reg_hdmiin4_auxpacketignore0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
968  DefineRegister (0x1d0c, "reg_hdmiin4_auxpacketignore1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
969  DefineRegister (0x1d0d, "reg_hdmiin4_auxpacketignore2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
970  DefineRegister (0x1d0e, "reg_hdmiin4_auxpacketignore3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
971  DefineRegister (0x1d0f, "reg_hdmiin4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
972  DefineRegister (0x1d10, "reg_hdmiin4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
973  DefineRegister (0x1d11, "reg_hdmiin4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
974  DefineRegister (0x1d12, "reg_hdmiin4_rxclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
975  DefineRegister (0x1d13, "reg_hdmiin4_rxoversampling", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
976  DefineRegister (0x1d14, "reg_hdmiin4_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
977  DefineRegister (0x1d15, "reg_hdmiin4_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
978  DefineRegister (0x1d16, "reg_hdmiin4_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
979  DefineRegister (0x1d1e, "reg_hdmiin4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
980  DefineRegister (0x1d1f, "reg_hdmiin4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
981 
982  DefineRegister (0x2500, "reg_hdmiin4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
983  DefineRegister (0x2501, "reg_hdmiin4_videodetect0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
984  DefineRegister (0x2502, "reg_hdmiin4_videodetect1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
985  DefineRegister (0x2503, "reg_hdmiin4_videodetect2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
986  DefineRegister (0x2504, "reg_hdmiin4_videodetect3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
987  DefineRegister (0x2505, "reg_hdmiin4_videodetect4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
988  DefineRegister (0x2506, "reg_hdmiin4_videodetect5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
989  DefineRegister (0x2507, "reg_hdmiin4_videodetect6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
990  DefineRegister (0x2508, "reg_hdmiin4_videodetect7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
991  DefineRegister (0x2509, "reg_hdmiin4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
992  DefineRegister (0x250a, "reg_hdmiin4_receiverstatus", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
993  DefineRegister (0x250b, "reg_hdmiin4_auxpacketignore0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
994  DefineRegister (0x250c, "reg_hdmiin4_auxpacketignore1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
995  DefineRegister (0x250d, "reg_hdmiin4_auxpacketignore2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
996  DefineRegister (0x250e, "reg_hdmiin4_auxpacketignore3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
997  DefineRegister (0x250f, "reg_hdmiin4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
998  DefineRegister (0x2510, "reg_hdmiin4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
999  DefineRegister (0x2511, "reg_hdmiin4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1000  DefineRegister (0x2512, "reg_hdmiin4_rxclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1001  DefineRegister (0x2513, "reg_hdmiin4_rxoversampling", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1002  DefineRegister (0x2514, "reg_hdmiin4_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1003  DefineRegister (0x2515, "reg_hdmiin4_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1004  DefineRegister (0x2516, "reg_hdmiin4_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1005  DefineRegister (0x251e, "reg_hdmiin4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1006  DefineRegister (0x251f, "reg_hdmiin4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
1007 
1008  DefineRegister (0x2c00, "reg_hdmiin_i2c_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1009  DefineRegister (0x2c01, "reg_hdmiin_i2c_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1010  DefineRegister (0x2c02, "reg_hdmiin_video_setup", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1011  DefineRegister (0x2c03, "reg_hdmiin_hsync_duration", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1012  DefineRegister (0x2c04, "reg_hdmiin_h_active", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1013  DefineRegister (0x2c05, "reg_hdmiin_vsync_duration_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1014  DefineRegister (0x2c06, "reg_hdmiin_vsync_duration_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1015  DefineRegister (0x2c07, "reg_hdmiin_v_active_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1016  DefineRegister (0x2c08, "reg_hdmiin_v_active_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1017  DefineRegister (0x2c09, "reg_hdmiin_video_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1018  DefineRegister (0x2c0a, "reg_hdmiin_horizontal_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1019  DefineRegister (0x2c0b, "reg_hdmiin_hblank_data0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1020  DefineRegister (0x2c0c, "reg_hdmiin_hblank_data1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1021  DefineRegister (0x2c0d, "reg_hdmiin_vertical_data_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1022  DefineRegister (0x2c0e, "reg_hdmiin_vertical_data_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1023  DefineRegister (0x2c0f, "reg_hdmiin_color_depth", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1024  DefineRegister (0x2c12, "reg_hdmiin_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1025  DefineRegister (0x2c13, "reg_hdmiin_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1026  DefineRegister (0x2c14, "reg_hdmiin_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
1027 
1028  DefineRegister (0x3000, "reg_hdmiin_i2c_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1029  DefineRegister (0x3001, "reg_hdmiin_i2c_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1030  DefineRegister (0x3002, "reg_hdmiin_video_setup", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1031  DefineRegister (0x3003, "reg_hdmiin_hsync_duration", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1032  DefineRegister (0x3004, "reg_hdmiin_h_active", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1033  DefineRegister (0x3005, "reg_hdmiin_vsync_duration_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1034  DefineRegister (0x3006, "reg_hdmiin_vsync_duration_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1035  DefineRegister (0x3007, "reg_hdmiin_v_active_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1036  DefineRegister (0x3008, "reg_hdmiin_v_active_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1037  DefineRegister (0x3009, "reg_hdmiin_video_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1038  DefineRegister (0x300a, "reg_hdmiin_horizontal_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1039  DefineRegister (0x300b, "reg_hdmiin_hblank_data0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1040  DefineRegister (0x300c, "reg_hdmiin_hblank_data1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1041  DefineRegister (0x300d, "reg_hdmiin_vertical_data_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1042  DefineRegister (0x300e, "reg_hdmiin_vertical_data_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1043  DefineRegister (0x300f, "reg_hdmiin_color_depth", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1044  DefineRegister (0x3012, "reg_hdmiin_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1045  DefineRegister (0x3013, "reg_hdmiin_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1046  DefineRegister (0x3014, "reg_hdmiin_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
1047 
1048  DefineRegister (0x1d40, "reg_hdmiout4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1049  DefineRegister (0x1d41, "reg_hdmiout4_videosetup0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1050  DefineRegister (0x1d42, "reg_hdmiout4_videosetup1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1051  DefineRegister (0x1d43, "reg_hdmiout4_videosetup2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1052  DefineRegister (0x1d44, "reg_hdmiout4_videosetup3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1053  DefineRegister (0x1d45, "reg_hdmiout4_videosetup4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1054  DefineRegister (0x1d46, "reg_hdmiout4_videosetup5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1055  DefineRegister (0x1d47, "reg_hdmiout4_videosetup6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1056  DefineRegister (0x1d48, "reg_hdmiout4_videosetup7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1057  DefineRegister (0x1d49, "reg_hdmiout4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1058  DefineRegister (0x1d4b, "reg_hdmiout4_audiocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1059  DefineRegister (0x1d4f, "reg_hdmiout4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1060  DefineRegister (0x1d50, "reg_hdmiout4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1061  DefineRegister (0x1d51, "reg_hdmiout4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1062  DefineRegister (0x1d52, "reg_hdmiout4_txclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1063  DefineRegister (0x1d53, "reg_hdmiout4_fpllclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1064  DefineRegister (0x1d54, "reg_hdmiout4_audio_cts1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1065  DefineRegister (0x1d55, "reg_hdmiout4_audio_cts2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1066  DefineRegister (0x1d56, "reg_hdmiout4_audio_cts3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1067  DefineRegister (0x1d57, "reg_hdmiout4_audio_cts4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1068  DefineRegister (0x1d58, "reg_hdmiout4_audio_n", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1069  DefineRegister (0x1d5e, "reg_hdmiout4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1070  DefineRegister (0x1d5f, "reg_hdmiout4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1071  DefineRegister (0x1d60, "reg_hdmiout4_i2ccontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1072  DefineRegister (0x1d61, "reg_hdmiout4_i2cedid", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1073 
1074  DefineRegister (0x1d80, "reg_hdmiout4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1075  DefineRegister (0x1d81, "reg_hdmiout4_videosetup0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1076  DefineRegister (0x1d82, "reg_hdmiout4_videosetup1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1077  DefineRegister (0x1d83, "reg_hdmiout4_videosetup2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1078  DefineRegister (0x1d84, "reg_hdmiout4_videosetup3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1079  DefineRegister (0x1d85, "reg_hdmiout4_videosetup4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1080  DefineRegister (0x1d86, "reg_hdmiout4_videosetup5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1081  DefineRegister (0x1d87, "reg_hdmiout4_videosetup6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1082  DefineRegister (0x1d88, "reg_hdmiout4_videosetup7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1083  DefineRegister (0x1d89, "reg_hdmiout4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1084  DefineRegister (0x1d8b, "reg_hdmiout4_audiocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1085  DefineRegister (0x1d8f, "reg_hdmiout4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1086  DefineRegister (0x1d90, "reg_hdmiout4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1087  DefineRegister (0x1d91, "reg_hdmiout4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1088  DefineRegister (0x1d92, "reg_hdmiout4_txclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1089  DefineRegister (0x1d93, "reg_hdmiout4_fpllclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1090  DefineRegister (0x1d94, "reg_hdmiout4_audio_cts1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1091  DefineRegister (0x1d95, "reg_hdmiout4_audio_cts2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1092  DefineRegister (0x1d96, "reg_hdmiout4_audio_cts3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1093  DefineRegister (0x1d97, "reg_hdmiout4_audio_cts4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1094  DefineRegister (0x1d98, "reg_hdmiout4_audio_n", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1095  DefineRegister (0x1d9e, "reg_hdmiout4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1096  DefineRegister (0x1d9f, "reg_hdmiout4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1097  DefineRegister (0x1da0, "reg_hdmiout4_i2ccontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1098  DefineRegister (0x1da1, "reg_hdmiout4_i2cedid", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel2);
1099  }
1100 
1101  void SetupSDIErrorRegs(void)
1102  {
1103  static const ULWord baseNum[] = {kRegRXSDI1Status, kRegRXSDI2Status, kRegRXSDI3Status, kRegRXSDI4Status, kRegRXSDI5Status, kRegRXSDI6Status, kRegRXSDI7Status, kRegRXSDI8Status};
1104  static const string suffixes [] = {"Status", "CRCErrorCount", "FrameCountLow", "FrameCountHigh", "FrameRefCountLow", "FrameRefCountHigh"};
1105  static const int perms [] = {READWRITE, READWRITE, READWRITE, READWRITE, READONLY, READONLY};
1106 
1107  AJAAutoLock lock(&mGuardMutex);
1108  for (ULWord chan (0); chan < 8; chan++)
1109  for (UWord ndx(0); ndx < 6; ndx++)
1110  {
1111  ostringstream ossName; ossName << "kRegRXSDI" << DEC(chan+1) << suffixes[ndx];
1112  const string & regName (ossName.str());
1113  const uint32_t regNum (baseNum[chan] + ndx);
1114  const int perm (perms[ndx]);
1115  if (ndx == 0)
1116  DefineRegister (regNum, regName, mSDIErrorStatusRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1117  else if (ndx == 1)
1118  DefineRegister (regNum, regName, mSDIErrorCountRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1119  else
1120  DefineRegister (regNum, regName, mDefaultRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1121  }
1122  DefineRegister (kRegRXSDIFreeRunningClockLow, "kRegRXSDIFreeRunningClockLow", mDefaultRegDecoder, READONLY, kRegClass_SDIError, kRegClass_NULL, kRegClass_NULL);
1123  DefineRegister (kRegRXSDIFreeRunningClockHigh, "kRegRXSDIFreeRunningClockHigh", mDefaultRegDecoder, READONLY, kRegClass_SDIError, kRegClass_NULL, kRegClass_NULL);
1124  } // SetupSDIErrorRegs
1125 
1126  void SetupLUTRegs (void)
1127  {
1128  AJAAutoLock lock(&mGuardMutex);
1129  }
1130 
1131  void SetupCSCRegs(void)
1132  {
1133  static const string sChan[8] = {kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3, kRegClass_Channel4, kRegClass_Channel5, kRegClass_Channel6, kRegClass_Channel7, kRegClass_Channel8};
1134 
1135  AJAAutoLock lock(&mGuardMutex);
1136  for (unsigned num(0); num < 8; num++)
1137  {
1138  ostringstream ossRegName; ossRegName << "kRegEnhancedCSC" << (num+1);
1139  const string & chanClass (sChan[num]); const string rootName (ossRegName.str());
1140  const string modeName (rootName + "Mode"); const string inOff01Name (rootName + "InOffset0_1"); const string inOff2Name (rootName + "InOffset2");
1141  const string coeffA0Name (rootName + "CoeffA0"); const string coeffA1Name (rootName + "CoeffA1"); const string coeffA2Name (rootName + "CoeffA2");
1142  const string coeffB0Name (rootName + "CoeffB0"); const string coeffB1Name (rootName + "CoeffB1"); const string coeffB2Name (rootName + "CoeffB2");
1143  const string coeffC0Name (rootName + "CoeffC0"); const string coeffC1Name (rootName + "CoeffC1"); const string coeffC2Name (rootName + "CoeffC2");
1144  const string outOffABName(rootName + "OutOffsetA_B"); const string outOffCName (rootName + "OutOffsetC");
1145  const string keyModeName (rootName + "KeyMode"); const string keyClipOffName (rootName + "KeyClipOffset"); const string keyGainName (rootName + "KeyGain");
1146  DefineRegister (64*num + kRegEnhancedCSC1Mode, modeName, mEnhCSCModeDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1147  DefineRegister (64*num + kRegEnhancedCSC1InOffset0_1, inOff01Name, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1148  DefineRegister (64*num + kRegEnhancedCSC1InOffset2, inOff2Name, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1149  DefineRegister (64*num + kRegEnhancedCSC1CoeffA0, coeffA0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1150  DefineRegister (64*num + kRegEnhancedCSC1CoeffA1, coeffA1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1151  DefineRegister (64*num + kRegEnhancedCSC1CoeffA2, coeffA2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1152  DefineRegister (64*num + kRegEnhancedCSC1CoeffB0, coeffB0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1153  DefineRegister (64*num + kRegEnhancedCSC1CoeffB1, coeffB1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1154  DefineRegister (64*num + kRegEnhancedCSC1CoeffB2, coeffB2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1155  DefineRegister (64*num + kRegEnhancedCSC1CoeffC0, coeffC0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1156  DefineRegister (64*num + kRegEnhancedCSC1CoeffC1, coeffC1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1157  DefineRegister (64*num + kRegEnhancedCSC1CoeffC2, coeffC2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1158  DefineRegister (64*num + kRegEnhancedCSC1OutOffsetA_B, outOffABName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1159  DefineRegister (64*num + kRegEnhancedCSC1OutOffsetC, outOffCName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1160  DefineRegister (64*num + kRegEnhancedCSC1KeyMode, keyModeName, mEnhCSCKeyModeDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1161  DefineRegister (64*num + kRegEnhancedCSC1KeyClipOffset, keyClipOffName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1162  DefineRegister (64*num + kRegEnhancedCSC1KeyGain, keyGainName, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1163  }
1164  static const NTV2RegisterNumber sECSCRegs[8][5] = { { kRegCSCoefficients1_2, kRegCSCoefficients3_4, kRegCSCoefficients5_6, kRegCSCoefficients7_8, kRegCSCoefficients9_10 },
1165  { kRegCS2Coefficients1_2, kRegCS2Coefficients3_4, kRegCS2Coefficients5_6, kRegCS2Coefficients7_8, kRegCS2Coefficients9_10 },
1166  { kRegCS3Coefficients1_2, kRegCS3Coefficients3_4, kRegCS3Coefficients5_6, kRegCS3Coefficients7_8, kRegCS3Coefficients9_10 },
1167  { kRegCS4Coefficients1_2, kRegCS4Coefficients3_4, kRegCS4Coefficients5_6, kRegCS4Coefficients7_8, kRegCS4Coefficients9_10 },
1168  { kRegCS5Coefficients1_2, kRegCS5Coefficients3_4, kRegCS5Coefficients5_6, kRegCS5Coefficients7_8, kRegCS5Coefficients9_10 },
1169  { kRegCS6Coefficients1_2, kRegCS6Coefficients3_4, kRegCS6Coefficients5_6, kRegCS6Coefficients7_8, kRegCS6Coefficients9_10 },
1170  { kRegCS7Coefficients1_2, kRegCS7Coefficients3_4, kRegCS7Coefficients5_6, kRegCS7Coefficients7_8, kRegCS7Coefficients9_10 },
1171  { kRegCS8Coefficients1_2, kRegCS8Coefficients3_4, kRegCS8Coefficients5_6, kRegCS8Coefficients7_8, kRegCS8Coefficients9_10 } };
1172  for (unsigned chan(0); chan < 8; chan++)
1173  {
1174  const string & chanClass (sChan[chan]);
1175  DefineRegister (sECSCRegs[chan][0], "", mCSCoeff1234Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1176  DefineRegister (sECSCRegs[chan][1], "", mCSCoeff1234Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1177  DefineRegister (sECSCRegs[chan][2], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1178  DefineRegister (sECSCRegs[chan][3], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1179  DefineRegister (sECSCRegs[chan][4], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1180  }
1181 
1182  // LUT/ColorCorrection Registers...
1183  DefineRegister (kRegCh1ColorCorrectionControl, "", mLUTV1ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1184  DefineRegister (kRegCh2ColorCorrectionControl, "", mLUTV1ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1185  DefineRegister (kRegLUTV2Control, "", mLUTV2ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1186  // LUT tables...
1187 #if 1 // V2 tables need the appropriate Enable & Bank bits set in kRegLUTV2Control, otherwise they'll always readback zero!
1188  // So it's kinda pointless to read/decode them unless we do the "bank-select" dance immediately before reading them...
1189  const ULWord REDreg(kColorCorrectionLUTOffset_Red/4), GRNreg(kColorCorrectionLUTOffset_Green/4), BLUreg(kColorCorrectionLUTOffset_Blue/4);
1190  for (ULWord ndx(0); ndx < 512; ndx++)
1191  {
1192  ostringstream regNameR, regNameG, regNameB;
1193  regNameR << "kRegLUTRed" << DEC0N(ndx,3); regNameG << "kRegLUTGreen" << DEC0N(ndx,3); regNameB << "kRegLUTBlue" << DEC0N(ndx,3);
1194  DefineRegister (REDreg + ndx, regNameR.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1195  DefineRegister (GRNreg + ndx, regNameG.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1196  DefineRegister (BLUreg + ndx, regNameB.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1197  }
1198 #endif
1199  } // SetupCSCRegs
1200 
1201  void SetupMixerKeyerRegs(void)
1202  {
1203  AJAAutoLock lock(&mGuardMutex);
1204  // VidProc/Mixer/Keyer
1205  DefineRegister (kRegVidProc1Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1206  DefineRegister (kRegVidProc2Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1207  DefineRegister (kRegVidProc3Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1208  DefineRegister (kRegVidProc4Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1209  DefineRegister (kRegSplitControl, "", mSplitControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_NULL);
1210  DefineRegister (kRegFlatMatteValue, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1211  DefineRegister (kRegFlatMatte2Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1212  DefineRegister (kRegFlatMatte3Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1213  DefineRegister (kRegFlatMatte4Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1214  DefineRegister (kRegMixer1Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1215  DefineRegister (kRegMixer2Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1216  DefineRegister (kRegMixer3Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1217  DefineRegister (kRegMixer4Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1218  }
1219 
1220  void SetupNTV4FrameStoreRegs(void)
1221  {
1222  for (ULWord fsNdx(0); fsNdx < 4; fsNdx++)
1223  {
1224  for (ULWord regNdx(0); regNdx < ULWord(regNTV4FS_LAST); regNdx++)
1225  {
1226  ostringstream regName; regName << "kRegNTV4FS" << DEC(fsNdx+1) << "_";
1227  const ULWord registerNumber (kNTV4FrameStoreFirstRegNum + fsNdx * kNumNTV4FrameStoreRegisters + regNdx);
1228  switch (NTV4FrameStoreRegs(regNdx))
1229  {
1230  case regNTV4FS_LineLengthPitch:
1231  case regNTV4FS_ROIVHSize:
1232  case regNTV4FS_ROIF1StartAddr:
1233  case regNTV4FS_ROIF2StartAddr:
1234  case regNTV4FS_ROIF1VHOffsets:
1235  case regNTV4FS_ROIF2VHOffsets:
1236  case regNTV4FS_DisplayHorzPixelsPerLine:
1237  case regNTV4FS_DisplayFID:
1238  case regNTV4FS_F1ActiveLines:
1239  case regNTV4FS_F2ActiveLines:
1240  case regNTV4FS_RasterControl:
1241  case regNTV4FS_RasterPixelSkip:
1242  case regNTV4FS_RasterVideoFill_YCb_GB:
1243  case regNTV4FS_RasterVideoFill_Cr_AR:
1244  case regNTV4FS_RasterROIFillAlpha:
1245  case regNTV4FS_Status:
1246  case regNTV4FS_RasterOutputTimingPreset:
1247  case regNTV4FS_RasterVTotalLines:
1248  case regNTV4FS_RasterSmpteFramePulse:
1249  case regNTV4FS_RasterOddLineStartAddress:
1250  case regNTV4FS_RasterOffsetBlue:
1251  case regNTV4FS_RasterOffsetRed:
1252  case regNTV4FS_RasterOffsetAlpha:
1253  regName << sNTV4FrameStoreRegNames[regNdx];
1254  DefineRegister(registerNumber, regName.str(), mDecodeNTV4FSReg, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1255  break;
1256  case regNTV4FS_InputSourceSelect:
1257  regName << "InputSourceSelect";
1258  DefineRegister(registerNumber, regName.str(), mDecodeNTV4FSReg, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1259  break;
1260  default:
1261  regName << DEC(regNdx);
1262  DefineRegister(registerNumber, regName.str(), mDefaultRegDecoder, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1263  break;
1264  }
1265  } // for each FrameStore register
1266  } // for each FrameStore widget
1267  }
1268 
1269  void SetupVRegs(void)
1270  {
1271  AJAAutoLock lock(&mGuardMutex);
1272  DEF_REG (kVRegDriverVersion, mDriverVersionDecoder, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1273  DEF_REGNAME (kVRegRelativeVideoPlaybackDelay);
1274  DEF_REGNAME (kVRegAudioRecordPinDelay);
1275  DEF_REGNAME (kVRegGlobalAudioPlaybackMode);
1276  DEF_REGNAME (kVRegFlashProgramKey);
1277  DEF_REGNAME (kVRegStrictTiming);
1278  DEF_REG (kVRegDriverType, mDecodeDriverType, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1279  DEF_REGNAME (kVRegInputSelect);
1280  DEF_REGNAME (kVRegSecondaryFormatSelect);
1281  DEF_REGNAME (kVRegDigitalOutput1Select);
1282  DEF_REGNAME (kVRegDigitalOutput2Select);
1283  DEF_REGNAME (kVRegAnalogOutputSelect);
1284  DEF_REGNAME (kVRegAnalogOutputType);
1285  DEF_REGNAME (kVRegAnalogOutBlackLevel);
1286  DEF_REGNAME (kVRegInputSelectUser);
1287  DEF_REGNAME (kVRegVideoOutPauseMode);
1288  DEF_REGNAME (kVRegPulldownPattern);
1289  DEF_REGNAME (kVRegColorSpaceMode);
1290  DEF_REGNAME (kVRegGammaMode);
1291  DEF_REGNAME (kVRegLUTType);
1292  DEF_REGNAME (kVRegRGB10Range);
1293  DEF_REGNAME (kVRegRGB10Endian);
1294  DEF_REGNAME (kVRegFanControl);
1295  DEF_REGNAME (kVRegBitFileDownload);
1296  DEF_REGNAME (kVRegSaveRegistersToRegistry);
1297  DEF_REGNAME (kVRegRecallRegistersFromRegistry);
1298  DEF_REGNAME (kVRegClearAllSubscriptions);
1299  DEF_REGNAME (kVRegRestoreHardwareProcampRegisters);
1300  DEF_REGNAME (kVRegAcquireReferenceCount);
1301  DEF_REGNAME (kVRegReleaseReferenceCount);
1302  DEF_REGNAME (kVRegDTAudioMux0);
1303  DEF_REGNAME (kVRegDTAudioMux1);
1304  DEF_REGNAME (kVRegDTAudioMux2);
1305  DEF_REGNAME (kVRegDTFirmware);
1306  DEF_REGNAME (kVRegDTVersionAja);
1307  DEF_REGNAME (kVRegDTVersionDurian);
1308  DEF_REGNAME (kVRegDTAudioCapturePinConnected);
1309  DEF_REGNAME (kVRegTimeStampMode);
1310  DEF_REGNAME (kVRegTimeStampLastOutputVerticalLo);
1311  DEF_REGNAME (kVRegTimeStampLastOutputVerticalHi);
1312  DEF_REGNAME (kVRegTimeStampLastInput1VerticalLo);
1313  DEF_REGNAME (kVRegTimeStampLastInput1VerticalHi);
1314  DEF_REGNAME (kVRegTimeStampLastInput2VerticalLo);
1315  DEF_REGNAME (kVRegTimeStampLastInput2VerticalHi);
1316  DEF_REGNAME (kVRegNumberVideoMappingRegisters);
1317  DEF_REGNAME (kVRegNumberAudioMappingRegisters);
1318  DEF_REGNAME (kVRegAudioSyncTolerance);
1319  DEF_REGNAME (kVRegDmaSerialize);
1320  DEF_REGNAME (kVRegSyncChannel);
1321  DEF_REGNAME (kVRegSyncChannels);
1322  DEF_REGNAME (kVRegSoftwareUartFifo);
1323  DEF_REGNAME (kVRegTimeCodeCh1Delay);
1324  DEF_REGNAME (kVRegTimeCodeCh2Delay);
1325  DEF_REGNAME (kVRegTimeCodeIn1Delay);
1326  DEF_REGNAME (kVRegTimeCodeIn2Delay);
1327  DEF_REGNAME (kVRegTimeCodeCh3Delay);
1328  DEF_REGNAME (kVRegTimeCodeCh4Delay);
1329  DEF_REGNAME (kVRegTimeCodeIn3Delay);
1330  DEF_REGNAME (kVRegTimeCodeIn4Delay);
1331  DEF_REGNAME (kVRegTimeCodeCh5Delay);
1332  DEF_REGNAME (kVRegTimeCodeIn5Delay);
1333  DEF_REGNAME (kVRegTimeCodeCh6Delay);
1334  DEF_REGNAME (kVRegTimeCodeIn6Delay);
1335  DEF_REGNAME (kVRegTimeCodeCh7Delay);
1336  DEF_REGNAME (kVRegTimeCodeIn7Delay);
1337  DEF_REGNAME (kVRegTimeCodeCh8Delay);
1338  DEF_REGNAME (kVRegTimeCodeIn8Delay);
1339  DEF_REGNAME (kVRegDebug1);
1340  DEF_REGNAME (kVRegDebugLastFormat);
1341  DEF_REGNAME (kVRegDebugIPConfigTimeMS);
1342  DEF_REGNAME (kVRegDisplayReferenceSelect);
1343  DEF_REGNAME (kVRegVANCMode);
1344  DEF_REGNAME (kVRegDualStreamTransportType);
1345  DEF_REGNAME (kVRegDSKMode);
1346  DEF_REGNAME (kVRegIsoConvertEnable);
1347  DEF_REGNAME (kVRegDSKAudioMode);
1348  DEF_REGNAME (kVRegDSKForegroundMode);
1349  DEF_REGNAME (kVRegDSKForegroundFade);
1350  DEF_REGNAME (kVRegCaptureReferenceSelect);
1351  DEF_REGNAME (kVRegUnfilterAnc);
1352  DEF_REGNAME (kVRegSDIOutput1RGBRange);
1353  DEF_REGNAME (kVRegSDIInput1FormatSelect);
1354  DEF_REGNAME (kVRegSDIInput2FormatSelect);
1355  DEF_REGNAME (kVRegSDIInput1RGBRange);
1356  DEF_REGNAME (kVRegSDIInput2RGBRange);
1357  DEF_REGNAME (kVRegSDIInput1Stereo3DMode);
1358  DEF_REGNAME (kVRegSDIInput2Stereo3DMode);
1359  DEF_REGNAME (kVRegFrameBuffer1RGBRange);
1360  DEF_REGNAME (kVRegFrameBuffer1Stereo3DMode);
1361  DEF_REGNAME (kVRegHDMIInRgbRange);
1362  DEF_REGNAME (kVRegHDMIOutRgbRange);
1363  DEF_REGNAME (kVRegAnalogInBlackLevel);
1364  DEF_REGNAME (kVRegAnalogInputType);
1365  DEF_REGNAME (kVRegHDMIOutColorSpaceModeCtrl);
1366  DEF_REGNAME (kVRegHDMIOutProtocolMode);
1367  DEF_REGNAME (kVRegHDMIOutStereoSelect);
1368  DEF_REGNAME (kVRegHDMIOutStereoCodecSelect);
1369  DEF_REGNAME (kVRegHdmiOutSubSample);
1370  DEF_REGNAME (kVRegSDIInput1ColorSpaceMode);
1371  DEF_REGNAME (kVRegSDIInput2ColorSpaceMode);
1372  DEF_REGNAME (kVRegSDIOutput2RGBRange);
1373  DEF_REGNAME (kVRegSDIOutput1Stereo3DMode);
1374  DEF_REGNAME (kVRegSDIOutput2Stereo3DMode);
1375  DEF_REGNAME (kVRegFrameBuffer2RGBRange);
1376  DEF_REGNAME (kVRegFrameBuffer2Stereo3DMode);
1377  DEF_REGNAME (kVRegAudioGainDisable);
1378  DEF_REGNAME (kVRegLTCOnRefInSelect);
1379  DEF_REGNAME (kVRegActiveVideoOutFilter);
1380  DEF_REGNAME (kVRegAudioInputMapSelect);
1381  DEF_REGNAME (kVRegAudioInputDelay);
1382  DEF_REGNAME (kVRegDSKGraphicFileIndex);
1383  DEF_REGNAME (kVRegTimecodeBurnInMode);
1384  DEF_REGNAME (kVRegUseQTTimecode);
1385  DEF_REGNAME (kVRegAvailable164);
1386  DEF_REGNAME (kVRegRP188SourceSelect);
1387  DEF_REGNAME (kVRegQTCodecModeDebug);
1388  DEF_REGNAME (kVRegHDMIOutColorSpaceModeStatus);
1389  DEF_REGNAME (kVRegDeviceOnline);
1390  DEF_REGNAME (kVRegIsDefaultDevice);
1391  DEF_REGNAME (kVRegDesktopFrameBufferStatus);
1392  DEF_REGNAME (kVRegSDIOutput1ColorSpaceMode);
1393  DEF_REGNAME (kVRegSDIOutput2ColorSpaceMode);
1394  DEF_REGNAME (kVRegAudioOutputDelay);
1395  DEF_REGNAME (kVRegTimelapseEnable);
1396  DEF_REGNAME (kVRegTimelapseCaptureValue);
1397  DEF_REGNAME (kVRegTimelapseCaptureUnits);
1398  DEF_REGNAME (kVRegTimelapseIntervalValue);
1399  DEF_REGNAME (kVRegTimelapseIntervalUnits);
1400  DEF_REGNAME (kVRegSDIOutConfig);
1401  DEF_REGNAME (kVRegAnalogInStandard);
1402  DEF_REGNAME (kVRegOutputTimecodeOffset);
1403  DEF_REGNAME (kVRegOutputTimecodeType);
1404  DEF_REGNAME (kVRegQuicktimeUsingBoard);
1405  DEF_REGNAME (kVRegApplicationPID);
1406  DEF_REG (kVRegApplicationCode, mDecodeFourCC, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1407  DEF_REGNAME (kVRegReleaseApplication);
1408  DEF_REGNAME (kVRegForceApplicationPID);
1409  DEF_REGNAME (kVRegForceApplicationCode);
1410  DEF_REGNAME (kVRegIpConfigStreamRefresh);
1411  DEF_REGNAME (kVRegSDIInConfig);
1412  DEF_REGNAME (kVRegInputChangedCount);
1413  DEF_REGNAME (kVReg8kOutputTransportSelection);
1414  DEF_REGNAME (kVRegAnalogIoSelect);
1415  DEF_REGNAME (kVRegProcAmpSDRegsInitialized);
1416  DEF_REGNAME (kVRegProcAmpStandardDefBrightness);
1417  DEF_REGNAME (kVRegProcAmpStandardDefContrast);
1418  DEF_REGNAME (kVRegProcAmpStandardDefSaturation);
1419  DEF_REGNAME (kVRegProcAmpStandardDefHue);
1420  DEF_REGNAME (kVRegProcAmpStandardDefCbOffset);
1421  DEF_REGNAME (kVRegProcAmpStandardDefCrOffset);
1422  DEF_REGNAME (kVRegProcAmpEndStandardDefRange);
1423  DEF_REGNAME (kVRegProcAmpHDRegsInitialized);
1424  DEF_REGNAME (kVRegProcAmpHighDefBrightness);
1425  DEF_REGNAME (kVRegProcAmpHighDefContrast);
1426  DEF_REGNAME (kVRegProcAmpHighDefSaturationCb);
1427  DEF_REGNAME (kVRegProcAmpHighDefSaturationCr);
1428  DEF_REGNAME (kVRegProcAmpHighDefHue);
1429  DEF_REGNAME (kVRegProcAmpHighDefCbOffset);
1430  DEF_REGNAME (kVRegProcAmpHighDefCrOffset);
1431  DEF_REGNAME (kVRegProcAmpEndHighDefRange);
1432  DEF_REGNAME (kVRegChannel1UserBufferLevel);
1433  DEF_REGNAME (kVRegChannel2UserBufferLevel);
1434  DEF_REGNAME (kVRegInput1UserBufferLevel);
1435  DEF_REGNAME (kVRegInput2UserBufferLevel);
1436  DEF_REGNAME (kVRegProgressivePicture);
1437  DEF_REGNAME (kVRegLUT2Type);
1438  DEF_REGNAME (kVRegLUT3Type);
1439  DEF_REGNAME (kVRegLUT4Type);
1440  DEF_REGNAME (kVRegDigitalOutput3Select);
1441  DEF_REGNAME (kVRegDigitalOutput4Select);
1442  DEF_REGNAME (kVRegHDMIOutputSelect);
1443  DEF_REGNAME (kVRegRGBRangeConverterLUTType);
1444  DEF_REGNAME (kVRegTestPatternChoice);
1445  DEF_REGNAME (kVRegTestPatternFormat);
1446  DEF_REGNAME (kVRegEveryFrameTaskFilter);
1447  DEF_REGNAME (kVRegDefaultInput);
1448  DEF_REGNAME (kVRegDefaultVideoOutMode);
1449  DEF_REGNAME (kVRegDefaultVideoFormat);
1450  DEF_REGNAME (kVRegDigitalOutput5Select);
1451  DEF_REGNAME (kVRegLUT5Type);
1452  DEF_REGNAME (kVRegMacUserModeDebugLevel);
1453  DEF_REGNAME (kVRegMacKernelModeDebugLevel);
1454  DEF_REGNAME (kVRegMacUserModePingLevel);
1455  DEF_REGNAME (kVRegMacKernelModePingLevel);
1456  DEF_REGNAME (kVRegLatencyTimerValue);
1457  DEF_REGNAME (kVRegAudioInputSelect);
1458  DEF_REGNAME (kVRegSerialSuspended);
1459  DEF_REGNAME (kVRegXilinxProgramming);
1460  DEF_REGNAME (kVRegETTDiagLastSerialTimestamp);
1461  DEF_REGNAME (kVRegETTDiagLastSerialTimecode);
1462  DEF_REGNAME (kVRegStartupStatusFlags);
1463  DEF_REGNAME (kVRegRGBRangeMode);
1464  DEF_REGNAME (kVRegEnableQueuedDMAs);
1465  DEF_REGNAME (kVRegBA0MemorySize);
1466  DEF_REGNAME (kVRegBA1MemorySize);
1467  DEF_REGNAME (kVRegBA4MemorySize);
1468  DEF_REGNAME (kVRegNumDmaDriverBuffers);
1469  DEF_REGNAME (kVRegDMADriverBufferPhysicalAddress);
1470  DEF_REGNAME (kVRegBA2MemorySize);
1471  DEF_REGNAME (kVRegAcquireLinuxReferenceCount);
1472  DEF_REGNAME (kVRegReleaseLinuxReferenceCount);
1473  DEF_REGNAME (kVRegAdvancedIndexing);
1474  DEF_REGNAME (kVRegTimeStampLastInput3VerticalLo);
1475  DEF_REGNAME (kVRegTimeStampLastInput3VerticalHi);
1476  DEF_REGNAME (kVRegTimeStampLastInput4VerticalLo);
1477  DEF_REGNAME (kVRegTimeStampLastInput4VerticalHi);
1478  DEF_REGNAME (kVRegTimeStampLastInput5VerticalLo);
1479  DEF_REGNAME (kVRegTimeStampLastInput5VerticalHi);
1480  DEF_REGNAME (kVRegTimeStampLastInput6VerticalLo);
1481  DEF_REGNAME (kVRegTimeStampLastInput6VerticalHi);
1482  DEF_REGNAME (kVRegTimeStampLastInput7VerticalLo);
1483  DEF_REGNAME (kVRegTimeStampLastInput7VerticalHi);
1484  DEF_REGNAME (kVRegTimeStampLastInput8VerticalLo);
1485  DEF_REGNAME (kVRegTimeStampLastInput8VerticalHi);
1486  DEF_REGNAME (kVRegTimeStampLastOutput2VerticalLo);
1487  DEF_REGNAME (kVRegTimeStampLastOutput2VerticalHi);
1488  DEF_REGNAME (kVRegTimeStampLastOutput3VerticalLo);
1489  DEF_REGNAME (kVRegTimeStampLastOutput3VerticalHi);
1490  DEF_REGNAME (kVRegTimeStampLastOutput4VerticalLo);
1491  DEF_REGNAME (kVRegTimeStampLastOutput4VerticalHi);
1492  DEF_REGNAME (kVRegTimeStampLastOutput5VerticalLo);
1493  DEF_REGNAME (kVRegTimeStampLastOutput5VerticalHi);
1494  DEF_REGNAME (kVRegTimeStampLastOutput6VerticalLo);
1495  DEF_REGNAME (kVRegTimeStampLastOutput6VerticalHi);
1496  DEF_REGNAME (kVRegTimeStampLastOutput7VerticalLo);
1497  DEF_REGNAME (kVRegTimeStampLastOutput7VerticalHi);
1498  DEF_REGNAME (kVRegTimeStampLastOutput8VerticalLo);
1499  DEF_REGNAME (kVRegResetCycleCount);
1500  DEF_REGNAME (kVRegUseProgressive);
1501  DEF_REGNAME (kVRegFlashSize);
1502  DEF_REGNAME (kVRegFlashStatus);
1503  DEF_REGNAME (kVRegFlashState);
1504  DEF_REGNAME (kVRegPCIDeviceID);
1505  DEF_REGNAME (kVRegUartRxFifoSize);
1506  DEF_REGNAME (kVRegEFTNeedsUpdating);
1507  DEF_REGNAME (kVRegSuspendSystemAudio);
1508  DEF_REGNAME (kVRegAcquireReferenceCounter);
1509  DEF_REGNAME (kVRegTimeStampLastOutput8VerticalHi);
1510  DEF_REGNAME (kVRegFramesPerVertical);
1511  DEF_REGNAME (kVRegServicesInitialized);
1512  DEF_REGNAME (kVRegFrameBufferGangCount);
1513  DEF_REGNAME (kVRegChannelCrosspointFirst);
1514  DEF_REGNAME (kVRegChannelCrosspointLast);
1515  DEF_REGNAME (kVRegMonAncField1Offset);
1516  DEF_REGNAME (kVRegMonAncField2Offset);
1517  DEF_REGNAME (kVRegFollowInputFormat);
1518  DEF_REG (kVRegAncField1Offset, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1519  DEF_REG (kVRegAncField2Offset, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1520  DEF_REGNAME (kVRegAgentCheck);
1521  DEF_REGNAME (kVReg4kOutputTransportSelection);
1522  DEF_REG (kVRegCustomAncInputSelect, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1523  DEF_REGNAME (kVRegUseThermostat);
1524  DEF_REGNAME (kVRegThermalSamplingRate);
1525  DEF_REGNAME (kVRegFanSpeed);
1526  DEF_REGNAME (kVRegVideoFormatCh1);
1527  DEF_REGNAME (kVRegVideoFormatCh2);
1528  DEF_REGNAME (kVRegVideoFormatCh3);
1529  DEF_REGNAME (kVRegVideoFormatCh4);
1530  DEF_REGNAME (kVRegVideoFormatCh5);
1531  DEF_REGNAME (kVRegVideoFormatCh6);
1532  DEF_REGNAME (kVRegVideoFormatCh7);
1533  DEF_REGNAME (kVRegVideoFormatCh8);
1534 
1535  DEF_REG (kVRegIPAddrEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1536  DEF_REG (kVRegSubnetEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1537  DEF_REG (kVRegGatewayEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1538  DEF_REG (kVRegIPAddrEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1539  DEF_REG (kVRegSubnetEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1540  DEF_REG (kVRegGatewayEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1541  DEF_REG (kVRegRxcEnable1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1542  DEF_REG (kVRegRxcSfp1RxMatch1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1543  DEF_REG (kVRegRxcSfp1SourceIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1544  DEF_REG (kVRegRxcSfp1DestIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1545  DEF_REG (kVRegRxcSfp1SourcePort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1546  DEF_REG (kVRegRxcSfp1DestPort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1547  DEF_REG (kVRegRxcSfp1Vlan1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1548  DEF_REG (kVRegRxcSfp2RxMatch1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1549  DEF_REG (kVRegRxcSfp2SourceIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1550  DEF_REG (kVRegRxcSfp2DestIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1551  DEF_REG (kVRegRxcSfp2SourcePort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1552  DEF_REG (kVRegRxcSfp2DestPort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1553  DEF_REG (kVRegRxcSfp2Vlan1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1554  DEF_REG (kVRegRxcSsrc1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1555  DEF_REG (kVRegRxcPlayoutDelay1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1556  DEF_REG (kVRegRxcEnable2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1557  DEF_REG (kVRegRxcSfp1RxMatch2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1558  DEF_REG (kVRegRxcSfp1SourceIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1559  DEF_REG (kVRegRxcSfp1DestIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1560  DEF_REG (kVRegRxcSfp1SourcePort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1561  DEF_REG (kVRegRxcSfp1DestPort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1562  DEF_REG (kVRegRxcSfp1Vlan2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1563  DEF_REG (kVRegRxcSfp2RxMatch2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1564  DEF_REG (kVRegRxcSfp2SourceIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1565  DEF_REG (kVRegRxcSfp2DestIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1566  DEF_REG (kVRegRxcSfp2SourcePort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1567  DEF_REG (kVRegRxcSfp2DestPort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1568  DEF_REG (kVRegRxcSfp2Vlan2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1569  DEF_REG (kVRegRxcSsrc2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1570  DEF_REG (kVRegRxcPlayoutDelay2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1571  DEF_REG (kVRegTxcEnable3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1572  DEF_REG (kVRegTxcSfp1LocalPort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1573  DEF_REG (kVRegTxcSfp1RemoteIp3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1574  DEF_REG (kVRegTxcSfp1RemotePort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1575  DEF_REG (kVRegTxcSfp2LocalPort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1576  DEF_REG (kVRegTxcSfp2RemoteIp3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1577  DEF_REG (kVRegTxcSfp2RemotePort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1578  DEF_REG (kVRegTxcEnable4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1579  DEF_REG (kVRegTxcSfp1LocalPort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1580  DEF_REG (kVRegTxcSfp1RemoteIp4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1581  DEF_REG (kVRegTxcSfp1RemotePort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1582  DEF_REG (kVRegTxcSfp2LocalPort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1583  DEF_REG (kVRegTxcSfp2RemoteIp4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1584  DEF_REG (kVRegTxcSfp2RemotePort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1585  DEF_REG (kVRegMailBoxAcquire, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1586  DEF_REG (kVRegMailBoxRelease, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1587  DEF_REG (kVRegMailBoxAbort, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1588  DEF_REG (kVRegMailBoxTimeoutNS, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1589  DEF_REG (kVRegRxc_2DecodeSelectionMode1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1590  DEF_REG (kVRegRxc_2DecodeProgramNumber1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1591  DEF_REG (kVRegRxc_2DecodeProgramPID1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1592  DEF_REG (kVRegRxc_2DecodeAudioNumber1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1593  DEF_REG (kVRegRxc_2DecodeSelectionMode2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1594  DEF_REG (kVRegRxc_2DecodeProgramNumber2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1595  DEF_REG (kVRegRxc_2DecodeProgramPID2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1596  DEF_REG (kVRegRxc_2DecodeAudioNumber2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1597  DEF_REG (kVRegTxc_2EncodeVideoFormat1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1598  DEF_REG (kVRegTxc_2EncodeUllMode1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1599  DEF_REG (kVRegTxc_2EncodeBitDepth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1600  DEF_REG (kVRegTxc_2EncodeChromaSubSamp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1601  DEF_REG (kVRegTxc_2EncodeMbps1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1602  DEF_REG (kVRegTxc_2EncodeAudioChannels1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1603  DEF_REG (kVRegTxc_2EncodeStreamType1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1604  DEF_REG (kVRegTxc_2EncodeProgramPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1605  DEF_REG (kVRegTxc_2EncodeVideoPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1606  DEF_REG (kVRegTxc_2EncodePcrPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1607  DEF_REG (kVRegTxc_2EncodeAudio1Pid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1608  DEF_REG (kVRegTxc_2EncodeVideoFormat2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1609  DEF_REG (kVRegTxc_2EncodeUllMode2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1610  DEF_REG (kVRegTxc_2EncodeBitDepth2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1611  DEF_REG (kVRegTxc_2EncodeChromaSubSamp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1612  DEF_REG (kVRegTxc_2EncodeMbps2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1613  DEF_REG (kVRegTxc_2EncodeAudioChannels2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1614  DEF_REG (kVRegTxc_2EncodeStreamType2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1615  DEF_REG (kVRegTxc_2EncodeProgramPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1616  DEF_REG (kVRegTxc_2EncodeVideoPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1617  DEF_REG (kVRegTxc_2EncodePcrPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1618  DEF_REG (kVRegTxc_2EncodeAudio1Pid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1619  DEF_REG (kVReg2022_7Enable, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1620  DEF_REG (kVReg2022_7NetworkPathDiff, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1621  DEF_REGNAME (kVRegKIPRxCfgError);
1622  DEF_REGNAME (kVRegKIPTxCfgError);
1623  DEF_REGNAME (kVRegKIPEncCfgError);
1624  DEF_REGNAME (kVRegKIPDecCfgError);
1625  DEF_REGNAME (kVRegKIPNetCfgError);
1626  DEF_REG (kVRegUseHDMI420Mode, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_NULL, kRegClass_NULL);
1627  DEF_REGNAME (kVRegUserDefinedDBB);
1628  DEF_REG (kVRegHDMIOutAudioChannels, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_HDMI, kRegClass_NULL);
1629  DEF_REG (kVRegZeroHostAncPostCapture, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1630  DEF_REG (kVRegZeroDeviceAncPostCapture, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1631  DEF_REG (kVRegAudioMonitorChannelSelect, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1632  DEF_REG (kVRegAudioMixerOverrideState, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1633  DEF_REG (kVRegAudioMixerSourceMainEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1634  DEF_REG (kVRegAudioMixerSourceAux1Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1635  DEF_REG (kVRegAudioMixerSourceAux2Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1636  DEF_REG (kVRegAudioMixerSourceMainGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1637  DEF_REG (kVRegAudioMixerSourceAux1Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1638  DEF_REG (kVRegAudioMixerSourceAux2Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1639  DEF_REG (kVRegAudioCapMixerSourceMainEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1640  DEF_REG (kVRegAudioCapMixerSourceAux1Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1641  DEF_REG (kVRegAudioCapMixerSourceAux2Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1642  DEF_REG (kVRegAudioCapMixerSourceMainGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1643  DEF_REG (kVRegAudioCapMixerSourceAux1Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1644  DEF_REG (kVRegAudioCapMixerSourceAux2Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1645  DEF_REGNAME (kVRegSwizzle4kInput);
1646  DEF_REGNAME (kVRegSwizzle4kOutput);
1647  DEF_REG (kVRegAnalogAudioIOConfiguration, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1648  DEF_REGNAME (kVRegHdmiHdrOutChanged);
1649  DEF_REGNAME (kVRegDisableAutoVPID);
1650  DEF_REGNAME (kVRegEnableBT2020);
1651  DEF_REGNAME (kVRegHdmiHdrOutMode);
1652  DEF_REGNAME (kVRegServicesForceInit);
1653  DEF_REGNAME (kVRegServicesModeFinal);
1654 
1655  DEF_REG (kVRegNTV2VPIDTransferCharacteristics1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1656  DEF_REG (kVRegNTV2VPIDColorimetry1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1657  DEF_REG (kVRegNTV2VPIDLuminance1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1658  DEF_REG (kVRegNTV2VPIDTransferCharacteristics, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1659  DEF_REG (kVRegNTV2VPIDColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1660  DEF_REG (kVRegNTV2VPIDLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1661 
1662  DEF_REG (kVRegNTV2VPIDTransferCharacteristics2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1663  DEF_REG (kVRegNTV2VPIDColorimetry2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1664  DEF_REG (kVRegNTV2VPIDLuminance2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1665 
1666  DEF_REG (kVRegNTV2VPIDTransferCharacteristics3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1667  DEF_REG (kVRegNTV2VPIDColorimetry3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1668  DEF_REG (kVRegNTV2VPIDLuminance3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1669 
1670  DEF_REG (kVRegNTV2VPIDTransferCharacteristics4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1671  DEF_REG (kVRegNTV2VPIDColorimetry4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1672  DEF_REG (kVRegNTV2VPIDLuminance4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1673 
1674  DEF_REG (kVRegNTV2VPIDTransferCharacteristics5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1675  DEF_REG (kVRegNTV2VPIDColorimetry5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1676  DEF_REG (kVRegNTV2VPIDLuminance5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1677 
1678  DEF_REG (kVRegNTV2VPIDTransferCharacteristics6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1679  DEF_REG (kVRegNTV2VPIDColorimetry6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1680  DEF_REG (kVRegNTV2VPIDLuminance6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1681 
1682  DEF_REG (kVRegNTV2VPIDTransferCharacteristics7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1683  DEF_REG (kVRegNTV2VPIDColorimetry7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1684  DEF_REG (kVRegNTV2VPIDLuminance7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1685 
1686  DEF_REG (kVRegNTV2VPIDTransferCharacteristics8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1687  DEF_REG (kVRegNTV2VPIDColorimetry8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1688  DEF_REG (kVRegNTV2VPIDLuminance8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1689 
1690  DEF_REG (kVRegUserColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1691  DEF_REG (kVRegUserTransfer, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1692  DEF_REG (kVRegUserLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1693 
1694  DEF_REG (kVRegHdrColorimetryCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1695  DEF_REG (kVRegHdrTransferCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1696  DEF_REG (kVRegHdrLuminanceCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1697  DEF_REG (kVRegHdrGreenXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1698  DEF_REG (kVRegHdrGreenYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1699  DEF_REG (kVRegHdrBlueXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1700  DEF_REG (kVRegHdrBlueYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1701  DEF_REG (kVRegHdrRedXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1702  DEF_REG (kVRegHdrRedYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1703  DEF_REG (kVRegHdrWhiteXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1704  DEF_REG (kVRegHdrWhiteYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1705  DEF_REG (kVRegHdrMasterLumMaxCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1706  DEF_REG (kVRegHdrMasterLumMinCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1707  DEF_REG (kVRegHdrMaxCLLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1708  DEF_REG (kVRegHdrMaxFALLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1709  DEF_REG (kVRegHDROverrideState, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1710  DEF_REG (kVRegPCIMaxReadRequestSize, mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1711  DEF_REG (kVRegPCILinkSpeed, mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1712  DEF_REG (kVRegPCILinkWidth, mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1713  DEF_REG (kVRegUserInColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1714  DEF_REG (kVRegUserInTransfer, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1715  DEF_REG (kVRegUserInLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1716  DEF_REG (kVRegHdrInColorimetryCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1717  DEF_REG (kVRegHdrInTransferCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1718  DEF_REG (kVRegHdrInLuminanceCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1719  DEF_REG (kVRegHdrInGreenXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1720  DEF_REG (kVRegHdrInGreenYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1721  DEF_REG (kVRegHdrInBlueXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1722  DEF_REG (kVRegHdrInBlueYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1723  DEF_REG (kVRegHdrInRedXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1724  DEF_REG (kVRegHdrInRedYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1725  DEF_REG (kVRegHdrInWhiteXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1726  DEF_REG (kVRegHdrInWhiteYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1727  DEF_REG (kVRegHdrInMasterLumMaxCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1728  DEF_REG (kVRegHdrInMasterLumMinCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1729  DEF_REG (kVRegHdrInMaxCLLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1730  DEF_REG (kVRegHdrInMaxFALLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1731  DEF_REG (kVRegHDRInOverrideState, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1732  DEF_REG (kVRegNTV2VPIDRGBRange1, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1733  DEF_REG (kVRegNTV2VPIDRGBRange2, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1734  DEF_REG (kVRegNTV2VPIDRGBRange3, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1735  DEF_REG (kVRegNTV2VPIDRGBRange4, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1736  DEF_REG (kVRegNTV2VPIDRGBRange5, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1737  DEF_REG (kVRegNTV2VPIDRGBRange6, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1738  DEF_REG (kVRegNTV2VPIDRGBRange7, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1739  DEF_REG (kVRegNTV2VPIDRGBRange8, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1740 
1741  DEF_REG (kVRegRotaryGainOverrideEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1742  DEF_REG (kVRegAudioMixerOutputGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1743  DEF_REG (kVRegAudioHeadphoneGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1744  DEF_REG (kVRegAudioMixerOutputEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1745  DEF_REG (kVRegAudioHeadphoneEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1746  DEF_REG (kVRegAudioEncoderOutputEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1747  DEF_REG (kVRegAudioEncoderHeadphoneEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1748 
1749  DEF_REG (kVRegDmaTransferRateC2H1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1750  DEF_REG (kVRegDmaHardwareRateC2H1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1751  DEF_REG (kVRegDmaTransferRateH2C1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1752  DEF_REG (kVRegDmaHardwareRateH2C1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1753  DEF_REG (kVRegDmaTransferRateC2H2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1754  DEF_REG (kVRegDmaHardwareRateC2H2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1755  DEF_REG (kVRegDmaTransferRateH2C2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1756  DEF_REG (kVRegDmaHardwareRateH2C2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1757  DEF_REG (kVRegDmaTransferRateC2H3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1758  DEF_REG (kVRegDmaHardwareRateC2H3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1759  DEF_REG (kVRegDmaTransferRateH2C3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1760  DEF_REG (kVRegDmaHardwareRateH2C3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1761  DEF_REG (kVRegDmaTransferRateC2H4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1762  DEF_REG (kVRegDmaHardwareRateC2H4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1763  DEF_REG (kVRegDmaTransferRateH2C4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1764  DEF_REG (kVRegDmaHardwareRateH2C4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1765 
1766  DEF_REG (kVRegHDMIInAviInfo1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1767  DEF_REG (kVRegHDMIInDrmInfo1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1768  DEF_REG (kVRegHDMIInDrmGreenPrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1769  DEF_REG (kVRegHDMIInDrmBluePrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1770  DEF_REG (kVRegHDMIInDrmRedPrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1771  DEF_REG (kVRegHDMIInDrmWhitePoint1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1772  DEF_REG (kVRegHDMIInDrmMasteringLuminence1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1773  DEF_REG (kVRegHDMIInDrmLightLevel1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1774 
1775  DEF_REG (kVRegHDMIInAviInfo2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1776  DEF_REG (kVRegHDMIInDrmInfo2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1777  DEF_REG (kVRegHDMIInDrmGreenPrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1778  DEF_REG (kVRegHDMIInDrmBluePrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1779  DEF_REG (kVRegHDMIInDrmRedPrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1780  DEF_REG (kVRegHDMIInDrmWhitePoint2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1781  DEF_REG (kVRegHDMIInDrmMasteringLuminence2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1782  DEF_REG (kVRegHDMIInDrmLightLevel2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1783 
1784  DEF_REG (kVRegBaseFirmwareDeviceID, mDecodeBoardID, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
1785 
1786  DEF_REG (kVRegHDMIOutStatus1, mDecodeHDMIOutputStatus,READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_NULL);
1787  DEF_REG (kVRegAudioOutputToneSelect, mDefaultRegDecoder, READWRITE, kRegClass_Audio,kRegClass_Output, kRegClass_NULL);
1788  DEF_REG (kVRegDynFirmwareUpdateCounts, mDecodeDynFWUpdateCounts,READWRITE,kRegClass_NULL,kRegClass_NULL,kRegClass_NULL);
1789 
1790  DEF_REGNAME (kVRegLastAJA);
1791  DEF_REGNAME (kVRegFirstOEM);
1792 
1793  for (ULWord ndx(1); ndx < 1024; ndx++) // <== Start at 1, kVRegDriverVersion already done
1794  {
1795  ostringstream oss; oss << "VIRTUALREG_START+" << ndx;
1796  const string regName (oss.str());
1797  const ULWord regNum (VIRTUALREG_START + ndx);
1798  if (mRegNumToStringMap.find(regNum) == mRegNumToStringMap.end())
1799  {
1800  mRegNumToStringMap.insert (RegNumToStringPair(regNum, regName));
1801  mStringToRegNumMMap.insert (StringToRegNumPair(ToLower(regName), regNum));
1802  }
1803  DefineRegDecoder (regNum, mDefaultRegDecoder);
1804  DefineRegReadWrite (regNum, READWRITE);
1805  DefineRegClass (regNum, kRegClass_Virtual);
1806  }
1807  DefineRegClass (kVRegAudioOutputToneSelect, kRegClass_Audio);
1808  DefineRegClass (kVRegMonAncField1Offset, kRegClass_Anc);
1809  DefineRegClass (kVRegMonAncField2Offset, kRegClass_Anc);
1810  DefineRegClass (kVRegAncField1Offset, kRegClass_Anc);
1811  DefineRegClass (kVRegAncField2Offset, kRegClass_Anc);
1812  } // SetupVRegs
1813 
1814 public:
1815  static ostream & PrintLabelValuePairs (ostream & oss, const AJALabelValuePairs & inLabelValuePairs)
1816  {
1817  for (AJALabelValuePairsConstIter it(inLabelValuePairs.begin()); it != inLabelValuePairs.end(); )
1818  {
1819  const string & label (it->first);
1820  const string & value (it->second);
1821  if (label.empty())
1822  ;
1823  else if (label.at(label.length()-1) != ' ' && label.at(label.length()-1) != ':') // C++11 "label.back()" would be better
1824  oss << label << ": " << value;
1825  else if (label.at(label.length()-1) == ':') // C++11 "label.back()" would be better
1826  oss << label << " " << value;
1827  else
1828  oss << label << value;
1829  if (++it != inLabelValuePairs.end())
1830  oss << endl;
1831  }
1832  return oss;
1833  }
1834 
1835  string RegNameToString (const uint32_t inRegNum) const
1836  {
1837  AJAAutoLock lock(&mGuardMutex);
1838  RegNumToStringMap::const_iterator iter (mRegNumToStringMap.find (inRegNum));
1839  if (iter != mRegNumToStringMap.end())
1840  return iter->second;
1841 
1842  ostringstream oss; oss << "Reg ";
1843  if (inRegNum <= kRegNumRegisters)
1844  oss << DEC(inRegNum);
1845  else if (inRegNum <= 0x0000FFFF)
1846  oss << xHEX0N(inRegNum,4);
1847  else
1848  oss << xHEX0N(inRegNum,8);
1849  return oss.str();
1850  }
1851 
1852  string RegValueToString (const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
1853  {
1854  AJAAutoLock lock(&mGuardMutex);
1855  RegNumToDecoderMap::const_iterator iter(mRegNumToDecoderMap.find(inRegNum));
1856  ostringstream oss;
1857  if (iter != mRegNumToDecoderMap.end() && iter->second)
1858  {
1859  const Decoder * pDecoder (iter->second);
1860  oss << (*pDecoder)(inRegNum, inRegValue, inDeviceID);
1861  }
1862  return oss.str();
1863  }
1864 
1865  bool IsRegInClass (const uint32_t inRegNum, const string & inClassName) const
1866  {
1867  AJAAutoLock lock(&mGuardMutex);
1868  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.find(inClassName)); it != mRegClassToRegNumMMap.end() && it->first == inClassName; ++it)
1869  if (it->second == inRegNum)
1870  return true;
1871  return false;
1872  }
1873 
1874  inline bool IsRegisterWriteOnly (const uint32_t inRegNum) const {return IsRegInClass (inRegNum, kRegClass_WriteOnly);}
1875  inline bool IsRegisterReadOnly (const uint32_t inRegNum) const {return IsRegInClass (inRegNum, kRegClass_ReadOnly);}
1876 
1877  NTV2StringSet GetAllRegisterClasses (void) const
1878  {
1879  AJAAutoLock lock(&mGuardMutex);
1880  if (mAllRegClasses.empty())
1881  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.begin()); it != mRegClassToRegNumMMap.end(); ++it)
1882  if (mAllRegClasses.find(it->first) == mAllRegClasses.end())
1883  mAllRegClasses.insert(it->first);
1884  return mAllRegClasses;
1885  }
1886 
1887  NTV2StringSet GetRegisterClasses (const uint32_t inRegNum, const bool inRemovePrefix) const
1888  {
1889  AJAAutoLock lock(&mGuardMutex);
1890  NTV2StringSet result;
1891  NTV2StringSet allClasses (GetAllRegisterClasses());
1892  for (NTV2StringSetConstIter it(allClasses.begin()); it != allClasses.end(); ++it)
1893  if (IsRegInClass (inRegNum, *it))
1894  {
1895  string str(*it);
1896  if (inRemovePrefix)
1897  str.erase(0, 10); // Remove "kRegClass_" prefix
1898  if (result.find(str) == result.end())
1899  result.insert(str);
1900  }
1901  return result;
1902  }
1903 
1904  NTV2RegNumSet GetRegistersForClass (const string & inClassName) const
1905  {
1906  AJAAutoLock lock(&mGuardMutex);
1907  NTV2RegNumSet result;
1908  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.find(inClassName)); it != mRegClassToRegNumMMap.end() && it->first == inClassName; ++it)
1909  if (result.find(it->second) == result.end())
1910  result.insert(it->second);
1911  return result;
1912  }
1913 
1914  NTV2RegNumSet GetRegistersForDevice (const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude) const
1915  {
1916  NTV2RegNumSet result;
1917  const uint32_t maxRegNum (::NTV2DeviceGetMaxRegisterNumber(inDeviceID));
1918 
1919  for (uint32_t regNum (0); regNum <= maxRegNum; regNum++)
1920  result.insert(regNum);
1921 
1922  AJAAutoLock lock(&mGuardMutex);
1923 
1924  if (::NTV2DeviceCanDoCustomAnc(inDeviceID))
1925  {
1926  const NTV2RegNumSet ancRegs (GetRegistersForClass(kRegClass_Anc));
1927  const UWord numVideoInputs (::NTV2DeviceGetNumVideoInputs(inDeviceID));
1928  const UWord numVideoOutputs (::NTV2DeviceGetNumVideoOutputs(inDeviceID));
1929  const UWord numSpigots(numVideoInputs > numVideoOutputs ? numVideoInputs : numVideoOutputs);
1930  NTV2RegNumSet allChanRegs; // For just those channels it supports
1931  for (UWord num(0); num < numSpigots; num++)
1932  {
1933  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1934  allChanRegs.insert(chRegs.begin(), chRegs.end());
1935  }
1936  std::set_intersection (ancRegs.begin(), ancRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1937  }
1938 
1939  if (::NTV2DeviceCanDoCustomAux(inDeviceID))
1940  {
1941  const NTV2RegNumSet auxRegs (GetRegistersForClass(kRegClass_Aux));
1942  const UWord numVideoInputs (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID));
1943  const UWord numVideoOutputs (::NTV2DeviceGetNumHDMIVideoOutputs(inDeviceID));
1944  const UWord numSpigots(numVideoInputs > numVideoOutputs ? numVideoInputs : numVideoOutputs);
1945  NTV2RegNumSet allChanRegs; // For just those channels it supports
1946  for (UWord num(0); num < numSpigots; num++)
1947  {
1948  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1949  allChanRegs.insert(chRegs.begin(), chRegs.end());
1950  }
1951  std::set_intersection (auxRegs.begin(), auxRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1952  }
1953 
1954  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
1955  {
1956  const NTV2RegNumSet sdiErrRegs (GetRegistersForClass(kRegClass_SDIError));
1957  result.insert(sdiErrRegs.begin(), sdiErrRegs.end());
1958  }
1959 
1960  if (::NTV2DeviceCanDoAudioMixer(inDeviceID))
1961  {
1962  for (ULWord regNum(kRegAudioMixerInputSelects); regNum <= kRegAudioMixerAux2GainCh2; regNum++)
1963  result.insert(regNum);
1964  for (ULWord regNum(kRegAudioMixerAux1InputLevels); regNum <= kRegAudioMixerMainOutputLevelsPair7; regNum++)
1965  result.insert(regNum);
1966  }
1967 
1968  if (::NTV2DeviceHasXilinxDMA(inDeviceID))
1969  {
1970  }
1971 
1972  if (::NTV2DeviceCanDoEnhancedCSC(inDeviceID))
1973  {
1974  const NTV2RegNumSet ecscRegs (GetRegistersForClass(kRegClass_CSC));
1975  const UWord numCSCs (::NTV2DeviceGetNumCSCs(inDeviceID));
1976  NTV2RegNumSet allChanRegs; // For just those CSCs it supports
1977  for (UWord num(0); num < numCSCs; num++)
1978  {
1979  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1980  allChanRegs.insert(chRegs.begin(), chRegs.end());
1981  }
1982  std::set_intersection (ecscRegs.begin(), ecscRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1983  }
1984 
1985  if (::NTV2DeviceGetNumLUTs(inDeviceID))
1986  {
1987  const NTV2RegNumSet LUTRegs (GetRegistersForClass(kRegClass_LUT));
1988  result.insert(LUTRegs.begin(), LUTRegs.end());
1989  }
1990 
1991  if (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID) > 1) // KonaHDMI
1992  {
1993  for (ULWord regNum = 0x1d00; regNum <= 0x1d1f; regNum++)
1994  result.insert(regNum);
1995  for (ULWord regNum = 0x2500; regNum <= 0x251f; regNum++)
1996  result.insert(regNum);
1997  for (ULWord regNum = 0x2c00; regNum <= 0x2c1f; regNum++)
1998  result.insert(regNum);
1999  for (ULWord regNum = 0x3000; regNum <= 0x301f; regNum++)
2000  result.insert(regNum);
2001  }
2002  else if (NTV2DeviceGetHDMIVersion(inDeviceID) > 3) // Io4KPlus, IoIP2022, IoIP2110, Kona5, KonaHDMI
2003  { // v4 HDMI: Io4K+, IoIP2022, IoIP2110, Kona5, KonaHDMI...
2004  for (ULWord regNum = 0x1d00; regNum <= 0x1d1f; regNum++)
2005  result.insert(regNum);
2006  for (ULWord regNum = 0x1d40; regNum <= 0x1d5f; regNum++)
2007  result.insert(regNum);
2008  for (ULWord regNum = 0x3C00; regNum <= 0x3C0A; regNum++)
2009  result.insert(regNum);
2010  }
2011 
2012  if (inDeviceID == DEVICE_ID_IOX3 || inDeviceID == DEVICE_ID_KONA5_8K_MV_TX)
2013  { // IoX3 and some Kona5 support MultiViewer/MultiRaster
2014  result.insert(ULWord(kRegMRQ1Control));
2015  result.insert(ULWord(kRegMRQ2Control));
2016  result.insert(ULWord(kRegMRQ3Control));
2017  result.insert(ULWord(kRegMRQ4Control));
2018  result.insert(ULWord(kRegMROutControl));
2019  result.insert(ULWord(kRegMRSupport));
2020  }
2021 
2022  if (NTV2DeviceHasNTV4FrameStores(inDeviceID))
2023  {
2024  const NTV2RegNumSet ntv4FSRegs (GetRegistersForClass(kRegClass_NTV4FrameStore));
2025  const UWord numFrameStores (::NTV2DeviceGetNumFrameStores(inDeviceID));
2026  NTV2RegNumSet chanRegs; // Just the supported NTV4 FrameStores
2027  for (UWord num(0); num < numFrameStores; num++)
2028  {
2029  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
2030  chanRegs.insert(chRegs.begin(), chRegs.end());
2031  }
2032  std::set_intersection (ntv4FSRegs.begin(), ntv4FSRegs.end(), chanRegs.begin(), chanRegs.end(), std::inserter(result, result.begin()));
2033  }
2034 
2035  if (NTV2DeviceCanDoIDSwitch(inDeviceID))
2036  {
2037  result.insert(ULWord(kRegIDSwitch));
2038  }
2039 
2040  if (NTV2DeviceHasPWMFanControl(inDeviceID))
2041  {
2042  result.insert(ULWord(kRegPWMFanControl));
2043  result.insert(ULWord(kRegPWMFanStatus));
2044  }
2045 
2046  if (NTV2DeviceCanDoBreakoutBoard(inDeviceID))
2047  {
2048  result.insert(ULWord(kRegBOBStatus));
2049  result.insert(ULWord(kRegBOBGPIInData));
2050  result.insert(ULWord(kRegBOBGPIInterruptControl));
2051  result.insert(ULWord(kRegBOBGPIOutData));
2052  result.insert(ULWord(kRegBOBAudioControl));
2053  }
2054 
2055  if (NTV2DeviceHasBracketLED(inDeviceID))
2056  {
2057  result.insert(ULWord(kRegLEDReserved0));
2058  result.insert(ULWord(kRegLEDClockDivide));
2059  result.insert(ULWord(kRegLEDReserved2));
2060  result.insert(ULWord(kRegLEDReserved3));
2061  result.insert(ULWord(kRegLEDSDI1Control));
2062  result.insert(ULWord(kRegLEDSDI2Control));
2063  result.insert(ULWord(kRegLEDHDMIInControl));
2064  result.insert(ULWord(kRegLEDHDMIOutControl));
2065  }
2066 
2067  if (NTV2DeviceCanDoClockMonitor(inDeviceID))
2068  {
2069  result.insert(ULWord(kRegCMWControl));
2070  result.insert(ULWord(kRegCMW1485Out));
2071  result.insert(ULWord(kRegCMW14835Out));
2072  result.insert(ULWord(kRegCMW27Out));
2073  result.insert(ULWord(kRegCMW12288Out));
2074  result.insert(ULWord(kRegCMWHDMIOut));
2075  }
2076 
2077  if (inOtherRegsToInclude & kIncludeOtherRegs_VRegs)
2078  {
2079  const NTV2RegNumSet vRegs (GetRegistersForClass(kRegClass_Virtual));
2080  result.insert(vRegs.begin(), vRegs.end());
2081  }
2082 
2083  if (inOtherRegsToInclude & kIncludeOtherRegs_XptROM)
2084  {
2085  const NTV2RegNumSet xptMapRegs (GetRegistersForClass(kRegClass_XptROM));
2086  result.insert(xptMapRegs.begin(), xptMapRegs.end());
2087  }
2088  return result;
2089  }
2090 
2091 
2092  NTV2RegNumSet GetRegistersWithName (const string & inName, const int inMatchStyle = EXACTMATCH) const
2093  {
2094  NTV2RegNumSet result;
2095  string nameStr(inName);
2096  const size_t nameStrLen(aja::lower(nameStr).length());
2097  StringToRegNumConstIter it;
2098  AJAAutoLock lock(&mGuardMutex);
2099  if (inMatchStyle == EXACTMATCH)
2100  {
2101  it = mStringToRegNumMMap.find(nameStr);
2102  if (it != mStringToRegNumMMap.end())
2103  result.insert(it->second);
2104  return result;
2105  }
2106  // Inexact match...
2107  for (it = mStringToRegNumMMap.begin(); it != mStringToRegNumMMap.end(); ++it)
2108  {
2109  const size_t pos(it->first.find(nameStr));
2110  if (pos == string::npos)
2111  continue;
2112  switch (inMatchStyle)
2113  {
2114  case CONTAINS: result.insert(it->second); break;
2115  case STARTSWITH: if (pos == 0)
2116  {result.insert(it->second);}
2117  break;
2118  case ENDSWITH: if (pos+nameStrLen == it->first.length())
2119  {result.insert(it->second);}
2120  break;
2121  default: break;
2122  }
2123  }
2124  return result;
2125  }
2126 
2127  bool GetXptRegNumAndMaskIndex (const NTV2InputCrosspointID inInputXpt, uint32_t & outXptRegNum, uint32_t & outMaskIndex) const
2128  {
2129  AJAAutoLock lock(&mGuardMutex);
2130  outXptRegNum = 0xFFFFFFFF;
2131  outMaskIndex = 0xFFFFFFFF;
2132  InputXpt2XptRegNumMaskIndexMapConstIter iter (mInputXpt2XptRegNumMaskIndexMap.find (inInputXpt));
2133  if (iter == mInputXpt2XptRegNumMaskIndexMap.end())
2134  return false;
2135  outXptRegNum = iter->second.first;
2136  outMaskIndex = iter->second.second;
2137  return true;
2138  }
2139 
2140  NTV2InputCrosspointID GetInputCrosspointID (const uint32_t inXptRegNum, const uint32_t inMaskIndex) const
2141  {
2142  AJAAutoLock lock(&mGuardMutex);
2143  const XptRegNumAndMaskIndex key (inXptRegNum, inMaskIndex);
2144  XptRegNumMaskIndex2InputXptMapConstIter iter (mXptRegNumMaskIndex2InputXptMap.find (key));
2145  if (iter != mXptRegNumMaskIndex2InputXptMap.end())
2146  return iter->second;
2147  return NTV2_INPUT_CROSSPOINT_INVALID;
2148  }
2149 
2150  ostream & Print (ostream & inOutStream) const
2151  {
2152  AJAAutoLock lock(&mGuardMutex);
2153  static const string sLineBreak (96, '=');
2154  static const uint32_t sMasks[4] = {0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000};
2155 
2156  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegNumToStringMap: " << mRegNumToStringMap.size() << " mappings:" << endl << sLineBreak << endl;
2157  for (RegNumToStringMap::const_iterator it (mRegNumToStringMap.begin()); it != mRegNumToStringMap.end(); ++it)
2158  inOutStream << "reg " << setw(5) << it->first << "(" << HEX0N(it->first,8) << dec << ") => '" << it->second << "'" << endl;
2159 
2160  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegNumToDecoderMap: " << mRegNumToDecoderMap.size() << " mappings:" << endl << sLineBreak << endl;
2161  for (RegNumToDecoderMap::const_iterator it (mRegNumToDecoderMap.begin()); it != mRegNumToDecoderMap.end(); ++it)
2162  inOutStream << "reg " << setw(5) << it->first << "(" << HEX0N(it->first,8) << dec << ") => " << (it->second == &mDefaultRegDecoder ? "(default decoder)" : "Custom Decoder") << endl;
2163 
2164  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegClassToRegNumMMap: " << mRegClassToRegNumMMap.size() << " mappings:" << endl << sLineBreak << endl;
2165  for (RegClassToRegNumMMap::const_iterator it (mRegClassToRegNumMMap.begin()); it != mRegClassToRegNumMMap.end(); ++it)
2166  inOutStream << setw(32) << it->first << " => reg " << setw(5) << it->second << "(" << HEX0N(it->second,8) << dec << ") " << RegNameToString(it->second) << endl;
2167 
2168  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of StringToRegNumMMap: " << mStringToRegNumMMap.size() << " mappings:" << endl << sLineBreak << endl;
2169  for (StringToRegNumMMap::const_iterator it (mStringToRegNumMMap.begin()); it != mStringToRegNumMMap.end(); ++it)
2170  inOutStream << setw(32) << it->first << " => reg " << setw(5) << it->second << "(" << HEX0N(it->second,8) << dec << ") " << RegNameToString(it->second) << endl;
2171 
2172  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of InputXpt2XptRegNumMaskIndexMap: " << mInputXpt2XptRegNumMaskIndexMap.size() << " mappings:" << endl << sLineBreak << endl;
2173  for (InputXpt2XptRegNumMaskIndexMap::const_iterator it (mInputXpt2XptRegNumMaskIndexMap.begin()); it != mInputXpt2XptRegNumMaskIndexMap.end(); ++it)
2174  inOutStream << setw(32) << ::NTV2InputCrosspointIDToString(it->first) << "(" << HEX0N(it->first,2)
2175  << ") => reg " << setw(3) << it->second.first << "(" << HEX0N(it->second.first,3) << dec << "|" << setw(20) << RegNameToString(it->second.first)
2176  << ") mask " << it->second.second << "(" << HEX0N(sMasks[it->second.second],8) << ")" << endl;
2177 
2178  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of XptRegNumMaskIndex2InputXptMap: " << mXptRegNumMaskIndex2InputXptMap.size() << " mappings:" << endl << sLineBreak << endl;
2179  for (XptRegNumMaskIndex2InputXptMap::const_iterator it (mXptRegNumMaskIndex2InputXptMap.begin()); it != mXptRegNumMaskIndex2InputXptMap.end(); ++it)
2180  inOutStream << "reg " << setw(3) << it->first.first << "(" << HEX0N(it->first.first,4) << "|" << setw(20) << RegNameToString(it->first.first)
2181  << ") mask " << it->first.second << "(" << HEX0N(sMasks[it->first.second],8) << ") => "
2182  << setw(27) << ::NTV2InputCrosspointIDToString(it->second) << "(" << HEX0N(it->second,2) << ")" << endl;
2183  return inOutStream;
2184  }
2185 
2186 private:
2187  typedef std::map<uint32_t, string> RegNumToStringMap;
2188  typedef std::pair<uint32_t, string> RegNumToStringPair;
2189 
2190  static string ToLower (const string & inStr)
2191  {
2192  string result (inStr);
2193  std::transform (result.begin (), result.end (), result.begin (), ::tolower);
2194  return result;
2195  }
2196 
2197  struct DecodeGlobalControlReg : public Decoder
2198  {
2199  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2200  {
2201  (void) inRegNum;
2202  (void) inDeviceID;
2203  const NTV2FrameGeometry frameGeometry (NTV2FrameGeometry (((inRegValue & kRegMaskGeometry ) >> 3)));
2204  const NTV2Standard videoStandard (NTV2Standard ((inRegValue & kRegMaskStandard ) >> 7));
2205  const NTV2ReferenceSource referenceSource (NTV2ReferenceSource ((inRegValue & kRegMaskRefSource ) >> 10));
2206  const NTV2RegisterWriteMode registerWriteMode (NTV2RegisterWriteMode ((inRegValue & kRegMaskRegClocking ) >> 20));
2207  const NTV2FrameRate frameRate (NTV2FrameRate (((inRegValue & kRegMaskFrameRate ) >> kRegShiftFrameRate)
2208  | ((inRegValue & kRegMaskFrameRateHiBit) >> (kRegShiftFrameRateHiBit - 3))));
2209  ostringstream oss;
2210  oss << "Frame Rate: " << ::NTV2FrameRateToString (frameRate, true) << endl
2211  << "Frame Geometry: " << ::NTV2FrameGeometryToString (frameGeometry, true) << endl
2212  << "Standard: " << ::NTV2StandardToString (videoStandard, true) << endl
2213  << "Reference Source: " << ::NTV2ReferenceSourceToString (referenceSource, true) << endl
2214  << "Ch 2 link B 1080p 50/60: " << ((inRegValue & kRegMaskSmpte372Enable) ? "On" : "Off") << endl
2215  << "LEDs ";
2216  for (int led(0); led < 4; ++led)
2217  oss << (((inRegValue & kRegMaskLED) >> (16 + led)) ? "*" : ".");
2218  oss << endl
2219  << "Register Clocking: " << ::NTV2RegisterWriteModeToString (registerWriteMode, true).c_str() << endl
2220  << "Ch 1 RP-188 output: " << EnabDisab(inRegValue & kRegMaskRP188ModeCh1) << endl
2221  << "Ch 2 RP-188 output: " << EnabDisab(inRegValue & kRegMaskRP188ModeCh2) << endl
2222  << "Color Correction: " << "Channel: " << ((inRegValue & BIT(31)) ? "2" : "1")
2223  << " Bank " << ((inRegValue & BIT (30)) ? "1" : "0");
2224  return oss.str();
2225  }
2226  } mDecodeGlobalControlReg;
2227 
2228  // reg 267 aka kRegGlobalControl2
2229  struct DecodeGlobalControl2 : public Decoder
2230  {
2231  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2232  {
2233  (void) inRegNum;
2234  (void) inDeviceID;
2235  static const ULWord playCaptModes[] = { kRegMaskAud1PlayCapMode,kRegMaskAud2PlayCapMode,kRegMaskAud3PlayCapMode,kRegMaskAud4PlayCapMode,
2236  kRegMaskAud5PlayCapMode,kRegMaskAud6PlayCapMode,kRegMaskAud7PlayCapMode,kRegMaskAud8PlayCapMode};
2237  static const ULWord rp188Modes[] = { 0, 0, kRegMaskRP188ModeCh3,kRegMaskRP188ModeCh4,kRegMaskRP188ModeCh5,ULWord(kRegMaskRP188ModeCh6),kRegMaskRP188ModeCh7,kRegMaskRP188ModeCh8};
2238  static const ULWord k425Masks[] = { kRegMask425FB12, kRegMask425FB34, kRegMask425FB56, kRegMask425FB78};
2239  static const ULWord BLinkModes[] = { kRegMaskSmpte372Enable4, kRegMaskSmpte372Enable6, kRegMaskSmpte372Enable8};
2240  ostringstream oss;
2241  oss << "Reference source bit 4: " << SetNotset(inRegValue & kRegMaskRefSource2) << endl
2242  << "Quad Mode Channel 1-4: " << SetNotset(inRegValue & kRegMaskQuadMode) << endl
2243  << "Quad Mode Channel 5-8: " << SetNotset(inRegValue & kRegMaskQuadMode2) << endl
2244  << "Independent Channel Mode: " << SetNotset(inRegValue & kRegMaskIndependentMode) << endl
2245  << "2MB Frame Support: " << SuppNotsupp(inRegValue & kRegMask2MFrameSupport) << endl
2246  << "Audio Mixer: " << PresNotPres(inRegValue & kRegMaskAudioMixerPresent) << endl
2247  << "Is DNXIV Product: " << YesNo(inRegValue & kRegMaskIsDNXIV) << endl;
2248  for (unsigned ch(0); ch < 8; ch++)
2249  oss << "Audio " << DEC(ch+1) << " Play/Capture Mode: " << OnOff(inRegValue & playCaptModes[ch]) << endl;
2250  for (unsigned ch(2); ch < 8; ch++)
2251  oss << "Ch " << DEC(ch+1) << " RP188 Output: " << EnabDisab(inRegValue & rp188Modes[ch]) << endl;
2252  for (unsigned ch(0); ch < 3; ch++)
2253  oss << "Ch " << DEC(2*(ch+2)) << " 1080p50/p60 Link-B Mode: " << EnabDisab(inRegValue & BLinkModes[ch]) << endl;
2254  for (unsigned ch(0); ch < 4; ch++)
2255  oss << "Ch " << DEC(ch*2+1) << "/" << DEC(ch*2+2) << " 2SI Mode: " << EnabDisab(inRegValue & k425Masks[ch]) << endl;
2256  oss << "2SI Min Align Delay 1-4: " << EnabDisab(inRegValue & BIT(24)) << endl
2257  << "2SI Min Align Delay 5-8: " << EnabDisab(inRegValue & BIT(25));
2258  return oss.str();
2259  }
2260  } mDecodeGlobalControl2;
2261 
2262  // reg 108 aka kRegGlobalControl3
2263  struct DecodeGlobalControl3 : public Decoder
2264  {
2265  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2266  {
2267  (void) inRegNum;
2268  (void) inDeviceID;
2269  ostringstream oss;
2270  oss << "Bidirectional analog audio 1-4: " << (inRegValue & kRegMaskAnalogIOControl_14 ? "Receive" : "Transmit") << endl
2271  << "Bidirectional analog audio 5-8: " << (inRegValue & kRegMaskAnalogIOControl_58 ? "Receive" : "Transmit") << endl
2272  << "VU Meter Audio Select: " << (inRegValue & kRegMaskVUMeterSelect ? "AudMixer" : "AudSys1") << endl
2273  << "Quad Quad Mode FrameStores 1-2: " << EnabDisab(inRegValue & kRegMaskQuadQuadMode) << endl
2274  << "Quad Quad Mode FrameStores 3-4: " << EnabDisab(inRegValue & kRegMaskQuadQuadMode2) << endl
2275  << "Quad Quad Squares Mode 1-4: " << EnabDisab(inRegValue & kRegMaskQuadQuadSquaresMode) << endl
2276  << "Frame Pulse Enable: " << EnabDisab(inRegValue & kRegMaskFramePulseEnable);
2277  if (inRegValue & kRegMaskFramePulseEnable)
2278  oss << endl
2279  << "Frame Pulse Ref Src: " << DEC((inRegValue & kRegMaskFramePulseRefSelect) >> kRegShiftFramePulseRefSelect);
2280  return oss.str();
2281  }
2282  } mDecodeGlobalControl3;
2283 
2284  // Regs 377,378,379,380,381,382,383 aka kRegGlobalControlCh2,kRegGlobalControlCh3,kRegGlobalControlCh4,kRegGlobalControlCh5,kRegGlobalControlCh6,kRegGlobalControlCh7,kRegGlobalControlCh8
2285  struct DecodeGlobalControlChanReg : public Decoder
2286  {
2287  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2288  {
2289  (void) inRegNum;
2290  (void) inDeviceID;
2291  ostringstream oss;
2292  const NTV2FrameGeometry frameGeometry = NTV2FrameGeometry((inRegValue & kRegMaskGeometry) >> 3);
2293  const NTV2Standard videoStandard = NTV2Standard((inRegValue & kRegMaskStandard) >> 7);
2294  const NTV2FrameRate frameRate = NTV2FrameRate(((inRegValue & kRegMaskFrameRate) >> kRegShiftFrameRate) | ((inRegValue & kRegMaskFrameRateHiBit) >> (kRegShiftFrameRateHiBit - 3)));
2295  oss << "Frame Rate: " << ::NTV2FrameRateToString (frameRate) << endl
2296  << "Frame Geometry: " << ::NTV2FrameGeometryToString (frameGeometry) << endl
2297  << "Standard: " << ::NTV2StandardToString (videoStandard);
2298  return oss.str();
2299  }
2300  } mDecodeGlobalControlChanRegs;
2301 
2302  // Regs 1/5/257/260/384/388/392/396 aka kRegCh1Control,kRegCh2Control,kRegCh3Control,kRegCh4Control,kRegCh5Control,kRegCh6Control,kRegCh7Control,kRegCh8Control
2303  struct DecodeChannelControlReg : public Decoder
2304  {
2305  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2306  {
2307  (void) inRegNum;
2308  (void) inDeviceID;
2309  ostringstream oss;
2310  const ULWord fbfUpper ((inRegValue & kRegMaskFrameFormatHiBit) >> 2);
2311  const ULWord fbfLower ((inRegValue & kRegMaskFrameFormat) >> 1);
2312  oss << "Mode: " << (inRegValue & kRegMaskMode ? "Capture" : "Display") << endl
2313  << "Format: " << ::NTV2FrameBufferFormatToString(NTV2PixelFormat(fbfUpper | fbfLower),false) << endl
2314  << "Channel: " << DisabEnab(inRegValue & kRegMaskChannelDisable) << endl
2315  << "Viper Squeeze: " << (inRegValue & BIT(9) ? "Squeeze" : "Normal") << endl
2316  << "Flip Vertical: " << (inRegValue & kRegMaskFrameOrientation ? "Upside Down" : "Normal") << endl
2317  << "DRT Display: " << OnOff(inRegValue & kRegMaskQuarterSizeMode) << endl
2318  << "Frame Buffer Mode: " << (inRegValue & kRegMaskFrameBufferMode ? "Field" : "Frame") << endl
2319  << "Dither: " << (inRegValue & kRegMaskDitherOn8BitInput ? "Dither 8-bit inputs" : "No dithering") << endl
2320  << "Frame Size: " << (1 << (((inRegValue & kK2RegMaskFrameSize) >> 20) + 1)) << " MB" << endl;
2321  if (inRegNum == kRegCh1Control && ::NTV2DeviceSoftwareCanChangeFrameBufferSize(inDeviceID))
2322  oss << "Frame Size Override: " << EnabDisab(inRegValue & kRegMaskFrameSizeSetBySW) << endl;
2323  oss << "RGB Range: " << (inRegValue & BIT(24) ? "Black = 0x40" : "Black = 0") << endl
2324  << "VANC Data Shift: " << (inRegValue & kRegMaskVidProcVANCShift ? "Enabled" : "Normal 8 bit conversion");
2325  return oss.str();
2326  }
2327  } mDecodeChannelControl;
2328 
2329  struct DecodeFBControlReg : public Decoder
2330  {
2331  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2332  {
2333  (void) inRegNum;
2334  (void) inDeviceID;
2335  const bool isOn ((inRegValue & (1 << 29)) != 0);
2336  const uint16_t format ((inRegValue >> 15) & 0x1F);
2337  ostringstream oss;
2338  oss << OnOff(isOn) << endl
2339  << "Format: " << xHEX0N(format,4) << " (" << DEC(format) << ")";
2340  return oss.str();
2341  }
2342  } mDecodeFBControlReg;
2343 
2344  struct DecodeChannelControlExtReg : public Decoder
2345  {
2346  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2347  {
2348  (void) inRegNum;
2349  (void) inDeviceID;
2350  ostringstream oss;
2351  oss << "Input Video 2:1 Decimate: " << EnabDisab(inRegValue & BIT(0)) << endl
2352  << "HDMI Rx Direct: " << EnabDisab(inRegValue & BIT(1)) << endl
2353  << "3:2 Pulldown Mode: " << EnabDisab(inRegValue & BIT(2));
2354  return oss.str();
2355  }
2356  } mDecodeChannelControlExt;
2357 
2358  struct DecodeSysmonVccIntDieTemp : public Decoder
2359  {
2360  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2361  {
2362  (void) inRegNum;
2363  (void) inDeviceID;
2364  UWord rawDieTemp (0);
2365  double dieTempC (0);
2366  if (NTV2DeviceCanDoVersalSysMon(inDeviceID))
2367  {
2368  rawDieTemp = (inRegValue & 0x0000FFFF);
2369  dieTempC = double(rawDieTemp) / 128.0;
2370  }
2371  else
2372  {
2373  rawDieTemp = ((inRegValue & 0x0000FFFF) >> 6);
2374  dieTempC = ((double(rawDieTemp)) * 503.975 / 1024.0 - 273.15 );
2375  }
2376  const UWord rawVoltage ((inRegValue >> 22) & 0x3FF);
2377  const double dieTempF (dieTempC * 9.0 / 5.0 + 32.0);
2378  const double voltage (double(rawVoltage)/ 1024.0 * 3.0);
2379  ostringstream oss;
2380  oss << "Die Temperature: " << fDEC(dieTempC,5,2) << " Celcius (" << fDEC(dieTempF,5,2) << " Fahrenheit)" << endl
2381  << "Core Voltage: " << fDEC(voltage,5,2) << " Volts DC";
2382  return oss.str();
2383  }
2384  } mDecodeSysmonVccIntDieTemp;
2385 
2386  struct DecodeSDITransmitCtrl : public Decoder
2387  {
2388  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2389  {
2390  (void) inRegNum;
2391  const UWord numInputs (::NTV2DeviceGetNumVideoInputs(inDeviceID));
2392  const UWord numOutputs (::NTV2DeviceGetNumVideoOutputs(inDeviceID));
2393  const UWord numSpigots (numInputs > numOutputs ? numInputs : numOutputs);
2394  ostringstream oss;
2395  if (::NTV2DeviceHasBiDirectionalSDI(inDeviceID))
2396  {
2397  const uint32_t txEnableBits (((inRegValue & 0x0F000000) >> 20) | ((inRegValue & 0xF0000000) >> 28));
2398  if (numSpigots)
2399  for (UWord spigot(0); spigot < numSpigots; )
2400  {
2401  const uint32_t txEnabled (txEnableBits & BIT(spigot));
2402  oss << "SDI " << DEC(++spigot) << ": " << (txEnabled ? "Output/Transmit" : "Input/Receive");
2403  if (spigot < numSpigots)
2404  oss << endl;
2405  }
2406  else
2407  oss << "(No SDI inputs or outputs)";
2408  }
2409  else
2410  oss << "(Bi-directional SDI not supported)";
2411  // CRC checking
2412  return oss.str();
2413  }
2414  } mDecodeSDITransmitCtrl;
2415 
2416  struct DecodeConversionCtrl : public Decoder
2417  {
2418  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2419  { (void) inRegNum;
2420  ostringstream oss;
2421  if (!::NTV2DeviceGetUFCVersion(inDeviceID))
2422  {
2423  const ULWord bitfileID((inRegValue & kK2RegMaskConverterInRate) >> kK2RegShiftConverterInRate);
2424  oss << "Bitfile ID: " << xHEX0N(bitfileID, 2) << endl
2425  << "Memory Test: Start: " << YesNo(inRegValue & BIT(28)) << endl
2426  << "Memory Test: Done: " << YesNo(inRegValue & BIT(29)) << endl
2427  << "Memory Test: Passed: " << YesNo(inRegValue & BIT(30));
2428  }
2429  else
2430  {
2431  const NTV2Standard inStd ( NTV2Standard( inRegValue & kK2RegMaskConverterInStandard ));
2432  const NTV2Standard outStd ( NTV2Standard((inRegValue & kK2RegMaskConverterOutStandard ) >> kK2RegShiftConverterOutStandard));
2433  const NTV2FrameRate inRate ( NTV2FrameRate((inRegValue & kK2RegMaskConverterInRate ) >> kK2RegShiftConverterInRate));
2434  const NTV2FrameRate outRate ( NTV2FrameRate((inRegValue & kK2RegMaskConverterOutRate ) >> kK2RegShiftConverterOutRate));
2435  const NTV2UpConvertMode upCvtMode ( NTV2UpConvertMode((inRegValue & kK2RegMaskUpConvertMode ) >> kK2RegShiftUpConvertMode));
2436  const NTV2DownConvertMode dnCvtMode (NTV2DownConvertMode((inRegValue & kK2RegMaskDownConvertMode ) >> kK2RegShiftDownConvertMode));
2437  const NTV2IsoConvertMode isoCvtMode ( NTV2IsoConvertMode((inRegValue & kK2RegMaskIsoConvertMode ) >> kK2RegShiftIsoConvertMode));
2438  oss << "Input Video Standard: " << ::NTV2StandardToString(inStd, true) << endl
2439  << "Input Video Frame Rate: " << ::NTV2FrameRateToString(inRate, true) << endl
2440  << "Output Video Standard: " << ::NTV2StandardToString(outStd, true) << endl
2441  << "Output Video Frame Rate: " << ::NTV2FrameRateToString(outRate, true) << endl
2442  << "Up Convert Mode: " << ::NTV2UpConvertModeToString(upCvtMode, true) << endl
2443  << "Down Convert Mode: " << ::NTV2DownConvertModeToString(dnCvtMode, true) << endl
2444  << "SD Anamorphic ISO Convert Mode: " << ::NTV2IsoConvertModeToString(isoCvtMode, true) << endl
2445  << "DownCvt 2-3 Pulldown: " << EnabDisab(inRegValue & kK2RegMaskConverterPulldown) << endl
2446  << "Vert Filter Preload: " << DisabEnab(inRegValue & BIT(7)) << endl
2447  << "Output Vid Std PsF (Deint Mode): " << EnabDisab(inRegValue & kK2RegMaskDeinterlaceMode) << endl
2448  << "Up Conv Line21 Pass|Blank Mode: " << DEC(ULWord(inRegValue & kK2RegMaskUCPassLine21) >> kK2RegShiftUCAutoLine21) << endl
2449  << "UFC Clock: " << EnabDisab(inRegValue & kK2RegMaskEnableConverter);
2450  }
2451  return oss.str();
2452  }
2453  } mConvControlRegDecoder;
2454 
2455  struct DecodeRelayCtrlStat : public Decoder
2456  {
2457  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2458  {
2459  (void) inRegNum;
2460  ostringstream oss;
2461  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2462  {
2463  oss << "SDI1-SDI2 Relay Control: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayControl12) << endl
2464  << "SDI3-SDI4 Relay Control: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayControl34) << endl
2465  << "SDI1-SDI2 Relay Watchdog: " << EnabDisab(inRegValue & kRegMaskSDIWatchdogEnable12) << endl
2466  << "SDI3-SDI4 Relay Watchdog: " << EnabDisab(inRegValue & kRegMaskSDIWatchdogEnable34) << endl
2467  << "SDI1-SDI2 Relay Position: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayPosition12) << endl
2468  << "SDI3-SDI4 Relay Position: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayPosition34) << endl
2469  << "Watchdog Timer Status: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIWatchdogStatus);
2470  }
2471  else
2472  oss << "(SDI bypass relays not supported)";
2473  return oss.str();
2474  }
2475  } mDecodeRelayCtrlStat;
2476 
2477  struct DecodeWatchdogTimeout : public Decoder
2478  {
2479  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2480  {
2481  (void) inRegNum;
2482  ostringstream oss;
2483  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2484  {
2485  const uint32_t ticks8nanos (inRegValue); // number of 8-nanosecond ticks
2486  const double microsecs (double(ticks8nanos) * 8.0 / 1000.0);
2487  const double millisecs (microsecs / 1000.0);
2488  oss << "Watchdog Timeout [8-ns ticks]: " << xHEX0N(ticks8nanos,8) << " (" << DEC(ticks8nanos) << ")" << endl
2489  << "Watchdog Timeout [usec]: " << microsecs << endl
2490  << "Watchdog Timeout [msec]: " << millisecs;
2491  }
2492  else
2493  oss << "(SDI bypass relays not supported)";
2494  return oss.str();
2495  }
2496  } mDecodeWatchdogTimeout;
2497 
2498  struct DecodeWatchdogKick : public Decoder
2499  {
2500  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2501  {
2502  (void) inRegNum;
2503  ostringstream oss;
2504  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2505  {
2506  const uint32_t whichReg(inRegNum - kRegSDIWatchdogKick1);
2507  NTV2_ASSERT(whichReg < 2);
2508  const uint32_t expectedValue(whichReg ? 0x01234567 : 0xA5A55A5A);
2509  oss << xHEX0N(inRegValue,8);
2510  if (inRegValue == expectedValue)
2511  oss << " (Normal)";
2512  else
2513  oss << " (Not expected, should be " << xHEX0N(expectedValue,8) << ")";
2514  }
2515  else
2516  oss << "(SDI bypass relays not supported)";
2517  return oss.str();
2518  }
2519  } mDecodeWatchdogKick;
2520 
2521  struct DecodeInputVPID: public Decoder
2522  {
2523  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2524  {
2525  (void) inRegNum;
2526  (void) inDeviceID;
2527  const uint32_t regValue (NTV2EndianSwap32(inRegValue)); // Input VPID register values require endian-swap
2528  ostringstream oss;
2529  AJALabelValuePairs info;
2530  const CNTV2VPID ntv2vpid(regValue);
2531  PrintLabelValuePairs(oss, ntv2vpid.GetInfo(info));
2532  return oss.str();
2533  }
2534  } mVPIDInpRegDecoder;
2535 
2536  struct DecodeOutputVPID: public Decoder
2537  {
2538  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2539  {
2540  (void) inRegNum;
2541  (void) inDeviceID;
2542  ostringstream oss;
2543  AJALabelValuePairs info;
2544  const CNTV2VPID ntv2vpid(inRegValue);
2545  PrintLabelValuePairs(oss, ntv2vpid.GetInfo(info));
2546  return oss.str();
2547  }
2548  } mVPIDOutRegDecoder;
2549 
2550  struct DecodeBitfileDateTime : public Decoder
2551  {
2552  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2553  {
2554  (void) inDeviceID;
2555  ostringstream oss;
2556  if (inRegNum == kRegBitfileDate)
2557  {
2558  const UWord yyyy ((inRegValue & 0xFFFF0000) >> 16);
2559  const UWord mm ((inRegValue & 0x0000FF00) >> 8);
2560  const UWord dd (inRegValue & 0x000000FF);
2561  if (yyyy > 0x2015 && mm > 0 && mm < 0x13 && dd > 0 && dd < 0x32)
2562  oss << "Bitfile Date: " << HEX0N(mm,2) << "/" << HEX0N(dd,2) << "/" << HEX0N(yyyy,4);
2563  else
2564  oss << "Bitfile Date: " << xHEX0N(inRegValue, 8);
2565  }
2566  else if (inRegNum == kRegBitfileTime)
2567  {
2568  const UWord hh ((inRegValue & 0x00FF0000) >> 16);
2569  const UWord mm ((inRegValue & 0x0000FF00) >> 8);
2570  const UWord ss (inRegValue & 0x000000FF);
2571  if (hh < 0x24 && mm < 0x60 && ss < 0x60)
2572  oss << "Bitfile Time: " << HEX0N(hh,2) << ":" << HEX0N(mm,2) << ":" << HEX0N(ss,2);
2573  else
2574  oss << "Bitfile Time: " << xHEX0N(inRegValue, 8);
2575  }
2576  else NTV2_ASSERT(false); // impossible
2577  return oss.str();
2578  }
2579  } mDecodeBitfileDateTime;
2580 
2581  struct DecodeBoardID : public Decoder
2582  {
2583  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2584  { (void) inRegNum; (void) inDeviceID;
2585  const string str1 (::NTV2DeviceIDToString(NTV2DeviceID(inRegValue), false));
2586  const string str2 (::NTV2DeviceIDToString(NTV2DeviceID(inRegValue), true));
2587  ostringstream oss;
2588  oss << "NTV2DeviceID: " << ::NTV2DeviceIDString(NTV2DeviceID(inRegValue)) << endl
2589  << "Device Name: '" << str1 << "'";
2590  if (str1 != str2)
2591  oss << endl
2592  << "Retail Device Name: '" << str2 << "'";
2593  return oss.str();
2594  }
2595  } mDecodeBoardID;
2596 
2597  struct DecodeDynFWUpdateCounts : public Decoder
2598  {
2599  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2600  { (void) inRegNum; (void) inDeviceID;
2601  ostringstream oss;
2602  oss << "# attempts: " << DEC(inRegValue >> 16) << endl
2603  << "# successes: " << DEC(inRegValue & 0x0000FFFF);
2604  return oss.str();
2605  }
2606  } mDecodeDynFWUpdateCounts;
2607 
2608  struct DecodeFWUserID : public Decoder
2609  {
2610  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2611  { (void) inRegNum; (void) inDeviceID;
2612  ostringstream oss;
2613  if (inRegValue)
2614  oss << "Current Design ID: " << xHEX0N(NTV2BitfileHeaderParser::GetDesignID(inRegValue),4) << endl
2615  << "Current Design Version: " << xHEX0N(NTV2BitfileHeaderParser::GetDesignVersion(inRegValue),4) << endl
2616  << "Current Bitfile ID: " << xHEX0N(NTV2BitfileHeaderParser::GetBitfileID(inRegValue),4) << endl
2617  << "Current Bitfile Version: " << xHEX0N(NTV2BitfileHeaderParser::GetBitfileVersion(inRegValue),4);
2618  return oss.str();
2619  }
2620  } mDecodeFirmwareUserID;
2621 
2622  struct DecodeCanDoStatus : public Decoder
2623  {
2624  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2625  { (void) inRegNum; (void) inDeviceID;
2626  ostringstream oss;
2627  oss << "Has CanConnect Xpt Route ROM: " << YesNo(inRegValue & BIT(0)) << endl
2628  << "AudioSystems can start on VBI: " << YesNo(inRegValue & BIT(1));
2629  return oss.str();
2630  }
2631  } mDecodeCanDoStatus;
2632 
2633  struct DecodeVidControlReg : public Decoder // Bit31=Is16x9 | Bit30=IsMono
2634  {
2635  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2636  {
2637  (void) inRegNum;
2638  (void) inDeviceID;
2639  const bool is16x9 ((inRegValue & BIT(31)) != 0);
2640  const bool isMono ((inRegValue & BIT(30)) != 0);
2641  ostringstream oss;
2642  oss << "Aspect Ratio: " << (is16x9 ? "16x9" : "4x3") << endl
2643  << "Depth: " << (isMono ? "Monochrome" : "Color");
2644  return oss.str();
2645  }
2646  } mDecodeVidControlReg;
2647 
2648  struct DecodeVidIntControl : public Decoder
2649  {
2650  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2651  {
2652  (void) inRegNum;
2653  (void) inDeviceID;
2654  ostringstream oss;
2655  oss << "Output 1 Vertical Enable: " << YesNo(inRegValue & BIT(0)) << endl
2656  << "Input 1 Vertical Enable: " << YesNo(inRegValue & BIT(1)) << endl
2657  << "Input 2 Vertical Enable: " << YesNo(inRegValue & BIT(2)) << endl
2658  << "Audio Out Wrap Interrupt Enable: " << YesNo(inRegValue & BIT(4)) << endl
2659  << "Audio In Wrap Interrupt Enable: " << YesNo(inRegValue & BIT(5)) << endl
2660  << "Wrap Rate Interrupt Enable: " << YesNo(inRegValue & BIT(6)) << endl
2661  << "UART Tx Interrupt Enable" << YesNo(inRegValue & BIT(7)) << endl
2662  << "UART Rx Interrupt Enable" << YesNo(inRegValue & BIT(8)) << endl
2663  << "UART Rx Interrupt Clear" << ActInact(inRegValue & BIT(15)) << endl
2664  << "UART 2 Tx Interrupt Enable" << YesNo(inRegValue & BIT(17)) << endl
2665  << "Output 2 Vertical Enable: " << YesNo(inRegValue & BIT(18)) << endl
2666  << "Output 3 Vertical Enable: " << YesNo(inRegValue & BIT(19)) << endl
2667  << "Output 4 Vertical Enable: " << YesNo(inRegValue & BIT(20)) << endl
2668  << "Output 4 Vertical Clear: " << ActInact(inRegValue & BIT(21)) << endl
2669  << "Output 3 Vertical Clear: " << ActInact(inRegValue & BIT(22)) << endl
2670  << "Output 2 Vertical Clear: " << ActInact(inRegValue & BIT(23)) << endl
2671  << "UART Tx Interrupt Clear" << ActInact(inRegValue & BIT(24)) << endl
2672  << "Wrap Rate Interrupt Clear" << ActInact(inRegValue & BIT(25)) << endl
2673  << "UART 2 Tx Interrupt Clear" << ActInact(inRegValue & BIT(26)) << endl
2674  << "Audio Out Wrap Interrupt Clear" << ActInact(inRegValue & BIT(27)) << endl
2675  << "Input 2 Vertical Clear: " << ActInact(inRegValue & BIT(29)) << endl
2676  << "Input 1 Vertical Clear: " << ActInact(inRegValue & BIT(30)) << endl
2677  << "Output 1 Vertical Clear: " << ActInact(inRegValue & BIT(31));
2678  return oss.str();
2679  }
2680  } mDecodeVidIntControl;
2681 
2682  struct DecodeVidIntControl2 : public Decoder
2683  {
2684  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2685  {
2686  (void) inRegNum;
2687  (void) inDeviceID;
2688  ostringstream oss;
2689  oss << "Input 3 Vertical Enable: " << YesNo(inRegValue & BIT(1)) << endl
2690  << "Input 4 Vertical Enable: " << YesNo(inRegValue & BIT(2)) << endl
2691  << "Input 5 Vertical Enable: " << YesNo(inRegValue & BIT(8)) << endl
2692  << "Input 6 Vertical Enable: " << YesNo(inRegValue & BIT(9)) << endl
2693  << "Input 7 Vertical Enable: " << YesNo(inRegValue & BIT(10)) << endl
2694  << "Input 8 Vertical Enable: " << YesNo(inRegValue & BIT(11)) << endl
2695  << "Output 5 Vertical Enable: " << YesNo(inRegValue & BIT(12)) << endl
2696  << "Output 6 Vertical Enable: " << YesNo(inRegValue & BIT(13)) << endl
2697  << "Output 7 Vertical Enable: " << YesNo(inRegValue & BIT(14)) << endl
2698  << "Output 8 Vertical Enable: " << YesNo(inRegValue & BIT(15)) << endl
2699  << "Output 8 Vertical Clear: " << ActInact(inRegValue & BIT(16)) << endl
2700  << "Output 7 Vertical Clear: " << ActInact(inRegValue & BIT(17)) << endl
2701  << "Output 6 Vertical Clear: " << ActInact(inRegValue & BIT(18)) << endl
2702  << "Output 5 Vertical Clear: " << ActInact(inRegValue & BIT(19)) << endl
2703  << "Input 8 Vertical Clear: " << ActInact(inRegValue & BIT(25)) << endl
2704  << "Input 7 Vertical Clear: " << ActInact(inRegValue & BIT(26)) << endl
2705  << "Input 6 Vertical Clear: " << ActInact(inRegValue & BIT(27)) << endl
2706  << "Input 5 Vertical Clear: " << ActInact(inRegValue & BIT(28)) << endl
2707  << "Input 4 Vertical Clear: " << ActInact(inRegValue & BIT(29)) << endl
2708  << "Input 3 Vertical Clear: " << ActInact(inRegValue & BIT(30));
2709  return oss.str();
2710  }
2711  } mDecodeVidIntControl2;
2712 
2713  struct DecodeStatusReg : public Decoder
2714  {
2715  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2716  {
2717  (void) inRegNum;
2718  (void) inDeviceID;
2719  ostringstream oss;
2720  oss << "Input 1 Vertical Blank: " << ActInact(inRegValue & BIT(20)) << endl
2721  << "Input 1 Field ID: " << (inRegValue & BIT(21) ? "1" : "0") << endl
2722  << "Input 1 Vertical Interrupt: " << ActInact(inRegValue & BIT(30)) << endl
2723  << "Input 2 Vertical Blank: " << ActInact(inRegValue & BIT(18)) << endl
2724  << "Input 2 Field ID: " << (inRegValue & BIT(19) ? "1" : "0") << endl
2725  << "Input 2 Vertical Interrupt: " << ActInact(inRegValue & BIT(29)) << endl
2726  << "Output 1 Vertical Blank: " << ActInact(inRegValue & BIT(22)) << endl
2727  << "Output 1 Field ID: " << (inRegValue & BIT(23) ? "1" : "0") << endl
2728  << "Output 1 Vertical Interrupt: " << ActInact(inRegValue & BIT(31)) << endl
2729  << "Output 2 Vertical Blank: " << ActInact(inRegValue & BIT(4)) << endl
2730  << "Output 2 Field ID: " << (inRegValue & BIT(5) ? "1" : "0") << endl
2731  << "Output 2 Vertical Interrupt: " << ActInact(inRegValue & BIT(8)) << endl;
2732  if (::NTV2DeviceGetNumVideoOutputs(inDeviceID) > 2)
2733  oss << "Output 3 Vertical Blank: " << ActInact(inRegValue & BIT(2)) << endl
2734  << "Output 3 Field ID: " << (inRegValue & BIT(3) ? "1" : "0") << endl
2735  << "Output 3 Vertical Interrupt: " << ActInact(inRegValue & BIT(7)) << endl
2736  << "Output 4 Vertical Blank: " << ActInact(inRegValue & BIT(0)) << endl
2737  << "Output 4 Field ID: " << (inRegValue & BIT(1) ? "1" : "0") << endl
2738  << "Output 4 Vertical Interrupt: " << ActInact(inRegValue & BIT(6)) << endl;
2739  oss << "Aux Vertical Interrupt: " << ActInact(inRegValue & BIT(12)) << endl
2740  << "I2C 1 Interrupt: " << ActInact(inRegValue & BIT(14)) << endl
2741  << "I2C 2 Interrupt: " << ActInact(inRegValue & BIT(13)) << endl
2742  << "Chunk Rate Interrupt: " << ActInact(inRegValue & BIT(16)) << endl;
2743  if (::NTV2DeviceGetNumSerialPorts(inDeviceID))
2744  oss << "Generic UART Interrupt: " << ActInact(inRegValue & BIT(9)) << endl
2745  << "Uart 1 Rx Interrupt: " << ActInact(inRegValue & BIT(15)) << endl
2746  << "Uart 1 Tx Interrupt: " << ActInact(inRegValue & BIT(24)) << endl;
2747  if (::NTV2DeviceGetNumSerialPorts(inDeviceID) > 1)
2748  oss << "Uart 2 Tx Interrupt: " << ActInact(inRegValue & BIT(26)) << endl;
2749  if (::NTV2DeviceGetNumLTCInputs(inDeviceID))
2750  oss << "LTC In 1 Present: " << YesNo(inRegValue & BIT(17)) << endl;
2751  oss << "Wrap Rate Interrupt: " << ActInact(inRegValue & BIT(25)) << endl
2752  << "Audio Out Wrap Interrupt: " << ActInact(inRegValue & BIT(27)) << endl
2753  << "Audio 50Hz Interrupt: " << ActInact(inRegValue & BIT(28));
2754  return oss.str();
2755  }
2756  } mDecodeStatusReg;
2757 
2758  struct DecodeCPLDVersion : public Decoder
2759  {
2760  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2761  {
2762  (void) inRegNum;
2763  (void) inDeviceID;
2764  ostringstream oss;
2765  oss << "CPLD Version: " << DEC(inRegValue & (BIT(0)|BIT(1))) << endl
2766  << "Failsafe Bitfile Loaded: " << (inRegValue & BIT(4) ? "Yes" : "No") << endl
2767  << "Force Reload: " << YesNo(inRegValue & BIT(8));
2768  ULWord pcbRev ((inRegValue & 0xF0000000) >> 28);
2769  if (pcbRev) oss << endl
2770  << "PCB Version: " << xHEX0N(pcbRev,2);
2771  return oss.str();
2772  }
2773  } mDecodeCPLDVersion;
2774 
2775  struct DecodeStatus2Reg : public Decoder
2776  {
2777  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2778  {
2779  (void) inRegNum;
2780  (void) inDeviceID;
2781  static const uint8_t bitNumsInputVBlank[] = {20, 18, 16, 14, 12, 10}; // Input 3/4/5/6/7/8 Vertical Blank
2782  static const uint8_t bitNumsInputFieldID[] = {21, 19, 17, 15, 13, 11}; // Input 3/4/5/6/7/8 Field ID
2783  static const uint8_t bitNumsInputVertInt[] = {30, 29, 28, 27, 26, 25}; // Input 3/4/5/6/7/8 Vertical Interrupt
2784  static const uint8_t bitNumsOutputVBlank[] = { 8, 6, 4, 2}; // Output 5/6/7/8 Vertical Blank
2785  static const uint8_t bitNumsOutputFieldID[] = { 9, 7, 5, 3}; // Output 5/6/7/8 Field ID
2786  static const uint8_t bitNumsOutputVertInt[] = {31, 24, 23, 22}; // Output 5/6/7/8 Vertical Interrupt
2787  ostringstream oss;
2788  for (unsigned ndx(0); ndx < 6; ndx++)
2789  oss << "Input " << (ndx+3) << " Vertical Blank: " << ActInact(inRegValue & BIT(bitNumsInputVBlank[ndx])) << endl
2790  << "Input " << (ndx+3) << " Field ID: " << (inRegValue & BIT(bitNumsInputFieldID[ndx]) ? "1" : "0") << endl
2791  << "Input " << (ndx+3) << " Vertical Interrupt: " << ActInact(inRegValue & BIT(bitNumsInputVertInt[ndx])) << endl;
2792  for (unsigned ndx(0); ndx < 4; ndx++)
2793  oss << "Output " << (ndx+5) << " Vertical Blank: " << ActInact(inRegValue & BIT(bitNumsOutputVBlank[ndx])) << endl
2794  << "Output " << (ndx+5) << " Field ID: " << (inRegValue & BIT(bitNumsOutputFieldID[ndx]) ? "1" : "0") << endl
2795  << "Output " << (ndx+5) << " Vertical Interrupt: " << ActInact(inRegValue & BIT(bitNumsOutputVertInt[ndx])) << endl;
2796  oss << "HDMI In Hot-Plug Detect Interrupt: " << ActInact(inRegValue & BIT(0)) << endl
2797  << "HDMI In Chip Interrupt: " << ActInact(inRegValue & BIT(1));
2798  return oss.str();
2799  }
2800  } mDecodeStatus2Reg;
2801 
2802  struct DecodeInputStatusReg : public Decoder
2803  {
2804  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2805  {
2806  (void) inRegNum;
2807  (void) inDeviceID;
2808  NTV2FrameRate fRate1 (NTV2FrameRate( (inRegValue & (BIT( 0)|BIT( 1)|BIT( 2) )) | ((inRegValue & BIT(28)) >> (28-3)) ));
2809  NTV2FrameRate fRate2 (NTV2FrameRate(((inRegValue & (BIT( 8)|BIT( 9)|BIT(10) )) >> 8) | ((inRegValue & BIT(29)) >> (29-3)) ));
2810  NTV2FrameRate fRateRf (NTV2FrameRate(((inRegValue & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) >> 16) ));
2811  ostringstream oss;
2812  oss << "Input 1 Frame Rate: " << ::NTV2FrameRateToString(fRate1, true) << endl
2813  << "Input 1 Geometry: ";
2814  if (BIT(30) & inRegValue)
2815  switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2816  {
2817  case 0: oss << "2K x 1080"; break;
2818  case 1: oss << "2K x 1556"; break;
2819  default: oss << "Invalid HI"; break;
2820  }
2821  else
2822  switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2823  {
2824  case 0: oss << "Unknown"; break;
2825  case 1: oss << "525"; break;
2826  case 2: oss << "625"; break;
2827  case 3: oss << "750"; break;
2828  case 4: oss << "1125"; break;
2829  case 5: oss << "1250"; break;
2830  case 6: case 7: oss << "Reserved"; break;
2831  default: oss << "Invalid LO"; break;
2832  }
2833  oss << endl
2834  << "Input 1 Scan Mode: " << ((BIT(7) & inRegValue) ? "Progressive" : "Interlaced") << endl
2835  << "Input 2 Frame Rate: " << ::NTV2FrameRateToString(fRate2, true) << endl
2836  << "Input 2 Geometry: ";
2837  if (BIT(31) & inRegValue)
2838  switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2839  {
2840  case 0: oss << "2K x 1080"; break;
2841  case 1: oss << "2K x 1556"; break;
2842  default: oss << "Invalid HI"; break;
2843  }
2844  else
2845  switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2846  {
2847  case 0: oss << "Unknown"; break;
2848  case 1: oss << "525"; break;
2849  case 2: oss << "625"; break;
2850  case 3: oss << "750"; break;
2851  case 4: oss << "1125"; break;
2852  case 5: oss << "1250"; break;
2853  case 6: case 7: oss << "Reserved"; break;
2854  default: oss << "Invalid LO"; break;
2855  }
2856  oss << endl
2857  << "Input 2 Scan Mode: " << ((BIT(15) & inRegValue) ? "Progressive" : "Interlaced") << endl
2858  << "Reference Frame Rate: " << ::NTV2FrameRateToString(fRateRf, true) << endl
2859  << "Reference Geometry: ";
2860  switch (((BIT(20)|BIT(21)|BIT(22)) & inRegValue) >> 20) // Ref scan geometry
2861  {
2862  case 0: oss << "NTV2_SG_UNKNOWN"; break;
2863  case 1: oss << "NTV2_SG_525"; break;
2864  case 2: oss << "NTV2_SG_625"; break;
2865  case 3: oss << "NTV2_SG_750"; break;
2866  case 4: oss << "NTV2_SG_1125"; break;
2867  case 5: oss << "NTV2_SG_1250"; break;
2868  default: oss << "Invalid"; break;
2869  }
2870  oss << endl
2871  << "Reference Scan Mode: " << ((BIT(23) & inRegValue) ? "Progressive" : "Interlaced") << endl
2872  << "AES Channel 1-2: " << ((BIT(24) & inRegValue) ? "Invalid" : "Valid") << endl
2873  << "AES Channel 3-4: " << ((BIT(25) & inRegValue) ? "Invalid" : "Valid") << endl
2874  << "AES Channel 5-6: " << ((BIT(26) & inRegValue) ? "Invalid" : "Valid") << endl
2875  << "AES Channel 7-8: " << ((BIT(27) & inRegValue) ? "Invalid" : "Valid");
2876  return oss.str();
2877  }
2878  } mDecodeInputStatusReg;
2879 
2880  struct DecodeSDIInputStatusReg : public Decoder
2881  {
2882  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2883  {
2884  (void) inDeviceID;
2885  uint16_t numSpigots(0), startSpigot(0), doTsiMuxSync(0);
2886  ostringstream oss;
2887  switch (inRegNum)
2888  {
2889  case kRegSDIInput3GStatus: numSpigots = 2; startSpigot = 1; doTsiMuxSync = 1; break;
2890  case kRegSDIInput3GStatus2: numSpigots = 2; startSpigot = 3; break;
2891  case kRegSDI5678Input3GStatus: numSpigots = 4; startSpigot = 5; break;
2892  }
2893  if ((startSpigot-1) >= ::NTV2DeviceGetNumVideoInputs(inDeviceID))
2894  return oss.str(); // Skip if no such SDI inputs
2895 
2896  for (uint16_t spigotNdx(0); spigotNdx < numSpigots; )
2897  {
2898  const uint16_t spigotNum (spigotNdx + startSpigot);
2899  const uint8_t statusBits ((inRegValue >> (spigotNdx*8)) & 0xFF);
2900  const uint8_t speedBits (statusBits & 0xC1);
2901  ostringstream ossSpeed, ossSpigot;
2902  ossSpigot << "SDI In " << spigotNum << " ";
2903  const string spigotLabel (ossSpigot.str());
2904  if (speedBits & 0x01) ossSpeed << " 3G";
2905  if (::NTV2DeviceCanDo12GSDI(inDeviceID))
2906  {
2907  if (speedBits & 0x40) ossSpeed << " 6G";
2908  if (speedBits & 0x80) ossSpeed << " 12G";
2909  }
2910  if (speedBits == 0) ossSpeed << " 1.5G";
2911  oss << spigotLabel << "Link Speed:" << ossSpeed.str() << endl
2912  << spigotLabel << "SMPTE Level B: " << YesNo(statusBits & 0x02) << endl
2913  << spigotLabel << "Link A VPID Valid: " << YesNo(statusBits & 0x10) << endl
2914  << spigotLabel << "Link B VPID Valid: " << YesNo(statusBits & 0x20) << endl;
2915  if (::NTV2DeviceCanDo3GLevelConversion(inDeviceID))
2916  oss << spigotLabel << "3Gb-to-3Ga Conversion: " << EnabDisab(statusBits & 0x04);
2917  else
2918  oss << spigotLabel << "3Gb-to-3Ga Conversion: n/a";
2919  if (++spigotNdx < numSpigots)
2920  oss << endl;
2921  } // for each spigot
2922  if (doTsiMuxSync && ::NTV2DeviceCanDo425Mux(inDeviceID))
2923  for (UWord tsiMux(0); tsiMux < 4; ++tsiMux)
2924  oss << endl
2925  << "TsiMux" << DEC(tsiMux+1) << " Sync Fail: " << ((inRegValue & (0x00010000UL << tsiMux)) ? "FAILED" : "OK");
2926  return oss.str();
2927  }
2928  } mDecodeSDIInputStatusReg;
2929 
2930  struct DecodeSDIInputStatus2Reg : public Decoder
2931  {
2932  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2933  {
2934  (void) inDeviceID;
2935  const string sOdd (inRegNum == kRegInputStatus2 ? "Input 3" : (inRegNum == kRegInput56Status ? "Input 5" : "Input 7"));
2936  const string sEven (inRegNum == kRegInputStatus2 ? "Input 4" : (inRegNum == kRegInput56Status ? "Input 6" : "Input 8"));
2937  const NTV2FrameRate fRate1 (NTV2FrameRate( (inRegValue & (BIT( 0)|BIT( 1)|BIT( 2) )) | ((inRegValue & BIT(28)) >> (28-3)) ));
2938  const NTV2FrameRate fRate2 (NTV2FrameRate(((inRegValue & (BIT( 8)|BIT( 9)|BIT(10) )) >> 8) | ((inRegValue & BIT(29)) >> (29-3)) ));
2939  ostringstream oss;
2940  oss << sOdd << " Scan Mode: " << ((BIT(7) & inRegValue) ? "Progressive" : "Interlaced") << endl
2941  << sOdd << " Frame Rate: " << ::NTV2FrameRateToString(fRate1, true) << endl
2942  << sOdd << " Geometry: ";
2943  if (BIT(30) & inRegValue) switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2944  {
2945  case 0: oss << "2K x 1080"; break;
2946  case 1: oss << "2K x 1556"; break;
2947  default: oss << "Invalid HI"; break;
2948  }
2949  else switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2950  {
2951  case 0: oss << "Unknown"; break;
2952  case 1: oss << "525"; break;
2953  case 2: oss << "625"; break;
2954  case 3: oss << "750"; break;
2955  case 4: oss << "1125"; break;
2956  case 5: oss << "1250"; break;
2957  case 6: case 7: oss << "Reserved"; break;
2958  default: oss << "Invalid LO"; break;
2959  }
2960  oss << endl
2961  << sEven << " Scan Mode: " << ((BIT(15) & inRegValue) ? "Progressive" : "Interlaced") << endl
2962  << sEven << " Frame Rate: " << ::NTV2FrameRateToString(fRate2, true) << endl
2963  << sEven << " Geometry: ";
2964  if (BIT(31) & inRegValue) switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2965  {
2966  case 0: oss << "2K x 1080"; break;
2967  case 1: oss << "2K x 1556"; break;
2968  default: oss << "Invalid HI"; break;
2969  }
2970  else switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2971  {
2972  case 0: oss << "Unknown"; break;
2973  case 1: oss << "525"; break;
2974  case 2: oss << "625"; break;
2975  case 3: oss << "750"; break;
2976  case 4: oss << "1125"; break;
2977  case 5: oss << "1250"; break;
2978  case 6: case 7: oss << "Reserved"; break;
2979  default: oss << "Invalid LO"; break;
2980  }
2981  return oss.str();
2982  }
2983  } mDecodeSDIInputStatus2Reg;
2984 
2985  struct DecodeFS1RefSelectReg : public Decoder
2986  {
2987  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2988  {
2989  (void) inDeviceID; (void) inRegNum; // kRegFS1ReferenceSelect
2990  ostringstream oss;
2991  oss << "BNC Select(LHi): " << (inRegValue & 0x00000010 ? "LTCIn1" : "Ref") << endl
2992  << "Ref BNC (Corvid): " << EnabDisab(inRegValue & 0x00000020) << endl
2993  << "LTC Present (also Reg 21): " << YesNo(inRegValue & 0x00000040) << endl
2994  << "LTC Emb Out Enable: " << YesNo(inRegValue & 0x00000080) << endl
2995  << "LTC Emb In Enable: " << YesNo(inRegValue & 0x00000100) << endl
2996  << "LTC Emb In Received: " << YesNo(inRegValue & 0x00000200) << endl
2997  << "LTC BNC Out Source: " << (inRegValue & 0x00000400 ? "E-E" : "Reg112/113");
2998  return oss.str();
2999  }
3000  } mDecodeFS1RefSelectReg;
3001 
3002  struct DecodeLTCStatusControlReg : public Decoder
3003  {
3004  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3005  {
3006  (void) inDeviceID; (void) inRegNum; // kRegLTCStatusControl
3007  const uint16_t LTC1InTimingSelect ((inRegValue >> 1) & 0x0000007);
3008  const uint16_t LTC2InTimingSelect ((inRegValue >> 9) & 0x0000007);
3009  const uint16_t LTC1OutTimingSelect ((inRegValue >> 16) & 0x0000007);
3010  const uint16_t LTC2OutTimingSelect ((inRegValue >> 20) & 0x0000007);
3011  ostringstream oss;
3012  oss << "LTC 1 Input Present: " << YesNo(inRegValue & 0x00000001) << endl
3013  << "LTC 1 Input FB Timing Select): " << xHEX0N(LTC1InTimingSelect,2) << " (" << DEC(LTC1InTimingSelect) << ")" << endl
3014  << "LTC 1 Bypass: " << EnabDisab(inRegValue & 0x00000010) << endl
3015  << "LTC 1 Bypass Select: " << DEC(ULWord((inRegValue >> 5) & 0x00000001)) << endl
3016  << "LTC 2 Input Present: " << YesNo(inRegValue & 0x00000100) << endl
3017  << "LTC 2 Input FB Timing Select): " << xHEX0N(LTC2InTimingSelect,2) << " (" << DEC(LTC2InTimingSelect) << ")" << endl
3018  << "LTC 2 Bypass: " << EnabDisab(inRegValue & 0x00001000) << endl
3019  << "LTC 2 Bypass Select: " << DEC(ULWord((inRegValue >> 13) & 0x00000001)) << endl
3020  << "LTC 1 Output FB Timing Select): " << xHEX0N(LTC1OutTimingSelect,2) << " (" << DEC(LTC1OutTimingSelect) << ")" << endl
3021  << "LTC 2 Output FB Timing Select): " << xHEX0N(LTC2OutTimingSelect,2) << " (" << DEC(LTC2OutTimingSelect) << ")";
3022  return oss.str();
3023  }
3024  } mLTCStatusControlDecoder;
3025 
3026  struct DecodeAudDetectReg : public Decoder
3027  {
3028  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3029  {
3030  (void) inDeviceID;
3031  ostringstream oss;
3032  switch (inRegNum)
3033  {
3034  case kRegAud1Detect:
3035  case kRegAudDetect2:
3036  for (uint16_t num(0); num < 8; )
3037  {
3038  const uint16_t group (num / 2);
3039  const bool isChan34 (num & 1);
3040  oss << "Group " << group << " CH " << (isChan34 ? "3-4: " : "1-2: ") << (inRegValue & BIT(num) ? "Present" : "Absent");
3041  if (++num < 8)
3042  oss << endl;
3043  }
3044  break;
3045 
3046  case kRegAudioDetect5678:
3047  break;
3048  }
3049  return oss.str();
3050  }
3051  } mDecodeAudDetectReg;
3052 
3053  struct DecodeAudControlReg : public Decoder
3054  {
3055  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3056  {
3057  (void) inRegNum;
3058  (void) inDeviceID;
3059  static const string ChStrs [] = { "Ch 1/2", "Ch 3/4", "Ch 5/6", "Ch 7/8" };
3060  uint16_t sdiOutput (0);
3061  switch (inRegNum)
3062  { case kRegAud1Control: sdiOutput = 1; break;
3063  case kRegAud3Control: sdiOutput = 3; break;
3064  case kRegAud5Control: sdiOutput = 5; break;
3065  case kRegAud7Control: sdiOutput = 7; break;
3066  default: break;
3067  }
3068 
3069  ostringstream oss;
3070  oss << "Audio Capture: " << EnabDisab(BIT(0) & inRegValue) << endl
3071  << "Audio Loopback: " << EnabDisab(BIT(3) & inRegValue) << endl
3072  << "Audio Input: " << DisabEnab(BIT(8) & inRegValue) << endl
3073  << "Audio Output: " << DisabEnab(BIT(9) & inRegValue) << endl
3074  << "Output Paused: " << YesNo(BIT(11) & inRegValue) << endl;
3075  if (sdiOutput)
3076  oss << "Audio Embedder SDIOut" << sdiOutput << ": " << DisabEnab(BIT(13) & inRegValue) << endl
3077  << "Audio Embedder SDIOut" << (sdiOutput+1) << ": " << DisabEnab(BIT(15) & inRegValue) << endl;
3078 
3079  oss << "A/V Sync Mode: " << EnabDisab(BIT(15) & inRegValue) << endl
3080  << "AES Rate Converter: " << DisabEnab(BIT(19) & inRegValue) << endl
3081  << "Audio Buffer Format: " << (BIT(20) & inRegValue ? "16-Channel " : (BIT(16) & inRegValue ? "8-Channel " : "6-Channel ")) << endl
3082  << (BIT(18) & inRegValue ? "96kHz" : "48kHz") << endl
3083  << (BIT(18) & inRegValue ? "96kHz Support" : "48kHz Support") << endl
3084  // << (BIT(22) & inRegValue ? "Embedded Support" : "No Embedded Support") << endl // JeffL says this bit is obsolete
3085  << "Slave Mode (64-chl): " << EnabDisab(BIT(23) & inRegValue) << endl // Redeployed in 16.2 for 64-ch audio
3086  << "K-box, Monitor: " << ChStrs [(BIT(24) & BIT(25) & inRegValue) >> 24] << endl
3087  << "K-Box Input: " << (BIT(26) & inRegValue ? "XLR" : "BNC") << endl
3088  << "K-Box: " << (BIT(27) & inRegValue ? "Present" : "Absent") << endl
3089  << "Cable: " << (BIT(28) & inRegValue ? "XLR" : "BNC") << endl
3090  << "Audio Buffer Size: " << (BIT(31) & inRegValue ? "4 MB" : "1 MB");
3091  return oss.str();
3092  }
3093  } mDecodeAudControlReg;
3094 
3095  struct DecodeAudSourceSelectReg : public Decoder
3096  {
3097  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3098  {
3099  (void) inRegNum;
3100  (void) inDeviceID;
3101  static const string SrcStrs [] = { "AES Input", "Embedded Groups 1 and 2", "" };
3102  static const unsigned SrcStrMap [] = { 0, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 };
3103  const uint16_t vidInput = (inRegValue & BIT(23) ? 2 : 0) + (inRegValue & BIT(16) ? 1 : 0);
3104  // WARNING! BIT(23) had better be clear on 0 & 1-input boards!!
3105  ostringstream oss;
3106  oss << "Audio Source: " << SrcStrs [SrcStrMap [(BIT(0) | BIT(1) | BIT(2) | BIT(3)) & inRegValue]] << endl
3107  << "Embedded Source Select: Video Input " << (1 + vidInput) << endl
3108  << "AES Sync Mode bit (fib): " << EnabDisab(inRegValue & BIT(18)) << endl
3109  << "PCM disabled: " << YesNo(inRegValue & BIT(17)) << endl
3110  << "Erase head enable: " << YesNo(inRegValue & BIT(19)) << endl
3111  << "Embedded Clock Select: " << (inRegValue & BIT(22) ? "Video Input" : "Board Reference") << endl
3112  << "3G audio source: " << (inRegValue & BIT(21) ? "Data stream 2" : "Data stream 1");
3113  return oss.str();
3114  }
3115  } mDecodeAudSourceSelectReg;
3116 
3117  struct DecodeAudOutputSrcMap : public Decoder
3118  {
3119  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3120  {
3121  (void) inRegNum;
3122  (void) inDeviceID;
3123  static const string AESOutputStrs[] = { "AES Outputs 1-4", "AES Outputs 5-8", "AES Outputs 9-12", "AES Outputs 13-16", ""};
3124  static const string SrcStrs[] = { "AudSys1, Audio Channels 1-4", "AudSys1, Audio Channels 5-8",
3125  "AudSys1, Audio Channels 9-12", "AudSys1, Audio Channels 13-16",
3126  "AudSys2, Audio Channels 1-4", "AudSys2, Audio Channels 5-8",
3127  "AudSys2, Audio Channels 9-12", "AudSys2, Audio Channels 13-16",
3128  "AudSys3, Audio Channels 1-4", "AudSys3, Audio Channels 5-8",
3129  "AudSys3, Audio Channels 9-12", "AudSys3, Audio Channels 13-16",
3130  "AudSys4, Audio Channels 1-4", "AudSys4, Audio Channels 5-8",
3131  "AudSys4, Audio Channels 9-12", "AudSys4, Audio Channels 13-16", ""};
3132  static const unsigned AESChlMappingShifts [4] = {0, 4, 8, 12};
3133 
3134  ostringstream oss;
3135  const uint32_t AESOutMapping (inRegValue & 0x0000FFFF);
3136  const uint32_t AnlgMonInfo ((inRegValue & kRegMaskMonitorSource) >> kRegShiftMonitorSource);
3137  const NTV2AudioSystem AnlgMonAudSys (NTV2AudioSystem(AnlgMonInfo >> 4));
3138  const NTV2AudioChannelPair AnlgMonChlPair (NTV2AudioChannelPair(AnlgMonInfo & 0xF));
3139  for (unsigned AESOutputQuad(0); AESOutputQuad < 4; AESOutputQuad++)
3140  oss << AESOutputStrs[AESOutputQuad] << " Source: " << SrcStrs[(AESOutMapping >> AESChlMappingShifts[AESOutputQuad]) & 0x0000000F] << endl;
3141  oss << "Analog Audio Monitor Output Source: " << ::NTV2AudioSystemToString(AnlgMonAudSys,true) << ", Channels " << ::NTV2AudioChannelPairToString(AnlgMonChlPair,true) << endl;
3142 
3143  // HDMI Audio Output Mapping -- interpretation depends on bit 29 of register 125 kRegHDMIOutControl MULTIREG_SPARSE_BITS
3144  const uint32_t HDMIMonInfo ((inRegValue & kRegMaskHDMIOutAudioSource) >> kRegShiftHDMIOutAudioSource);
3145  {
3146  // HDMI Audio 2-channel Mode:
3147  const NTV2AudioSystem HDMIMonAudSys (NTV2AudioSystem(HDMIMonInfo >> 4));
3148  const NTV2AudioChannelPair HDMIMonChlPair (NTV2AudioChannelPair(HDMIMonInfo & 0xF));
3149  oss << "HDMI 2-Chl Audio Output Source: " << ::NTV2AudioSystemToString(HDMIMonAudSys,true) << ", Channels " << ::NTV2AudioChannelPairToString(HDMIMonChlPair,true) << endl;
3150  }
3151  {
3152  // HDMI Audio 8-channel Mode:
3153  const uint32_t HDMIMon1234Info (HDMIMonInfo & 0x0F);
3154  const NTV2AudioSystem HDMIMon1234AudSys (NTV2AudioSystem(HDMIMon1234Info >> 2));
3155  const NTV2Audio4ChannelSelect HDMIMon1234SrcPairs (NTV2Audio4ChannelSelect(HDMIMon1234Info & 0x3));
3156  const uint32_t HDMIMon5678Info ((HDMIMonInfo >> 4) & 0x0F);
3157  const NTV2AudioSystem HDMIMon5678AudSys (NTV2AudioSystem(HDMIMon5678Info >> 2));
3158  const NTV2Audio4ChannelSelect HDMIMon5678SrcPairs (NTV2Audio4ChannelSelect(HDMIMon5678Info & 0x3));
3159  oss << "or HDMI 8-Chl Audio Output 1-4 Source: " << ::NTV2AudioSystemToString(HDMIMon1234AudSys,true) << ", Channels " << ::NTV2AudioChannelQuadToString(HDMIMon1234SrcPairs,true) << endl
3160  << "or HDMI 8-Chl Audio Output 5-8 Source: " << ::NTV2AudioSystemToString(HDMIMon5678AudSys,true) << ", Channels " << ::NTV2AudioChannelQuadToString(HDMIMon5678SrcPairs,true);
3161  }
3162  return oss.str();
3163  }
3164  } mDecodeAudOutputSrcMap;
3165 
3166  struct DecodePCMControlReg : public Decoder
3167  {
3168  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3169  {
3170  (void) inDeviceID;
3171  ostringstream oss;
3172  const UWord startAudioSystem (inRegNum == kRegPCMControl4321 ? 1 : 5);
3173  for (uint8_t audChan (0); audChan < 4; audChan++)
3174  {
3175  oss << "Audio System " << (startAudioSystem + audChan) << ": ";
3176  const uint8_t pcmBits (uint32_t(inRegValue >> (audChan * 8)) & 0x000000FF);
3177  if (pcmBits == 0x00)
3178  oss << "normal";
3179  else
3180  {
3181  oss << "non-PCM channels";
3182  for (uint8_t chanPair (0); chanPair < 8; chanPair++)
3183  if (pcmBits & (0x01 << chanPair))
3184  oss << " " << (chanPair*2+1) << "-" << (chanPair*2+2);
3185  }
3186  if (audChan < 3)
3187  oss << endl;
3188  }
3189  return oss.str();
3190  }
3191  } mDecodePCMControlReg;
3192 
3193  struct DecodeAudioMixerInputSelectReg : public Decoder
3194  { // kRegAudioMixerInputSelects
3195  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3196  { (void) inDeviceID; (void) inRegNum;
3197  const UWord mainInputSrc((inRegValue ) & 0x0000000F);
3198  const UWord aux1InputSrc((inRegValue >> 4) & 0x0000000F);
3199  const UWord aux2InputSrc((inRegValue >> 8) & 0x0000000F);
3200  ostringstream oss;
3201  oss << "Main Input Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(mainInputSrc)) << " (bits 0-3)" << endl
3202  << "Aux Input 1 Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(aux1InputSrc)) << " (bits 4-7)" << endl
3203  << "Aux Input 2 Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(aux2InputSrc)) << " (bits 8-11)";
3204  return oss.str();
3205  }
3206  } mAudMxrInputSelDecoder;
3207 
3208  struct DecodeAudioMixerGainRegs : public Decoder
3209  { // kRegAudioMixerMainGain,
3210  // kRegAudioMixerAux1GainCh1, kRegAudioMixerAux1GainCh2,
3211  // kRegAudioMixerAux2GainCh1, kRegAudioMixerAux2GainCh2
3212  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3213  { (void)inRegNum; (void)inDeviceID;
3214  static const double kUnityGain (0x00010000);
3215  const bool atUnity (inRegValue == 0x00010000);
3216  ostringstream oss;
3217  if (atUnity)
3218  oss << "Gain: 0 dB (Unity)";
3219  else
3220  {
3221  const double dValue (inRegValue);
3222  const bool aboveUnity (inRegValue >= 0x00010000);
3223  const string plusMinus (atUnity ? "" : (aboveUnity ? "+" : "-"));
3224  const string aboveBelow (atUnity ? "at" : (aboveUnity ? "above" : "below"));
3225  const uint32_t unityDiff (aboveUnity ? inRegValue - 0x00010000 : 0x00010000 - inRegValue);
3226  const double dB (double(20.0) * ::log10(dValue/kUnityGain));
3227  oss << "Gain: " << dB << " dB, " << plusMinus << xHEX0N(unityDiff,6)
3228  << " (" << plusMinus << DEC(unityDiff) << ") " << aboveBelow << " unity gain";
3229  }
3230  return oss.str();
3231  }
3232  } mAudMxrGainDecoder;
3233 
3234  struct DecodeAudioMixerChannelSelectReg : public Decoder
3235  { // kRegAudioMixerChannelSelect
3236  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3237  { (void) inRegNum; (void) inDeviceID;
3238  ostringstream oss;
3239  const uint32_t mainChanPair((inRegValue & kRegMaskAudioMixerChannelSelect ) >> kRegShiftAudioMixerChannelSelect );
3240  const uint32_t powerOfTwo ((inRegValue & kRegMaskAudioMixerLevelSampleCount) >> kRegShiftAudioMixerLevelSampleCount);
3241  oss << "Main Input Source Channel Pair: " << ::NTV2AudioChannelPairToString(NTV2AudioChannelPair(mainChanPair)) << " (bits 0-2)" << endl
3242  << "Level Measurement Sample Count: " << DEC(ULWord(1 << powerOfTwo)) << " (bits 8-15)";
3243  return oss.str();
3244  }
3245  } mAudMxrChanSelDecoder;
3246 
3247 
3248  struct DecodeAudioMixerMutesReg : public Decoder
3249  { // kRegAudioMixerMutes
3250  protected:
3251  typedef std::bitset<16> AudioChannelSet16;
3252  typedef std::bitset<2> AudioChannelSet2;
3253  static void SplitAudioChannelSet16(const AudioChannelSet16 & inChSet, NTV2StringList & outSet, NTV2StringList & outClear)
3254  {
3255  outSet.clear(); outClear.clear();
3256  for (size_t ndx(0); ndx < 16; ndx++)
3257  { ostringstream oss; oss << DEC(ndx+1);
3258  if (inChSet.test(ndx))
3259  outSet.push_back(oss.str());
3260  else
3261  outClear.push_back(oss.str());
3262  }
3263  if (outSet.empty()) outSet.push_back("<none>");
3264  if (outClear.empty()) outClear.push_back("<none>");
3265  }
3266  static void SplitAudioChannelSet2(const AudioChannelSet2 & inChSet, NTV2StringList & outSet, NTV2StringList & outClear)
3267  {
3268  outSet.clear(); outClear.clear(); static const string LR[] = {"L", "R"};
3269  for (size_t ndx(0); ndx < 2; ndx++)
3270  if (inChSet.test(ndx))
3271  outSet.push_back(LR[ndx]);
3272  else
3273  outClear.push_back(LR[ndx]);
3274  if (outSet.empty()) outSet.push_back("<none>");
3275  if (outClear.empty()) outClear.push_back("<none>");
3276  }
3277  public:
3278  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3279  { (void) inRegNum; (void) inDeviceID;
3280  uint32_t mainOutputMuteBits ((inRegValue & kRegMaskAudioMixerOutputChannelsMute) >> kRegShiftAudioMixerOutputChannelsMute); // Bits 0-15
3281  uint32_t mainInputMuteBits ((inRegValue & kRegMaskAudioMixerMainInputEnable ) >> kRegShiftAudioMixerMainInputEnable ); // Bits 16-17
3282  uint32_t aux1InputMuteBits ((inRegValue & kRegMaskAudioMixerAux1InputEnable ) >> kRegShiftAudioMixerAux1InputEnable ); // Bits 18-19
3283  uint32_t aux2InputMuteBits ((inRegValue & kRegMaskAudioMixerAux2InputEnable ) >> kRegShiftAudioMixerAux2InputEnable ); // Bits 20-21
3284  ostringstream oss;
3285  NTV2StringList mutedMainOut, unmutedMainOut, mutedMain, unmutedMain, mutedAux1, unmutedAux1, mutedAux2, unmutedAux2;
3286  SplitAudioChannelSet16(AudioChannelSet16(mainOutputMuteBits), mutedMainOut, unmutedMainOut);
3287  SplitAudioChannelSet2(AudioChannelSet2(mainInputMuteBits), mutedMain, unmutedMain);
3288  SplitAudioChannelSet2(AudioChannelSet2(aux1InputMuteBits), mutedAux1, unmutedAux1);
3289  SplitAudioChannelSet2(AudioChannelSet2(aux2InputMuteBits), mutedAux2, unmutedAux2);
3290  oss << "Main Output Muted/Disabled Channels: " << mutedMainOut << endl // bits[0:15]
3291  << "Main Output Unmuted/Enabled Channels: " << unmutedMainOut << endl;
3292  oss << "Main Input Muted/Disabled Channels: " << mutedMain << endl // bits[16:17]
3293  << "Main Input Unmuted/Enabled Channels: " << unmutedMain << endl;
3294  oss << "Aux Input 1 Muted/Disabled Channels: " << mutedAux1 << endl // bits[18:19]
3295  << "Aux Input 1 Unmuted/Enabled Channels: " << unmutedAux1 << endl;
3296  oss << "Aux Input 2 Muted/Disabled Channels: " << mutedAux2 << endl // bits[20-21]
3297  << "Aux Input 2 Unmuted/Enabled Channels: " << unmutedAux2;
3298  return oss.str();
3299  }
3300  } mAudMxrMutesDecoder;
3301 
3302  struct DecodeAudioMixerLevelsReg : public Decoder
3303  { // kRegAudioMixerAux1InputLevels, kRegAudioMixerAux2InputLevels,
3304  // kRegAudioMixerMainInputLevelsPair0 thru kRegAudioMixerMainInputLevelsPair7,
3305  // kRegAudioMixerMixedChannelOutputLevels
3306  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3307  { (void) inDeviceID;
3308  static const string sLabels[] = { "Aux Input 1", "Aux Input 2", "Main Input Audio Channels 1|2", "Main Input Audio Channels 3|4",
3309  "Main Input Audio Channels 5|6", "Main Input Audio Channels 7|8", "Main Input Audio Channels 9|10",
3310  "Main Input Audio Channels 11|12", "Main Input Audio Channels 13|14", "Main Input Audio Channels 15|16",
3311  "Main Output Audio Channels 1|2", "Main Output Audio Channels 3|4", "Main Output Audio Channels 5|6",
3312  "Main Output Audio Channels 7|8", "Main Output Audio Channels 9|10", "Main Output Audio Channels 11|12",
3313  "Main Output Audio Channels 13|14", "Main Output Audio Channels 15|16"};
3314  NTV2_ASSERT(inRegNum >= kRegAudioMixerAux1InputLevels);
3315  const uint32_t labelOffset(inRegNum - kRegAudioMixerAux1InputLevels);
3316  NTV2_ASSERT(labelOffset < 18);
3317  const string & label(sLabels[labelOffset]);
3318  const uint16_t leftLevel ((inRegValue & kRegMaskAudioMixerInputLeftLevel) >> kRegShiftAudioMixerInputLeftLevel);
3319  const uint16_t rightLevel ((inRegValue & kRegMaskAudioMixerInputRightLevel) >> kRegShiftAudioMixerInputRightLevel);
3320  ostringstream oss;
3321  oss << label << " Left Level:" << xHEX0N(leftLevel, 4) << " (" << DEC(leftLevel) << ")" << endl // bits[0:15]
3322  << label << " Right Level:" << xHEX0N(rightLevel,4) << " (" << DEC(rightLevel) << ")"; // bits[16:31]
3323  return oss.str();
3324  }
3325  } mAudMxrLevelDecoder;
3326 
3327  struct DecodeAncExtControlReg : public Decoder
3328  {
3329  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3330  {
3331  (void) inRegNum;
3332  (void) inDeviceID;
3333  ostringstream oss;
3334  static const string SyncStrs [] = { "field", "frame", "immediate", "unknown" };
3335  oss << "HANC Y enable: " << YesNo(inRegValue & BIT( 0)) << endl
3336  << "VANC Y enable: " << YesNo(inRegValue & BIT( 4)) << endl
3337  << "HANC C enable: " << YesNo(inRegValue & BIT( 8)) << endl
3338  << "VANC C enable: " << YesNo(inRegValue & BIT(12)) << endl
3339  << "Progressive video: " << YesNo(inRegValue & BIT(16)) << endl
3340  << "Synchronize: " << SyncStrs [(inRegValue & (BIT(24) | BIT(25))) >> 24] << endl
3341  << "Memory writes: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3342  << "SD Y+C Demux: " << EnabDisab(inRegValue & BIT(30)) << endl
3343  << "Metadata from: " << (inRegValue & BIT(31) ? "LSBs" : "MSBs");
3344  return oss.str();
3345  }
3346  } mDecodeAncExtControlReg;
3347 
3348  struct DecodeAuxExtControlReg : public Decoder
3349  {
3350  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3351  {
3352  (void) inRegNum;
3353  (void) inDeviceID;
3354  ostringstream oss;
3355  static const string SyncStrs [] = { "field", "frame", "immediate", "unknown" };
3356  oss << "Progressive video: " << YesNo(inRegValue & BIT(16)) << endl
3357  << "Synchronize: " << SyncStrs [(inRegValue & (BIT(24) | BIT(25))) >> 24] << endl
3358  << "Memory writes: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3359  << "Filter inclusion: " << EnabDisab(inRegValue & BIT(29));
3360  return oss.str();
3361  }
3362  } mDecodeAuxExtControlReg;
3363 
3364  // Also used for HDMI Aux regs: regAuxExtFieldVBLStartLine, regAuxExtFID
3365  struct DecodeAncExtFieldLinesReg : public Decoder
3366  {
3367  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3368  {
3369  (void) inDeviceID;
3370  ostringstream oss;
3371  const uint32_t which (inRegNum & 0x1F);
3372  const uint32_t valueLow (inRegValue & 0xFFF);
3373  const uint32_t valueHigh ((inRegValue >> 16) & 0xFFF);
3374  switch (which)
3375  {
3376  case 5: oss << "F1 cutoff line: " << valueLow << endl // regAncExtFieldCutoffLine
3377  << "F2 cutoff line: " << valueHigh;
3378  break;
3379  case 9: oss << "F1 VBL start line: " << valueLow << endl // regAncExtFieldVBLStartLine
3380  << "F2 VBL start line: " << valueHigh;
3381  break;
3382  case 11: oss << "Field ID high on line: " << valueLow << endl // regAncExtFID
3383  << "Field ID low on line: " << valueHigh;
3384  break;
3385  case 17: oss << "F1 analog start line: " << valueLow << endl // regAncExtAnalogStartLine
3386  << "F2 analog start line: " << valueHigh;
3387  break;
3388  default:
3389  oss << "Invalid register type";
3390  break;
3391  }
3392  return oss.str();
3393  }
3394  } mDecodeAncExtFieldLines;
3395 
3396  // Also used for HDMI Aux regs: regAuxExtTotalStatus, regAuxExtField1Status, regAuxExtField2Status
3397  struct DecodeAncExtStatusReg : public Decoder
3398  {
3399  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3400  {
3401  (void) inDeviceID;
3402  ostringstream oss;
3403  const uint32_t which (inRegNum & 0x1F);
3404  const uint32_t byteTotal (inRegValue & 0xFFFFFF);
3405  const bool overrun ((inRegValue & BIT(28)) ? true : false);
3406  switch (which)
3407  {
3408  case 6: oss << "Total bytes: "; break;
3409  case 7: oss << "Total F1 bytes: "; break;
3410  case 8: oss << "Total F2 bytes: "; break;
3411  default: oss << "Invalid register type"; break;
3412  }
3413  oss << DEC(byteTotal) << endl
3414  << "Overrun: " << YesNo(overrun);
3415  return oss.str();
3416  }
3417  } mDecodeAncExtStatus;
3418 
3419  // Also used for HDMI Aux Packet filtering
3420  struct DecodeAncExtIgnoreDIDReg : public Decoder
3421  {
3422  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3423  {
3424  (void) inRegNum;
3425  (void) inDeviceID;
3426  ostringstream oss;
3427  oss << "Ignoring DIDs " << HEX0N((inRegValue >> 0) & 0xFF, 2)
3428  << ", " << HEX0N((inRegValue >> 8) & 0xFF, 2)
3429  << ", " << HEX0N((inRegValue >> 16) & 0xFF, 2)
3430  << ", " << HEX0N((inRegValue >> 24) & 0xFF, 2);
3431  return oss.str();
3432  }
3433  } mDecodeAncExtIgnoreDIDs;
3434 
3435  struct DecodeAncExtAnalogFilterReg : public Decoder
3436  {
3437  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3438  {
3439  (void) inRegValue;
3440  (void) inDeviceID;
3441  ostringstream oss;
3442  uint32_t which (inRegNum & 0x1F);
3443  oss << "Each 1 bit specifies capturing ";
3444  switch (which)
3445  {
3446  case 18: oss << "F1 Y"; break;
3447  case 19: oss << "F2 Y"; break;
3448  case 20: oss << "F1 C"; break;
3449  case 21: oss << "F2 C"; break;
3450  default: return "Invalid register type";
3451  }
3452  oss << " line as analog, else digital";
3453  return oss.str();
3454  }
3455  } mDecodeAncExtAnalogFilter;
3456 
3457  struct DecodeAncInsValuePairReg : public Decoder
3458  {
3459  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3460  {
3461  (void) inDeviceID;
3462  ostringstream oss;
3463  const uint32_t which (inRegNum & 0x1F);
3464  const uint32_t valueLow (inRegValue & 0xFFFF);
3465  const uint32_t valueHigh ((inRegValue >> 16) & 0xFFFF);
3466 
3467  switch (which)
3468  {
3469  case 0: oss << "F1 byte count low: " << valueLow << endl
3470  << "F2 byte count low: " << valueHigh;
3471  break;
3472  case 4: oss << "HANC pixel delay: " << (valueLow & 0x3FF) << endl
3473  << "VANC pixel delay: " << (valueHigh & 0x7FF);
3474  break;
3475  case 5: oss << "F1 first active line: " << (valueLow & 0x7FF) << endl
3476  << "F2 first active line: " << (valueHigh & 0x7FF);
3477  break;
3478  case 6: oss << "Active line length: " << (valueLow & 0x7FF) << endl
3479  << "Total line length: " << (valueHigh & 0xFFF);
3480  break;
3481  case 8: oss << "Field ID high on line: " << (valueLow & 0x7FF) << endl
3482  << "Field ID low on line: " << (valueHigh & 0x7FF);
3483  break;
3484  case 11: oss << "F1 chroma blnk start line: " << (valueLow & 0x7FF) << endl
3485  << "F2 chroma blnk start line: " << (valueHigh & 0x7FF);
3486  break;
3487  case 14: oss << "F1 byte count high: " << valueLow << endl
3488  << "F2 byte count high: " << valueHigh;
3489  break;
3490  default: return "Invalid register type";
3491  }
3492  return oss.str();
3493  }
3494  } mDecodeAncInsValuePairReg;
3495 
3496  struct DecodeAncInsControlReg : public Decoder
3497  {
3498  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3499  {
3500  (void) inRegNum;
3501  (void) inDeviceID;
3502  ostringstream oss;
3503  oss << "HANC Y enable: " << YesNo(inRegValue & BIT( 0)) << endl
3504  << "VANC Y enable: " << YesNo(inRegValue & BIT( 4)) << endl
3505  << "HANC C enable: " << YesNo(inRegValue & BIT( 8)) << endl
3506  << "VANC C enable: " << YesNo(inRegValue & BIT(12)) << endl
3507  << "Payload Y insert: " << YesNo(inRegValue & BIT(16)) << endl
3508  << "Payload C insert: " << YesNo(inRegValue & BIT(17)) << endl
3509  << "Payload F1 insert: " << YesNo(inRegValue & BIT(20)) << endl
3510  << "Payload F2 insert: " << YesNo(inRegValue & BIT(21)) << endl
3511  << "Progressive video: " << YesNo(inRegValue & BIT(24)) << endl
3512  << "Memory reads: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3513  << "SD Packet Split: " << EnabDisab(inRegValue & BIT(31));
3514  return oss.str();
3515  }
3516  } mDecodeAncInsControlReg;
3517 
3518  struct DecodeAncInsChromaBlankReg : public Decoder
3519  {
3520  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3521  {
3522  (void) inRegValue;
3523  (void) inDeviceID;
3524  ostringstream oss;
3525  uint32_t which (inRegNum & 0x1F);
3526 
3527  oss << "Each 1 bit specifies if chroma in ";
3528  switch (which)
3529  {
3530  case 12: oss << "F1"; break;
3531  case 13: oss << "F2"; break;
3532  default: return "Invalid register type";
3533  }
3534  oss << " should be blanked or passed thru";
3535  return oss.str();
3536  }
3537  } mDecodeAncInsChromaBlankReg;
3538 
3539  struct DecodeXptGroupReg : public Decoder
3540  { // Every byte in the reg value is an NTV2OutputXptID
3541  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3542  { (void) inRegNum;
3543  static unsigned sShifts[4] = {0, 8, 16, 24};
3544  NTV2StringList strs;
3545  for (unsigned ndx(0); ndx < 4; ndx++)
3546  {
3547  const NTV2InputCrosspointID inputXpt (CNTV2RegisterExpert::GetInputCrosspointID (inRegNum, ndx));
3548  const NTV2OutputCrosspointID outputXpt (NTV2OutputCrosspointID((inRegValue >> sShifts[ndx]) & 0xFF));
3549  if (NTV2_IS_VALID_InputCrosspointID(inputXpt))
3550  {
3551  if (outputXpt != NTV2_XptBlack)
3552  {
3553  NTV2WidgetID wgtID(NTV2_WIDGET_INVALID);
3554  ostringstream oss;
3555  oss << ::NTV2InputCrosspointIDToString(inputXpt, false);
3556  /* Don't bother with inputXpt check, since wgtID guaranteed valid for every inputXpt seen here:
3557  if (!CNTV2SignalRouter::GetWidgetForInput (inputXpt, wgtID, inDeviceID))
3558  oss << " (unimpl)";
3559  */
3560  oss << " <== " << ::NTV2OutputCrosspointIDToString(outputXpt, false);
3561  if (!CNTV2SignalRouter::GetWidgetForOutput (outputXpt, wgtID, inDeviceID))
3562  oss << " (unimpl)";
3563  strs.push_back(oss.str());
3564  }
3565  }
3566  }
3567  return aja::join(strs, "\n");
3568  }
3569  } mDecodeXptGroupReg;
3570 
3571  struct DecodeXptValidReg : public Decoder
3572  {
3573  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3574  {
3575  NTV2_ASSERT(inRegNum >= uint32_t(kRegFirstValidXptROMRegister));
3576  NTV2_ASSERT(inRegNum < uint32_t(kRegInvalidValidXptROMRegister));
3577  ostringstream oss;
3578  NTV2InputXptID inputXpt;
3579  NTV2OutputXptIDSet outputXpts;
3580  if (CNTV2SignalRouter::GetRouteROMInfoFromReg (inRegNum, inRegValue, inputXpt, outputXpts)
3581  && NTV2_IS_VALID_InputCrosspointID(inputXpt))
3582  {
3583  NTV2StringList outputXptNames;
3584  for (NTV2OutputXptIDSetConstIter it(outputXpts.begin()); it != outputXpts.end(); ++it)
3585  {
3586  const NTV2OutputXptID outputXpt(*it);
3587  const string name(::NTV2OutputCrosspointIDToString(outputXpt,true));
3588  ostringstream ss;
3589  if (name.empty())
3590  ss << xHEX0N(outputXpt,2) << "(" << DEC(outputXpt) << ")";
3591  else
3592  ss << "'" << name << "'";
3593  outputXptNames.push_back(ss.str());
3594  }
3595  if (!outputXptNames.empty())
3596  oss << "Valid Xpts: " << outputXptNames;
3597  return oss.str();
3598  }
3599  else
3600  return Decoder::operator()(inRegNum, inRegValue, inDeviceID);
3601  }
3602  } mDecodeXptValidReg;
3603 
3604  struct DecodeNTV4FSReg : public Decoder
3605  {
3606  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3607  { (void) inDeviceID;
3608  static const string sPixClkSelects[] = {"27", "74.1758", "74.25", "148.3516", "148.5", "inv5", "inv6", "inv7"};
3609  static const string sSyncs[] = {"Sync to Frame", "Sync to Field", "Immediate", "Sync to External"};
3610  const ULWord ntv4RegNum ((inRegNum - kNTV4FrameStoreFirstRegNum) % kNumNTV4FrameStoreRegisters);
3611  ostringstream oss;
3612  switch (NTV4FrameStoreRegs(ntv4RegNum))
3613  {
3614  case regNTV4FS_RasterControl:
3615  { const ULWord disabled (inRegValue & BIT(1));
3616  const ULWord sync ((inRegValue & (BIT(20)|BIT(21))) >> 20);
3617  const ULWord pixClkSel((inRegValue & (BIT(16)|BIT(17)|BIT(18))) >> 16);
3618  const ULWord pixFmt((inRegValue & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12))) >> 8);
3619  if (!disabled)
3620  oss << "Enabled: " << YesNo(!disabled) << endl
3621  << "Mode: " << ((inRegValue & BIT( 0)) ? "Capture" : "Display") << endl
3622  << "DRT_DISP: " << OnOff(inRegValue & BIT( 2)) << endl
3623  << "Fill Bit: " << DEC((inRegValue & BIT( 3)) ? 1 : 0) << endl
3624  << "Dither: " << EnabDisab(inRegValue & BIT( 4)) << endl
3625  << "RGB8 Convert: " << ((inRegValue & BIT( 5)) ? "Use '00'" : "Copy MSBs") << endl
3626  << "Progressive: " << YesNo(inRegValue & BIT( 6)) << endl
3627  << "Pixel Format: " << DEC(pixFmt) << " " << ::NTV2FrameBufferFormatToString(NTV2PixelFormat(pixFmt)) << endl
3628  << "Pix Clk Sel: " << sPixClkSelects[pixClkSel] << " MHz" << endl
3629  << "Sync: " << sSyncs[sync];
3630  else
3631  oss << "Enabled: " << YesNo(!disabled);
3632  break;
3633  }
3634  case regNTV4FS_Status:
3635  { const ULWord lineCnt ((inRegValue & (0xFFFF0000)) >> 16);
3636  oss << "Field ID: " << OddEven(inRegValue & BIT( 0)) << endl
3637  << "Line Count: " << DEC(lineCnt);
3638  break;
3639  }
3640  case regNTV4FS_LineLengthPitch:
3641  { const int32_t xferByteCnt((inRegValue & 0xFFFF0000) >> 16), linePitch(inRegValue & 0x0000FFFF);
3642  oss << "Line Pitch: " << linePitch << (linePitch < 0 ? " (flipped)" : "") << endl
3643  << "Xfer Byte Count: " << xferByteCnt << " [bytes/line]" << (linePitch < 0 ? " (flipped)" : "");
3644  break;
3645  }
3646  case regNTV4FS_ROIVHSize:
3647  { const ULWord ROIVSize((inRegValue & (0x0FFF0000)) >> 16), ROIHSize(inRegValue & 0x00000FFF);
3648  oss << "ROI Horz Size: " << DEC(ROIHSize) << " [pixels]" << endl
3649  << "ROI Vert Size: " << DEC(ROIVSize) << " [lines]";
3650  break;
3651  }
3652  case regNTV4FS_ROIF1VHOffsets:
3653  case regNTV4FS_ROIF2VHOffsets:
3654  { const ULWord ROIVOff((inRegValue & (0x0FFF0000)) >> 16), ROIHOff(inRegValue & 0x00000FFF);
3655  const string fld(ntv4RegNum == regNTV4FS_ROIF1VHOffsets ? "F1" : "F2");
3656  oss << "ROI " << fld << " Horz Offset: " << DEC(ROIHOff) << endl
3657  << "ROI " << fld << " Vert Offset: " << DEC(ROIVOff);
3658  break;
3659  }
3660  case regNTV4FS_DisplayHorzPixelsPerLine:
3661  { const ULWord tot((inRegValue & (0x0FFF0000)) >> 16), act(inRegValue & 0x00000FFF);
3662  oss << "Disp Horz Active: " << DEC(act) << endl
3663  << "Disp Horz Total: " << DEC(tot);
3664  break;
3665  }
3666  case regNTV4FS_DisplayFID:
3667  { const ULWord lo((inRegValue & (0x07FF0000)) >> 16), hi(inRegValue & 0x000007FF);
3668  oss << "Disp FID Lo: " << DEC(lo) << endl
3669  << "Disp FID Hi: " << DEC(hi);
3670  break;
3671  }
3672  case regNTV4FS_F1ActiveLines:
3673  case regNTV4FS_F2ActiveLines:
3674  { const ULWord actEnd((inRegValue & (0x07FF0000)) >> 16), actStart(inRegValue & 0x000007FF);
3675  const string fld(ntv4RegNum == regNTV4FS_F1ActiveLines ? "F1" : "F2");
3676  oss << "Disp " << fld << " Active Start: " << DEC(actStart) << endl
3677  << "Disp " << fld << " Active End: " << DEC(actEnd);
3678  break;
3679  }
3680  case regNTV4FS_RasterPixelSkip:
3681  oss << "Unpacker Horz Offset: " << DEC(inRegValue & 0x0000FFFF);
3682  break;
3683  case regNTV4FS_RasterVideoFill_YCb_GB:
3684  case regNTV4FS_RasterVideoFill_Cr_AR:
3685  { const ULWord hi((inRegValue & (0xFFFF0000)) >> 16), lo(inRegValue & 0x0000FFFF);
3686  const string YGorA(ntv4RegNum == regNTV4FS_RasterVideoFill_YCb_GB ? "Y|G" : "A");
3687  const string CbBorCrR(ntv4RegNum == regNTV4FS_RasterVideoFill_YCb_GB ? "Cb|B" : "Cr|R");
3688  oss << "Disp Fill " << CbBorCrR << ": " << DEC(lo) << " " << xHEX0N(lo,4) << endl
3689  << "Disp Fill " << YGorA << ": " << DEC(hi) << " " << xHEX0N(hi,4);
3690  break;
3691  }
3692  case regNTV4FS_RasterROIFillAlpha:
3693  { const ULWord lo(inRegValue & 0x0000FFFF);
3694  oss << "ROI Fill Alpha: " << DEC(lo) << " " << xHEX0N(lo,4);
3695  break;
3696  }
3697  case regNTV4FS_RasterOutputTimingPreset:
3698  oss << "Output Timing Frame Pulse Preset: " << DEC(inRegValue & 0x00FFFFFF) << " "
3699  << xHEX0N(inRegValue & 0x00FFFFFF,6);
3700  break;
3701  case regNTV4FS_RasterOffsetBlue:
3702  case regNTV4FS_RasterOffsetRed:
3703  case regNTV4FS_RasterOffsetAlpha:
3704  { const int32_t lo (inRegValue & 0x00001FFF);
3705  oss << "Output Video Offset: " << lo << " " << xHEX0N(lo,6);
3706  break;
3707  }
3708  default:
3709  return Decoder::operator()(inRegNum, inRegValue, inDeviceID);
3710  }
3711  return oss.str();
3712  }
3713  } mDecodeNTV4FSReg;
3714 
3715  struct DecodeHDMIOutputControl : public Decoder
3716  {
3717  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3718  {
3719  (void) inRegNum;
3720  ostringstream oss;
3721  static const string sHDMIStdV1[] = { "1080i", "720p", "480i", "576i", "1080p", "SXGA", "", "", "", "", "", "", "", "", "", "" };
3722  static const string sHDMIStdV2V3[] = { "1080i", "720p", "480i", "576i", "1080p", "1556i", "2Kx1080p", "2Kx1080i", "UHD", "4K", "", "", "", "", "", "" };
3723  static const string sVidRates[] = { "", "60.00", "59.94", "30.00", "29.97", "25.00", "24.00", "23.98", "50.00", "48.00", "47.95", "", "", "", "", "" };
3724  static const string sSrcSampling[] = { "YC422", "RGB", "YC420", "Unknown/invalid" };
3725  static const string sBitDepth[] = { "8", "10", "12", "Unknown/invalid" };
3726  const ULWord hdmiVers (::NTV2DeviceGetHDMIVersion(inDeviceID));
3727  const ULWord rawVideoStd (inRegValue & kRegMaskHDMIOutV2VideoStd);
3728  const string hdmiVidStdStr (hdmiVers > 1 ? sHDMIStdV2V3[rawVideoStd] : (hdmiVers == 1 ? sHDMIStdV1[rawVideoStd] : ""));
3729  const string vidStdStr (::NTV2StandardToString (NTV2Standard(rawVideoStd), true));
3730  const uint32_t srcSampling ((inRegValue & kRegMaskHDMISampling) >> kRegShiftHDMISampling);
3731  const uint32_t srcBPC ((inRegValue & (BIT(16)|BIT(17))) >> 16);
3732  const uint32_t txBitDepth ((inRegValue & (BIT(20)|BIT(21))) >> 20);
3733  oss << "Video Standard: " << hdmiVidStdStr;
3734  if (hdmiVidStdStr != vidStdStr)
3735  oss << " (" << vidStdStr << ")";
3736  oss << endl
3737  << "Color Mode: " << ((inRegValue & BIT( 8)) ? "RGB" : "YCbCr") << endl
3738  << "Video Rate: " << sVidRates[(inRegValue & kLHIRegMaskHDMIOutFPS) >> kLHIRegShiftHDMIOutFPS] << endl
3739  << "Scan Mode: " << ((inRegValue & BIT(13)) ? "Progressive" : "Interlaced") << endl
3740  << "Bit Depth: " << ((inRegValue & BIT(14)) ? "10-bit" : "8-bit") << endl
3741  << "Output Color Sampling: " << ((inRegValue & BIT(15)) ? "4:4:4" : "4:2:2") << endl
3742  << "Output Bit Depth: " << sBitDepth[txBitDepth] << endl
3743  << "Src Color Sampling: " << sSrcSampling[srcSampling] << endl
3744  << "Src Bits Per Component: " << sBitDepth[srcBPC] << endl
3745  << "Output Range: " << ((inRegValue & BIT(28)) ? "Full" : "SMPTE") << endl
3746  << "Audio Channels: " << ((inRegValue & BIT(29)) ? "8" : "2") << endl
3747  << "Output: " << ((inRegValue & BIT(30)) ? "DVI" : "HDMI");
3748  if (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID) && ::NTV2DeviceGetNumHDMIVideoOutputs(inDeviceID))
3749  oss << endl
3750  << "Audio Loopback: " << OnOff(inRegValue & BIT(31));
3751  return oss.str();
3752  }
3753  } mDecodeHDMIOutputControl;
3754 
3755  struct DecodeHDMIInputStatus : public Decoder
3756  {
3757  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3758  {
3759  (void) inRegNum;
3760  ostringstream oss;
3761  const ULWord hdmiVers(::NTV2DeviceGetHDMIVersion (inDeviceID));
3762  const uint32_t vidStd (hdmiVers >= 2 ? (inRegValue & kRegMaskHDMIInV2VideoStd) >> kRegShiftHDMIInV2VideoStd : (inRegValue & kRegMaskInputStatusStd) >> kRegShiftInputStatusStd);
3763  const uint32_t rate ((inRegValue & kRegMaskInputStatusFPS) >> kRegShiftInputStatusFPS);
3764  static const string sStds[32] = {"1080i", "720p", "480i", "576i", "1080p", "SXGA", "2K1080p", "2K1080i", "3840p", "4096p"};
3765  static const string sRates[32] = {"invalid", "60.00", "59.94", "30.00", "29.97", "25.00", "24.00", "23.98", "50.00", "48.00", "47.95" };
3766  oss << "HDMI Input: " << (inRegValue & BIT(0) ? "Locked" : "Unlocked") << endl
3767  << "HDMI Input: " << (inRegValue & BIT(1) ? "Stable" : "Unstable") << endl
3768  << "Color Mode: " << (inRegValue & BIT(2) ? "RGB" : "YCbCr") << endl
3769  << "Bitdepth: " << (inRegValue & BIT(3) ? "10-bit" : "8-bit") << endl
3770  << "Audio Channels: " << (inRegValue & BIT(12) ? 2 : 8) << endl
3771  << "Scan Mode: " << (inRegValue & BIT(13) ? "Progressive" : "Interlaced") << endl
3772  << "Standard: " << (inRegValue & BIT(14) ? "SD" : "HD") << endl
3773  << "Video Standard: " << sStds[vidStd] << endl
3774  << "Protocol: " << (inRegValue & BIT(27) ? "DVI" : "HDMI") << endl
3775  << "Video Rate : " << (rate < 11 ? sRates[rate] : string("invalid"));
3776  return oss.str();
3777  }
3778  } mDecodeHDMIInputStatus;
3779 
3780  struct DecodeHDMIInputControl : public Decoder
3781  {
3782  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3783  {
3784  (void) inRegNum; (void) inDeviceID;
3785  ostringstream oss;
3786  const UWord chanPair ((inRegValue & (BIT(2) | BIT(3))) >> 2);
3787  const UWord txSrcSel ((inRegValue & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) >> 20);
3788  const UWord txCh12Sel ((inRegValue & (BIT(29)|BIT(30))) >> 29);
3789  static const NTV2AudioChannelPair pairs[] = {NTV2_AudioChannel1_2, NTV2_AudioChannel3_4, NTV2_AudioChannel5_6, NTV2_AudioChannel7_8};
3790  oss << "HDMI In EDID Write-Enable: " << EnabDisab(inRegValue & BIT(0)) << endl
3791  << "HDMI Force Output Params: " << SetNotset(inRegValue & BIT(1)) << endl
3792  << "HDMI In Audio Chan Select: " << ::NTV2AudioChannelPairToString(pairs[chanPair], true) << endl
3793  << "hdmi_rx_8ch_src_off: " << YesNo(inRegValue & BIT(4)) << endl
3794  << "Swap HDMI In Audio Ch. 3/4: " << YesNo(inRegValue & BIT(5)) << endl
3795  << "Swap HDMI Out Audio Ch. 3/4: " << YesNo(inRegValue & BIT(6)) << endl
3796  << "HDMI Prefer 420: " << SetNotset(inRegValue & BIT(7)) << endl
3797  << "hdmi_rx_spdif_err: " << SetNotset(inRegValue & BIT(8)) << endl
3798  << "hdmi_rx_afifo_under: " << SetNotset(inRegValue & BIT(9)) << endl
3799  << "hdmi_rx_afifo_empty: " << SetNotset(inRegValue & BIT(10)) << endl
3800  << "H polarity: " << (inRegValue & BIT(16) ? "Inverted" : "Normal") << endl
3801  << "V polarity: " << (inRegValue & BIT(17) ? "Inverted" : "Normal") << endl
3802  << "F polarity: " << (inRegValue & BIT(18) ? "Inverted" : "Normal") << endl
3803  << "DE polarity: " << (inRegValue & BIT(19) ? "Inverted" : "Normal") << endl
3804  << "Tx Src Sel: " << DEC(txSrcSel) << " (" << xHEX0N(txSrcSel,4) << ")" << endl
3805  << "Tx Center Cut: " << SetNotset(inRegValue & BIT(24)) << endl
3806  << "Tx 12 bit: " << SetNotset(inRegValue & BIT(26)) << endl
3807  << "RGB Input Gamut: " << (inRegValue & BIT(28) ? "Full Range" : "Narrow Range (SMPTE)") << endl
3808  << "Tx_ch12_sel: " << DEC(txCh12Sel) << " (" << xHEX0N(txCh12Sel,4) << ")" << endl
3809  << "Input AVI Gamut: " << (inRegValue & BIT(31) ? "Full Range" : "Narrow Range (SMPTE)") << endl
3810  << "EDID: " << SetNotset(inRegValue & BIT(31));
3811  return oss.str();
3812  }
3813  } mDecodeHDMIInputControl;
3814 
3815  struct DecodeHDMIOutputStatus : public Decoder
3816  {
3817  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3818  { (void) inRegNum; (void) inDeviceID;
3819  const NTV2HDMIOutputStatus stat (inRegValue);
3820  ostringstream oss;
3821  stat.Print(oss);
3822  return oss.str();
3823  }
3824  } mDecodeHDMIOutputStatus;
3825 
3826  struct DecodeHDMIOutHDRPrimary : public Decoder
3827  {
3828  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3829  {
3830  (void) inRegNum;
3831  ostringstream oss;
3832  if (::NTV2DeviceCanDoHDMIHDROut (inDeviceID))
3833  switch (inRegNum)
3834  {
3835  case kRegHDMIHDRGreenPrimary:
3836  case kRegHDMIHDRBluePrimary:
3837  case kRegHDMIHDRRedPrimary:
3838  case kRegHDMIHDRWhitePoint:
3839  case kVRegHDMIOutHDRGreenPrimary1:
3840  case kVRegHDMIOutHDRBluePrimary1:
3841  case kVRegHDMIOutHDRRedPrimary1:
3842  case kVRegHDMIOutHDRWhitePoint1:
3843  case kVRegHDMIOutHDRGreenPrimary2:
3844  case kVRegHDMIOutHDRBluePrimary2:
3845  case kVRegHDMIOutHDRRedPrimary2:
3846  case kVRegHDMIOutHDRWhitePoint2:
3847  case kVRegHDMIOutHDRGreenPrimary3:
3848  case kVRegHDMIOutHDRBluePrimary3:
3849  case kVRegHDMIOutHDRRedPrimary3:
3850  case kVRegHDMIOutHDRWhitePoint3:
3851  case kVRegHDMIOutHDRGreenPrimary4:
3852  case kVRegHDMIOutHDRBluePrimary4:
3853  case kVRegHDMIOutHDRRedPrimary4:
3854  case kVRegHDMIOutHDRWhitePoint4:
3855  { // Asserts to validate this one code block will handle all cases:
3856  NTV2_ASSERT (kRegMaskHDMIHDRGreenPrimaryX == kRegMaskHDMIHDRBluePrimaryX && kRegMaskHDMIHDRBluePrimaryX == kRegMaskHDMIHDRRedPrimaryX);
3857  NTV2_ASSERT (kRegMaskHDMIHDRGreenPrimaryY == kRegMaskHDMIHDRBluePrimaryY && kRegMaskHDMIHDRBluePrimaryY == kRegMaskHDMIHDRRedPrimaryY);
3858  NTV2_ASSERT (kRegMaskHDMIHDRRedPrimaryX == kRegMaskHDMIHDRWhitePointX && kRegMaskHDMIHDRRedPrimaryY == kRegMaskHDMIHDRWhitePointY);
3859  NTV2_ASSERT (kRegShiftHDMIHDRGreenPrimaryX == kRegShiftHDMIHDRBluePrimaryX && kRegShiftHDMIHDRBluePrimaryX == kRegShiftHDMIHDRRedPrimaryX);
3860  NTV2_ASSERT (kRegShiftHDMIHDRGreenPrimaryY == kRegShiftHDMIHDRBluePrimaryY && kRegShiftHDMIHDRBluePrimaryY == kRegShiftHDMIHDRRedPrimaryY);
3861  NTV2_ASSERT (kRegShiftHDMIHDRRedPrimaryX == kRegShiftHDMIHDRWhitePointX && kRegShiftHDMIHDRRedPrimaryY == kRegShiftHDMIHDRWhitePointY);
3862  const uint16_t xPrimary ((inRegValue & kRegMaskHDMIHDRRedPrimaryX) >> kRegShiftHDMIHDRRedPrimaryX);
3863  const uint16_t yPrimary ((inRegValue & kRegMaskHDMIHDRRedPrimaryY) >> kRegShiftHDMIHDRRedPrimaryY);
3864  const double xFloat (double(xPrimary) * 0.00002);
3865  const double yFloat (double(yPrimary) * 0.00002);
3866  if (NTV2_IS_VALID_HDR_PRIMARY (xPrimary))
3867  oss << "X: " << fDEC(xFloat,7,5) << endl;
3868  else
3869  oss << "X: " << HEX0N(xPrimary, 4) << "(invalid)" << endl;
3870  if (NTV2_IS_VALID_HDR_PRIMARY (yPrimary))
3871  oss << "Y: " << fDEC(yFloat,7,5);
3872  else
3873  oss << "Y: " << HEX0N(yPrimary, 4) << "(invalid)";
3874  break;
3875  }
3876  case kRegHDMIHDRMasteringLuminence:
3877  case kVRegHDMIOutHDRMasterLuminance1:
3878  case kVRegHDMIOutHDRMasterLuminance2:
3879  case kVRegHDMIOutHDRMasterLuminance3:
3880  case kVRegHDMIOutHDRMasterLuminance4:
3881  {
3882  const uint16_t minValue ((inRegValue & kRegMaskHDMIHDRMinMasteringLuminance) >> kRegShiftHDMIHDRMinMasteringLuminance);
3883  const uint16_t maxValue ((inRegValue & kRegMaskHDMIHDRMaxMasteringLuminance) >> kRegShiftHDMIHDRMaxMasteringLuminance);
3884  const double minFloat (double(minValue) * 0.00001);
3885  const double maxFloat (maxValue);
3886  oss << "Min: " << fDEC(minFloat,7,5) << endl
3887  << "Max: " << fDEC(maxFloat,7,5);
3888  break;
3889  }
3890  case kRegHDMIHDRLightLevel:
3891  case kVRegHDMIOutHDRLightLevel1:
3892  case kVRegHDMIOutHDRLightLevel2:
3893  case kVRegHDMIOutHDRLightLevel3:
3894  case kVRegHDMIOutHDRLightLevel4:
3895  {
3896  const uint16_t cntValue ((inRegValue & kRegMaskHDMIHDRMaxContentLightLevel) >> kRegShiftHDMIHDRMaxContentLightLevel);
3897  const uint16_t frmValue ((inRegValue & kRegMaskHDMIHDRMaxFrameAverageLightLevel) >> kRegShiftHDMIHDRMaxFrameAverageLightLevel);
3898  const double cntFloat (cntValue);
3899  const double frmFloat (frmValue);
3900  oss << "Max Content Light Level: " << fDEC(cntFloat,7,5) << endl
3901  << "Max Frame Light Level: " << fDEC(frmFloat,7,5);
3902  break;
3903  }
3904  default: NTV2_ASSERT(false);
3905  }
3906  return oss.str();
3907  }
3908  } mDecodeHDMIOutHDRPrimary;
3909 
3910  struct DecodeHDMIOutHDRControl : public Decoder
3911  {
3912  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3913  {
3914  (void) inRegNum;
3915  static const string sEOTFs[] = {"Trad Gamma SDR", "Trad Gamma HDR", "SMPTE ST 2084", "HLG"};
3916  ostringstream oss;
3917  if (::NTV2DeviceCanDoHDMIHDROut (inDeviceID))
3918  {
3919  const uint16_t EOTFvalue ((inRegValue & kRegMaskElectroOpticalTransferFunction) >> kRegShiftElectroOpticalTransferFunction);
3920  const uint16_t staticMetaDataDescID ((inRegValue & kRegMaskHDRStaticMetadataDescriptorID) >> kRegShiftHDRStaticMetadataDescriptorID);
3921  oss << "HDMI Out Dolby Vision Enabled: " << YesNo(inRegValue & kRegMaskHDMIHDRDolbyVisionEnable) << endl
3922  << "HDMI HDR Out Enabled: " << YesNo(inRegValue & kRegMaskHDMIHDREnable) << endl
3923  << "Constant Luminance: " << YesNo(inRegValue & kRegMaskHDMIHDRNonContantLuminance) << endl
3924  << "EOTF: " << sEOTFs[(EOTFvalue < 3) ? EOTFvalue : 3] << endl
3925  << "Static MetaData Desc ID: " << HEX0N(staticMetaDataDescID, 2) << " (" << DEC(staticMetaDataDescID) << ")";
3926  }
3927  return oss.str();
3928  }
3929  } mDecodeHDMIOutHDRControl;
3930 
3931  struct DecodeHDMIOutMRControl : public Decoder
3932  {
3933  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3934  { (void) inRegNum; (void) inDeviceID;
3935  ostringstream oss;
3936  static const string sMRStandard[] = { "1080i", "720p", "480i", "576i", "1080p", "1556i", "2Kx1080p", "2Kx1080i", "UHD", "4K", "", "", "", "", "", "" };
3937  const ULWord rawVideoStd (inRegValue & kRegMaskMRStandard);
3938  const string hdmiVidStdStr (sMRStandard[rawVideoStd]);
3939  const string vidStdStr (::NTV2StandardToString (NTV2Standard(rawVideoStd), true));
3940  oss << "Video Standard: " << hdmiVidStdStr;
3941  if (hdmiVidStdStr != vidStdStr)
3942  oss << " (" << vidStdStr << ")";
3943  oss << endl
3944  << "Capture Mode: " << ((inRegValue & kRegMaskMREnable) ? "Enabled" : "Disabled");
3945  return oss.str();
3946  }
3947  } mDecodeHDMIOutMRControl;
3948 
3949  struct DecodeSDIOutputControl : public Decoder
3950  {
3951  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3952  {
3953  (void) inRegNum;
3954  (void) inDeviceID;
3955  ostringstream oss;
3956  const uint32_t vidStd (inRegValue & (BIT(0)|BIT(1)|BIT(2)));
3957  static const string sStds[32] = {"1080i", "720p", "480i", "576i", "1080p", "1556i", "6", "7"};
3958  oss << "Video Standard: " << sStds[vidStd] << endl
3959  << "2Kx1080 mode: " << (inRegValue & BIT(3) ? "2048x1080" : "1920x1080") << endl
3960  << "HBlank RGB Range: Black=" << (inRegValue & BIT(7) ? "0x40" : "0x04") << endl
3961  << "12G enable: " << YesNo(inRegValue & BIT(17)) << endl
3962  << "6G enable: " << YesNo(inRegValue & BIT(16)) << endl
3963  << "3G enable: " << YesNo(inRegValue & BIT(24)) << endl
3964  << "3G mode: " << (inRegValue & BIT(25) ? "b" : "a") << endl
3965  << "VPID insert enable: " << YesNo(inRegValue & BIT(26)) << endl
3966  << "VPID overwrite enable: " << YesNo(inRegValue & BIT(27)) << endl
3967  << "DS 1 audio source: " "AudSys";
3968  switch ((inRegValue & (BIT(28)|BIT(30))) >> 28)
3969  {
3970  case 0: oss << (inRegValue & BIT(18) ? 5 : 1); break;
3971  case 1: oss << (inRegValue & BIT(18) ? 7 : 3); break;
3972  case 4: oss << (inRegValue & BIT(18) ? 6 : 2); break;
3973  case 5: oss << (inRegValue & BIT(18) ? 8 : 4); break;
3974  }
3975  oss << endl << "DS 2 audio source: AudSys";
3976  switch ((inRegValue & (BIT(29)|BIT(31))) >> 29)
3977  {
3978  case 0: oss << (inRegValue & BIT(19) ? 5 : 1); break;
3979  case 1: oss << (inRegValue & BIT(19) ? 7 : 3); break;
3980  case 4: oss << (inRegValue & BIT(19) ? 6 : 2); break;
3981  case 5: oss << (inRegValue & BIT(19) ? 8 : 4); break;
3982  }
3983  return oss.str();
3984  }
3985  } mDecodeSDIOutputControl;
3986 
3987  struct DecodeSDIOutTimingCtrl : public Decoder
3988  {
3989  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3990  { (void)inRegNum; (void)inDeviceID;
3991  ostringstream oss;
3992  const uint32_t hMask(0x00001FFF), vMask(0x1FFF0000);
3993  const uint32_t hOffset(inRegValue & hMask), vOffset((inRegValue & vMask) >> 16);
3994  oss << "Horz Offset: " << xHEX0N(UWord(hOffset),4) << endl
3995  << "Vert Offset: " << xHEX0N(UWord(vOffset),4) << endl
3996  << "E-E Timing Override: " << EnabDisab(inRegValue & BIT(31));
3997  return oss.str();
3998  }
3999  } mDecodeSDIOutTimingCtrl;
4000 
4001  struct DecodeDMAControl : public Decoder
4002  {
4003  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4004  {
4005  (void) inRegNum;
4006  (void) inDeviceID;
4007  const uint16_t gen ((inRegValue & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) >> 20);
4008  const uint16_t lanes ((inRegValue & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) >> 16);
4009  const uint16_t fwRev ((inRegValue & 0x0000FF00) >> 8);
4010  ostringstream oss;
4011  for (uint16_t engine(0); engine < 4; engine++)
4012  oss << "DMA " << (engine+1) << " Int Active?: " << YesNo(inRegValue & BIT(27+engine)) << endl;
4013  oss << "Bus Error Int Active?: " << YesNo(inRegValue & BIT(31)) << endl;
4014  for (uint16_t engine(0); engine < 4; engine++)
4015  oss << "DMA " << (engine+1) << " Busy?: " << YesNo(inRegValue & BIT(27+engine)) << endl;
4016  oss << "Strap: " << ((inRegValue & BIT(7)) ? "Installed" : "Not Installed") << endl
4017  << "Firmware Rev: " << xHEX0N(fwRev, 2) << " (" << DEC(fwRev) << ")" << endl
4018  << "Gen: " << gen << ((gen > 0 && gen < 4) ? "" : " <invalid>") << endl
4019  << "Lanes: " << DEC(lanes) << ((lanes < 9) ? "" : " <invalid>");
4020  return oss.str();
4021  }
4022  } mDMAControlRegDecoder;
4023 
4024  struct DecodeDMAIntControl : public Decoder
4025  {
4026  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4027  {
4028  (void) inRegNum;
4029  (void) inDeviceID;
4030  ostringstream oss;
4031  for (uint16_t eng(0); eng < 4; eng++)
4032  oss << "DMA " << (eng+1) << " Enabled?: " << YesNo(inRegValue & BIT(eng)) << endl;
4033  oss << "Bus Error Enabled?: " << YesNo(inRegValue & BIT(4)) << endl;
4034  for (uint16_t eng(0); eng < 4; eng++)
4035  oss << "DMA " << (eng+1) << " Active?: " << YesNo(inRegValue & BIT(27+eng)) << endl;
4036  oss << "Bus Error: " << YesNo(inRegValue & BIT(31));
4037  return oss.str();
4038  }
4039  } mDMAIntControlRegDecoder;
4040 
4041  struct DecodeDMAXferRate : public Decoder
4042  {
4043  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4044  { (void) inRegNum; (void) inDeviceID;
4045  ostringstream oss;
4046  oss << DEC(inRegValue) << " [MB/sec] [kB/ms] [B/us]";
4047  return oss.str();
4048  }
4049  } mDMAXferRateRegDecoder;
4050 
4051  struct DecodeRP188InOutDBB : public Decoder
4052  {
4053  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4054  {
4055  (void) inRegNum;
4056  (void) inDeviceID;
4057  const bool isReceivingRP188 (inRegValue & BIT(16));
4058  const bool isReceivingSelectedRP188 (inRegValue & BIT(17));
4059  const bool isReceivingLTC (inRegValue & BIT(18));
4060  const bool isReceivingVITC (inRegValue & BIT(19));
4061  ostringstream oss;
4062  oss << "RP188: " << (isReceivingRP188 ? (isReceivingSelectedRP188 ? "Selected" : "Unselected") : "No") << " RP-188 received"
4063  << (isReceivingLTC ? " +LTC" : "") << (isReceivingVITC ? " +VITC" : "") << endl
4064  << "Bypass: " << (inRegValue & BIT(23) ? (inRegValue & BIT(22) ? "SDI In 2" : "SDI In 1") : "Disabled") << endl
4065  << "Filter: " << HEX0N((inRegValue & 0xFF000000) >> 24, 2) << endl
4066  << "DBB: " << HEX0N((inRegValue & 0x0000FF00) >> 8, 2) << " " << HEX0N(inRegValue & 0x000000FF, 2);
4067  return oss.str();
4068  }
4069  } mRP188InOutDBBRegDecoder;
4070 
4071  struct DecodeVidProcControl : public Decoder
4072  {
4073  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4074  {
4075  (void) inRegNum;
4076  (void) inDeviceID;
4077  ostringstream oss;
4078  static const string sSplitStds [8] = {"1080i", "720p", "480i", "576i", "1080p", "1556i", "?6?", "?7?"};
4079  oss << "Mode: " << (inRegValue & kRegMaskVidProcMode ? ((inRegValue & BIT(24)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
4080  << "FG Control: " << (inRegValue & kRegMaskVidProcFGControl ? ((inRegValue & BIT(20)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
4081  << "BG Control: " << (inRegValue & kRegMaskVidProcBGControl ? ((inRegValue & BIT(22)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
4082  << "VANC Pass-Thru: " << ((inRegValue & BIT(13)) ? "Background" : "Foreground") << endl
4083  << "FG Matte: " << EnabDisab(inRegValue & kRegMaskVidProcFGMatteEnable) << endl
4084  << "BG Matte: " << EnabDisab(inRegValue & kRegMaskVidProcBGMatteEnable) << endl
4085  << "Input Sync: " << (inRegValue & kRegMaskVidProcSyncFail ? "not in sync" : "in sync") << endl
4086  << "Limiting: " << ((inRegValue & BIT(11)) ? "Off" : ((inRegValue & BIT(12)) ? "Legal Broadcast" : "Legal SDI")) << endl
4087  << "Split Video Std: " << sSplitStds[inRegValue & kRegMaskVidProcSplitStd];
4088  return oss.str();
4089  }
4090  } mVidProcControlRegDecoder;
4091 
4092  struct DecodeSplitControl : public Decoder
4093  {
4094  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4095  {
4096  (void) inRegNum;
4097  (void) inDeviceID;
4098  ostringstream oss;
4099  const uint32_t startmask (0x0000FFFF); // 16 bits
4100  const uint32_t slopemask (0x3FFF0000); // 14 bits / high order byte
4101  const uint32_t fractionmask(0x00000007); // 3 bits for fractions
4102  oss << "Split Start: " << HEX0N((inRegValue & startmask) & ~fractionmask, 4) << " "
4103  << HEX0N((inRegValue & startmask) & fractionmask, 4) << endl
4104  << "Split Slope: " << HEX0N(((inRegValue & slopemask) >> 16) & ~fractionmask, 4) << " "
4105  << HEX0N(((inRegValue & slopemask) >> 16) & fractionmask, 4) << endl
4106  << "Split Type: " << ((inRegValue & BIT(30)) ? "Vertical" : "Horizontal");
4107  return oss.str();
4108  }
4109  } mSplitControlRegDecoder;
4110 
4111  struct DecodeFlatMatteValue : public Decoder
4112  {
4113  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4114  {
4115  (void) inRegNum;
4116  (void) inDeviceID;
4117  ostringstream oss;
4118  const uint32_t mask (0x000003FF); // 10 bits
4119  oss << "Flat Matte Cb: " << HEX0N(inRegValue & mask, 3) << endl
4120  << "Flat Matte Y: " << HEX0N(((inRegValue >> 10) & mask) - 0x40, 3) << endl
4121  << "Flat Matte Cr: " << HEX0N((inRegValue >> 20) & mask, 3);
4122  return oss.str();
4123  }
4124  } mFlatMatteValueRegDecoder;
4125 
4126  struct DecodeEnhancedCSCMode : public Decoder
4127  {
4128  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4129  {
4130  (void) inRegNum;
4131  (void) inDeviceID;
4132  static const string sFiltSel[] = {"Full", "Simple", "None", "?"};
4133  static const string sEdgeCtrl[] = {"black", "extended pixels"};
4134  static const string sPixFmts[] = {"RGB 4:4:4", "YCbCr 4:4:4", "YCbCr 4:2:2", "?"};
4135  const uint32_t filterSelect ((inRegValue >> 12) & 0x3);
4136  const uint32_t edgeControl ((inRegValue >> 8) & 0x1);
4137  const uint32_t outPixFmt ((inRegValue >> 4) & 0x3);
4138  const uint32_t inpPixFmt (inRegValue & 0x3);
4139  ostringstream oss;
4140  oss << "Filter select: " << sFiltSel[filterSelect] << endl
4141  << "Filter edge control: " << "Filter to " << sEdgeCtrl[edgeControl] << endl
4142  << "Output pixel format: " << sPixFmts[outPixFmt] << endl
4143  << "Input pixel format: " << sPixFmts[inpPixFmt];
4144  return oss.str();
4145  }
4146  } mEnhCSCModeDecoder;
4147 
4148  struct DecodeEnhancedCSCOffset : public Decoder
4149  {
4150  static string U10Dot6ToFloat (const uint32_t inOffset)
4151  {
4152  double result (double((inOffset >> 6) & 0x3FF));
4153  result += double(inOffset & 0x3F) / 64.0;
4154  ostringstream oss; oss << fDEC(result,12,5); string resultStr(oss.str());
4155  return aja::replace (resultStr, sSpace, sNull);
4156  }
4157  static string U12Dot4ToFloat (const uint32_t inOffset)
4158  {
4159  double result (double((inOffset >> 4) & 0xFFF));
4160  result += double(inOffset & 0xF) / 16.0;
4161  ostringstream oss; oss << fDEC(result,12,4); string resultStr(oss.str());
4162  return aja::replace (resultStr, sSpace, sNull);
4163  }
4164  static string S13Dot2ToFloat (const uint32_t inOffset)
4165  {
4166  double result (double((inOffset >> 2) & 0x1FFF));
4167  result += double(inOffset & 0x3) / 4.0;
4168  if (inOffset & BIT(15))
4169  result = -result;
4170  ostringstream oss; oss << fDEC(result,12,2); string resultStr(oss.str());
4171  return aja::replace (resultStr, sSpace, sNull);
4172  }
4173  static string S11Dot4ToFloat (const uint32_t inOffset)
4174  {
4175  double result (double((inOffset >> 4) & 0x7FF));
4176  result += double(inOffset & 0xF) / 16.0;
4177  if (inOffset & BIT(15))
4178  result = -result;
4179  ostringstream oss; oss << fDEC(result,12,4); string resultStr(oss.str());
4180  return aja::replace (resultStr, sSpace, sNull);
4181  }
4182  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4183  {
4184  (void) inDeviceID;
4185  const uint32_t regNum (inRegNum & 0x1F);
4186  const uint32_t lo (inRegValue & 0x0000FFFF);
4187  const uint32_t hi ((inRegValue >> 16) & 0xFFFF);
4188  ostringstream oss;
4189  switch (regNum)
4190  {
4191  case 1: oss << "Component 0 input offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)" << endl
4192  << "Component 1 input offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4193  break;
4194  case 2: oss << "Component 2 input offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)";
4195  break;
4196  case 12: oss << "Component A output offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)" << endl
4197  << "Component B output offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4198  break;
4199  case 13: oss << "Component C output offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)";
4200  break;
4201  case 15: oss << "Key input offset: " << S13Dot2ToFloat(lo) << " (12-bit), " << S11Dot4ToFloat(lo) << " (10-bit)" << endl
4202  << "Key output offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4203  break;
4204  default: break;
4205  }
4206  return oss.str();
4207  }
4208  } mEnhCSCOffsetDecoder;
4209 
4210  struct DecodeEnhancedCSCKeyMode : public Decoder
4211  {
4212  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4213  {
4214  (void) inRegNum;
4215  (void) inDeviceID;
4216  static const string sSrcSel[] = {"Key Input", "Video Y Input"};
4217  static const string sRange[] = {"Full Range", "SMPTE Range"};
4218  const uint32_t keySrcSelect (inRegValue & 0x1);
4219  const uint32_t keyOutRange ((inRegValue >> 4) & 0x1);
4220  ostringstream oss;
4221  oss << "Key Source Select: " << sSrcSel[keySrcSelect] << endl
4222  << "Key Output Range: " << sRange[keyOutRange];
4223  return oss.str();
4224  }
4225  } mEnhCSCKeyModeDecoder;
4226 
4227  struct DecodeEnhancedCSCCoefficient : public Decoder
4228  {
4229  static string S2Dot15ToFloat (const uint32_t inCoefficient)
4230  {
4231  double result = (double((inCoefficient >> 15) & 0x3));
4232  result += double(inCoefficient & 0x7FFF) / 32768.0;
4233  if (inCoefficient & BIT(17))
4234  result = -result;
4235  ostringstream oss; oss << fDEC(result,12,10); string resultStr(oss.str());
4236  return aja::replace(resultStr, sSpace, sNull);
4237  }
4238  static string S12Dot12ToFloat (const uint32_t inCoefficient)
4239  {
4240  double result(double((inCoefficient >> 12) & 0xFFF));
4241  result += double(inCoefficient & 0xFFF) / 4096.0;
4242  if (inCoefficient & BIT(24))
4243  result = -result;
4244  ostringstream oss; oss << fDEC(result,12,6); string resultStr(oss.str());
4245  return aja::replace(resultStr, sSpace, sNull);
4246  }
4247  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4248  {
4249  (void) inDeviceID;
4250  uint32_t regNum (inRegNum & 0x1F);
4251  ostringstream oss;
4252  if (regNum > 2 && regNum < 12)
4253  {
4254  regNum -= 3;
4255  static const string sCoeffNames[] = {"A0", "A1", "A2", "B0", "B1", "B2", "C0", "C1", "C2"};
4256  const uint32_t coeff ((inRegValue >> 9) & 0x0003FFFF);
4257  oss << sCoeffNames[regNum] << " coefficient: " << S2Dot15ToFloat(coeff) << " (" << xHEX0N(coeff,8) << ")";
4258  }
4259  else if (regNum == 16)
4260  {
4261  const uint32_t gain ((inRegValue >> 4) & 0x01FFFFFF);
4262  oss << "Key gain: " << S12Dot12ToFloat(gain) << " (" << HEX0N(gain,8) << ")";
4263  }
4264  return oss.str();
4265  }
4266  } mEnhCSCCoeffDecoder;
4267 
4268  struct DecodeCSCoeff1234 : public Decoder
4269  {
4270  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4271  {
4272  (void) inDeviceID;
4273  const uint32_t coeff1 (((inRegValue >> 11) & 0x00000003) | uint32_t(inRegValue & 0x000007FF));
4274  const uint32_t coeff2 ((inRegValue >> 14) & 0x00001FFF);
4275  uint16_t nCoeff1(1), nCoeff2(2);
4276  switch(inRegNum)
4277  {
4278  case kRegCSCoefficients3_4: case kRegCS2Coefficients3_4: case kRegCS3Coefficients3_4: case kRegCS4Coefficients3_4:
4279  case kRegCS5Coefficients3_4: case kRegCS6Coefficients3_4: case kRegCS7Coefficients3_4: case kRegCS8Coefficients3_4:
4280  nCoeff1 = 3; nCoeff2 = 4; break;
4281  }
4282  // kRegCS?Coefficients1_2 kRegCS?Coefficients3_4
4283  // CSC 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
4284  // RegNum 142 147 291 296 347 460 465 470 143 148 292 297 348 461 466 471
4285  // kRegCS?Coefficients1_2: kK2RegMaskVidKeySyncStatus = BIT(28) 0=OK 1=SyncFail GetColorSpaceVideoKeySyncFail
4286  // kRegCS?Coefficients1_2: kK2RegMaskMakeAlphaFromKeySelect = BIT(29) 0=No 1=Yes GetColorSpaceMakeAlphaFromKey
4287  // kRegCS?Coefficients1_2: kK2RegMaskColorSpaceMatrixSelect = BIT(30) 0=Rec709 1=Rec601 GetColorSpaceMatrixSelect
4288  // kRegCS?Coefficients1_2: kK2RegMaskUseCustomCoefSelect = BIT(31) 0=No 1=Yes GetColorSpaceUseCustomCoefficient
4289  // kRegCS?Coefficients3_4: kK2RegMaskXena2RGBRange = BIT(31) 0=Full 1=SMPTE GetColorSpaceRGBBlackRange
4290  // kK2RegMaskCustomCoefficientLow = BITS(0-10) CSCCustomCoeffs.Coefficient1 GetColorSpaceCustomCoefficients
4291  // kK2RegMaskCustomCoefficientHigh = BITS(16-26) CSCCustomCoeffs.Coefficient2 GetColorSpaceCustomCoefficients
4292  // kK2RegMaskCustomCoefficient12BitLow = BITS(0-12) CSCCustomCoeffs.Coefficient1 GetColorSpaceCustomCoefficients12Bit
4293  // kK2RegMaskCustomCoefficient12BitHigh= BITS(14-26) CSCCustomCoeffs.Coefficient2 GetColorSpaceCustomCoefficients12Bit
4294  ostringstream oss;
4295  if (nCoeff1 == 1)
4296  oss << "Video Key Sync Status: " << (inRegValue & BIT(28) ? "SyncFail" : "OK") << endl
4297  << "Make Alpha From Key Input: " << EnabDisab(inRegValue & BIT(29)) << endl
4298  << "Matrix Select: " << (inRegValue & BIT(30) ? "Rec601" : "Rec709") << endl
4299  << "Use Custom Coeffs: " << YesNo(inRegValue & BIT(31)) << endl;
4300  else
4301  oss << "RGB Range: " << (inRegValue & BIT(31) ? "SMPTE (0x040-0x3C0)" : "Full (0x000-0x3FF)") << endl;
4302  oss << "Coefficient" << DEC(nCoeff1) << ": " << xHEX0N(coeff1, 4) << endl
4303  << "Coefficient" << DEC(nCoeff2) << ": " << xHEX0N(coeff2, 4);
4304  return oss.str();
4305  }
4306  } mCSCoeff1234Decoder;
4307 
4308  struct DecodeCSCoeff567890 : public Decoder
4309  {
4310  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4311  {
4312  (void) inDeviceID;
4313  const uint32_t coeff5 (((inRegValue >> 11) & 0x00000003) | uint32_t(inRegValue & 0x000007FF));
4314  const uint32_t coeff6 ((inRegValue >> 14) & 0x00001FFF);
4315  uint16_t nCoeff5(5), nCoeff6(6);
4316  switch(inRegNum)
4317  {
4318  case kRegCSCoefficients7_8: case kRegCS2Coefficients7_8: case kRegCS3Coefficients7_8: case kRegCS4Coefficients7_8:
4319  case kRegCS5Coefficients7_8: case kRegCS6Coefficients7_8: case kRegCS7Coefficients7_8: case kRegCS8Coefficients7_8:
4320  nCoeff5 = 7; nCoeff6 = 8; break;
4321  case kRegCSCoefficients9_10: case kRegCS2Coefficients9_10: case kRegCS3Coefficients9_10: case kRegCS4Coefficients9_10:
4322  case kRegCS5Coefficients9_10: case kRegCS6Coefficients9_10: case kRegCS7Coefficients9_10: case kRegCS8Coefficients9_10:
4323  nCoeff5 = 9; nCoeff6 = 10; break;
4324  }
4325  // kRegCS?Coefficients5_6 kRegCS?Coefficients7_8 kRegCS?Coefficients9_10
4326  // CSC 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
4327  // RegNum 143 148 292 297 348 461 466 471 144 149 293 298 349 462 467 472 145 150 294 299 350 463 468 473
4328  // kK2RegMaskCustomCoefficientLow = BITS(0-10) CSCCustomCoeffs.Coefficient5 GetColorSpaceCustomCoefficients
4329  // kK2RegMaskCustomCoefficientHigh = BITS(16-26) CSCCustomCoeffs.Coefficient6 GetColorSpaceCustomCoefficients
4330  // kK2RegMaskCustomCoefficient12BitLow = BITS(0-12) CSCCustomCoeffs.Coefficient5 GetColorSpaceCustomCoefficients12Bit
4331  // kK2RegMaskCustomCoefficient12BitHigh= BITS(14-26) CSCCustomCoeffs.Coefficient6 GetColorSpaceCustomCoefficients12Bit
4332  ostringstream oss;
4333  oss << "Coefficient" << DEC(nCoeff5) << ": " << xHEX0N(coeff5, 4) << endl
4334  << "Coefficient" << DEC(nCoeff6) << ": " << xHEX0N(coeff6, 4);
4335  return oss.str();
4336  }
4337  } mCSCoeff567890Decoder;
4338 
4339  struct DecodeLUTV1ControlReg : public Decoder // kRegCh1ColorCorrectionControl (68), kRegCh2ColorCorrectionControl (69)
4340  {
4341  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4342  { static const string sModes[] = {"Off", "RGB", "YCbCr", "3-Way", "Invalid"};
4343  const ULWord lutVersion (::NTV2DeviceGetLUTVersion(inDeviceID));
4344  const UWord saturation (UWord(inRegValue & kRegMaskSaturationValue));
4345  const UWord mode (UWord((inRegValue & kRegMaskCCMode) >> kRegShiftCCMode));
4346  const bool outBankSelect (((inRegValue & kRegMaskCCOutputBankSelect) >> kRegShiftCCOutputBankSelect) ? true : false);
4347  const bool cc5HostBank (((inRegValue & kRegMaskCC5HostAccessBankSelect) >> kRegShiftCC5HostAccessBankSelect) ? true : false);
4348  const bool cc5OutputBank (((inRegValue & kRegMaskCC5OutputBankSelect) >> kRegShiftCC5OutputBankSelect) ? true : false);
4349  const bool cc5Select (((inRegValue & kRegMaskLUT5Select) >> kRegShiftLUT5Select) ? true : false);
4350  const bool ccConfig2 (((inRegValue & kRegMaskLUTSelect) >> kRegShiftLUTSelect) ? true : false);
4351  const bool cc3BankSel (((inRegValue & kRegMaskCC3OutputBankSelect) >> kRegShiftCC3OutputBankSelect) ? true : false);
4352  const bool cc4BankSel (((inRegValue & kRegMaskCC4OutputBankSelect) >> kRegShiftCC4OutputBankSelect) ? true : false);
4353  NTV2_ASSERT(mode < 4);
4354  ostringstream oss;
4355  if (lutVersion != 1)
4356  oss << "(Register data relevant for V1 LUT, this device has V" << DEC(lutVersion) << " LUT)";
4357  else
4358  {
4359  oss << "LUT Saturation Value: " << xHEX0N(saturation,4) << " (" << DEC(saturation) << ")" << endl
4360  << "LUT Output Bank Select: " << SetNotset(outBankSelect) << endl
4361  << "LUT Mode: " << sModes[mode] << " (" << DEC(mode) << ")";
4362  if (inRegNum == kRegCh1ColorCorrectionControl)
4363  oss << endl
4364  << "LUT5 Host Bank Select: " << SetNotset(cc5HostBank) << endl
4365  << "LUT5 Output Bank Select: " << SetNotset(cc5OutputBank) << endl
4366  << "LUT5 Select: " << SetNotset(cc5Select) << endl
4367  << "Config 2nd LUT Set: " << YesNo(ccConfig2);
4368  }
4369  oss << endl
4370  << "LUT3 Bank Select: " << SetNotset(cc3BankSel) << endl
4371  << "LUT4 Bank Select: " << SetNotset(cc4BankSel);
4372  return oss.str();
4373  }
4374  } mLUTV1ControlRegDecoder;
4375 
4376  struct DecodeLUTV2ControlReg : public Decoder // kRegLUTV2Control 376
4377  {
4378  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4379  { (void) inRegNum;
4380  const ULWord lutVersion (::NTV2DeviceGetLUTVersion(inDeviceID));
4381  ostringstream oss;
4382  if (lutVersion != 2)
4383  oss << "(Register data relevant for V2 LUT, this device has V" << DEC(lutVersion) << "LUT)";
4384  else
4385  {
4386  for (UWord lutNum(0); lutNum < 8; lutNum++)
4387  oss << "LUT" << DEC(lutNum+1) << " Enabled: " << (YesNo(inRegValue & (1<<lutNum))) << endl
4388  << "LUT" << DEC(lutNum+1) << " Host Access Bank Select: " << (inRegValue & (1<<(lutNum+8)) ? '1' : '0') << endl
4389  << "LUT" << DEC(lutNum+1) << " Output Bank Select: " << (inRegValue & (1<<(lutNum+16)) ? '1' : '0') << endl;
4390  oss << "12-Bit LUT mode: " << ((inRegValue & BIT(28)) ? "12-bit" : "10-bit") << endl
4391  << "12-Bit LUT page reg: " << DEC(UWord((inRegValue & (BIT(24)|BIT(25))) >> 24));
4392  }
4393  return oss.str();
4394  }
4395  } mLUTV2ControlRegDecoder;
4396 
4397  struct DecodeLUT : public Decoder
4398  {
4399  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4400  {
4401  (void) inDeviceID;
4402  static const ULWord RedReg(kColorCorrectionLUTOffset_Red/4), GreenReg(kColorCorrectionLUTOffset_Green/4), BlueReg(kColorCorrectionLUTOffset_Blue/4);
4403  const bool isRed(inRegNum >= RedReg && inRegNum < GreenReg), isGreen(inRegNum >= GreenReg && inRegNum < BlueReg), isBlue(inRegNum>=BlueReg);
4404  NTV2_ASSERT(isRed||isGreen||isBlue);
4405  ostringstream oss;
4406  // Within each 32-bit LUT word are stored two 10-bit values:
4407  // - bits <31:22> ==> LUT[2i+1]
4408  // - bits <15:6> ==> LUT[2i]
4409  const string label(isRed ? "Red[" : (isGreen ? "Green[" : "Blue["));
4410  const ULWord ndx((inRegNum - (isRed ? RedReg : (isGreen ? GreenReg : BlueReg))) * 2);
4411  const ULWord lo((inRegValue >> kRegColorCorrectionLUTEvenShift) & 0x000003FF);
4412  const ULWord hi((inRegValue >> kRegColorCorrectionLUTOddShift) & 0x000003FF);
4413  oss << label << DEC0N(ndx+0,3) << "]: " << DEC0N(lo,3) << endl
4414  << label << DEC0N(ndx+1,3) << "]: " << DEC0N(hi,3);
4415  return oss.str();
4416  }
4417  } mLUTDecoder;
4418 
4419  struct DecodeSDIErrorStatus : public Decoder
4420  {
4421  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4422  {
4423  (void) inRegNum;
4424  (void) inDeviceID;
4425  ostringstream oss;
4426  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
4427  oss << "Unlock Tally: " << DEC(inRegValue & 0x7FFF) << endl
4428  << "Locked: " << YesNo(inRegValue & BIT(16)) << endl
4429  << "Link A VPID Valid: " << YesNo(inRegValue & BIT(20)) << endl
4430  << "Link B VPID Valid: " << YesNo(inRegValue & BIT(21)) << endl
4431  << "TRS Error Detected: " << YesNo(inRegValue & BIT(24));
4432  return oss.str();
4433  }
4434  } mSDIErrorStatusRegDecoder;
4435 
4436  struct DecodeSDIErrorCount : public Decoder
4437  {
4438  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4439  {
4440  (void) inRegNum;
4441  (void) inDeviceID;
4442  ostringstream oss;
4443  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
4444  oss << "Link A: " << DEC(inRegValue & 0x0000FFFF) << endl
4445  << "Link B: " << DEC((inRegValue & 0xFFFF0000) >> 16);
4446  return oss.str();
4447  }
4448  } mSDIErrorCountRegDecoder;
4449 
4450  struct DecodeDriverVersion : public Decoder
4451  {
4452  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4453  { (void) inDeviceID;
4454  NTV2_ASSERT(inRegNum == kVRegDriverVersion);
4455  ULWord vMaj(NTV2DriverVersionDecode_Major(inRegValue)), vMin(NTV2DriverVersionDecode_Minor(inRegValue));
4456  ULWord vDot(NTV2DriverVersionDecode_Point(inRegValue)), vBld(NTV2DriverVersionDecode_Build(inRegValue));
4457  ULWord buildType((inRegValue >> 30) & 0x00000003);
4458  static const string sBuildTypes[] = { "Release", "Beta", "Alpha", "Development"};
4459  static const string sBldTypes[] = { "", "b", "a", "d"};
4460  ostringstream oss;
4461  oss << "Driver Version: " << DEC(vMaj) << "." << DEC(vMin) << "." << DEC(vDot);
4462  if (buildType) oss << sBldTypes[buildType] << DEC(vBld);
4463  oss << endl
4464  << "Major Version: " << DEC(vMaj) << endl
4465  << "Minor Version: " << DEC(vMin) << endl
4466  << "Point Version: " << DEC(vDot) << endl
4467  << "Build Type: " << sBuildTypes[buildType] << endl
4468  << "Build Number: " << DEC(vBld);
4469  return oss.str();
4470  }
4471  } mDriverVersionDecoder;
4472 
4473  struct DecodeFourCC : public Decoder
4474  {
4475  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4476  { (void) inDeviceID; (void) inRegNum;
4477  char ch; string str4cc;
4478  ch = char((inRegValue & 0xFF000000) >> 24);
4479  str4cc += ::isprint(ch) ? ch : '?';
4480  ch = char((inRegValue & 0x00FF0000) >> 16);
4481  str4cc += ::isprint(ch) ? ch : '?';
4482  ch = char((inRegValue & 0x0000FF00) >> 8);
4483  str4cc += ::isprint(ch) ? ch : '?';
4484  ch = char((inRegValue & 0x000000FF) >> 0);
4485  str4cc += ::isprint(ch) ? ch : '?';
4486 
4487  ostringstream oss;
4488  oss << "'" << str4cc << "'";
4489  return oss.str();
4490  }
4491  } mDecodeFourCC;
4492 
4493  struct DecodeDriverType : public Decoder
4494  {
4495  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4496  { (void) inDeviceID; (void) inRegNum;
4497  ostringstream oss;
4498  #if defined(AJAMac)
4499  if (inRegValue == 0x44455854) // 'DEXT'
4500  oss << "DriverKit ('DEXT')";
4501  else if (inRegValue)
4502  oss << "(Unknown/Invalid " << xHEX0N(inRegValue,8) << ")";
4503  else
4504  oss << "Kernel Extension ('KEXT')";
4505  #else
4506  (void) inRegValue;
4507  oss << "(Normal)";
4508  #endif
4509  return oss.str();
4510  }
4511  } mDecodeDriverType;
4512 
4513  struct DecodeIDSwitchStatus : public Decoder
4514  {
4515  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4516  { (void) inRegNum;
4517  ostringstream oss;
4518  if (::NTV2DeviceCanDoIDSwitch(inDeviceID))
4519  {
4520  const uint32_t switchEnableBits (((inRegValue & 0x0F000000) >> 20) | ((inRegValue & 0xF0000000) >> 28));
4521  for (UWord idSwitch(0); idSwitch < 4; )
4522  {
4523  const uint32_t switchEnabled (switchEnableBits & BIT(idSwitch));
4524  oss << "Switch " << DEC(++idSwitch) << ": " << (switchEnabled ? "Enabled" : "Disabled");
4525  if (idSwitch < 4)
4526  oss << endl;
4527  }
4528  }
4529  else
4530  {
4531  oss << "(ID Switch not supported)";
4532  }
4533 
4534  return oss.str();
4535  }
4536  } mDecodeIDSwitchStatus;
4537 
4538  struct DecodePWMFanControl : public Decoder
4539  {
4540  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4541  { (void) inRegNum;
4542  ostringstream oss;
4543  if (::NTV2DeviceHasPWMFanControl(inDeviceID))
4544  oss << "Fan Speed: " << DEC(inRegValue & kRegMaskPWMFanSpeed) << endl
4545  << "Fan Control Enabled: " << ((inRegValue & kRegMaskPWMFanSpeedControl) ? "Enabled" : "Disabled");
4546  return oss.str();
4547  }
4548  } mDecodePWMFanControl;
4549 
4550  struct DecodePWMFanMonitor : public Decoder
4551  {
4552  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4553  { (void) inRegNum;
4554  ostringstream oss;
4555  if (::NTV2DeviceHasPWMFanControl(inDeviceID))
4556  oss << "Tach Period: " << DEC(inRegValue & kRegMaskPWMFanTachPeriodStatus) << endl
4557  << "Fan Status: " << ((inRegValue & kRegMaskPWMFanStatus) ? "Stopped" : "Running");
4558  return oss.str();
4559  }
4560  } mDecodePWMFanMonitor;
4561 
4562  struct DecodeBOBStatus : public Decoder
4563  {
4564  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4565  { (void) inRegNum;
4566  ostringstream oss;
4567  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4568  oss << "Break Out Board: " << ((inRegValue & kRegMaskBOBAbsent) ? "Disconnected" : "Connected") << endl
4569  << "ADAV801 Initialization: " << ((inRegValue & kRegMaskBOBADAV801UpdateStatus) ? "Complete" : "In Progress") << endl
4570  << "ADAV801 DIR Locked(Debug): " << DEC(inRegValue & kRegMaskBOBADAV801DIRLocked);
4571  else
4572  oss << "Device does not support a breakout board";
4573  return oss.str();
4574  }
4575  } mDecodeBOBStatus;
4576 
4577  struct DecodeBOBGPIIn : public Decoder
4578  {
4579  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4580  { (void) inRegNum;
4581  ostringstream oss;
4582  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4583  oss << "GPI In 1: " << DEC(inRegValue & kRegMaskBOBGPIIn1Data) << endl
4584  << "GPI In 2: " << DEC(inRegValue & kRegMaskBOBGPIIn2Data) << endl
4585  << "GPI In 3: " << DEC(inRegValue & kRegMaskBOBGPIIn3Data) << endl
4586  << "GPI In 4: " << DEC(inRegValue & kRegMaskBOBGPIIn4Data) ;
4587  else
4588  oss << "Device does not support a breakout board";
4589  return oss.str();
4590  }
4591  } mDecodeBOBGPIIn;
4592 
4593  struct DecodeBOBGPIInInterruptControl : public Decoder
4594  {
4595  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4596  { (void) inRegNum;
4597  ostringstream oss;
4598  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4599  oss << "GPI In 1 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn1InterruptControl) << endl
4600  << "GPI In 2 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn2InterruptControl) << endl
4601  << "GPI In 3 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn3InterruptControl) << endl
4602  << "GPI In 4 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn4InterruptControl) ;
4603  else
4604  oss << "Device does not support a breakout board";
4605  return oss.str();
4606  }
4607  } mDecodeBOBGPIInInterruptControl;
4608 
4609  struct DecodeBOBGPIOut : public Decoder
4610  {
4611  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4612  { (void) inRegNum;
4613  ostringstream oss;
4614  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4615  oss << "GPI Out 1 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut1Data) << endl
4616  << "GPI Out 2 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut2Data) << endl
4617  << "GPI Out 3 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut3Data) << endl
4618  << "GPI Out 4 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut4Data) ;
4619  else
4620  oss << "Device does not support a breakout board";
4621  return oss.str();
4622  }
4623  } mDecodeBOBGPIOut;
4624 
4625  struct DecodeBOBAudioControl : public Decoder
4626  {
4627  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4628  { (void) inRegNum;
4629  ostringstream oss;
4630  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4631  {
4632  string dBuLabel;
4633  switch(inRegValue & kRegMaskBOBAnalogLevelControl)
4634  {
4635  case 0:
4636  dBuLabel = "+24dBu";
4637  break;
4638  case 1:
4639  dBuLabel = "+18dBu";
4640  break;
4641  case 2:
4642  dBuLabel = "+12dBu";
4643  break;
4644  case 3:
4645  dBuLabel = "+15dBu";
4646  break;
4647 
4648  }
4649  oss << "ADC/DAC Re-init: " << DEC(inRegValue & kRegMaskBOBADAV801Reset) << endl
4650  << "Analog Level Control: " << dBuLabel << endl
4651  << "Analog Select: " << DEC(inRegValue & kRegMaskBOBAnalogInputSelect);
4652  }
4653  else
4654  oss << "Device does not support a breakout board";
4655  return oss.str();
4656  }
4657  } mDecodeBOBAudioControl;
4658 
4659  struct DecodeLEDControl : public Decoder
4660  {
4661  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4662  { (void) inRegNum;
4663  ostringstream oss;
4664  if (::NTV2DeviceHasBracketLED(inDeviceID))
4665  oss << "Blue: " << DEC(inRegValue & kRegMaskLEDBlueControl) << endl
4666  << "Green: " << DEC(inRegValue & kRegMaskLEDGreenControl) << endl
4667  << "Red: " << DEC(inRegValue & kRegMaskLEDRedControl);
4668  else
4669  oss << "Device does not support a breakout board";
4670  return oss.str();
4671  }
4672  } mDecodeLEDControl;
4673 
4674  static const int NOREADWRITE = 0;
4675  static const int READONLY = 1;
4676  static const int WRITEONLY = 2;
4677  static const int READWRITE = 3;
4678 
4679  static const int CONTAINS = 0;
4680  static const int STARTSWITH = 1;
4681  static const int ENDSWITH = 2;
4682  static const int EXACTMATCH = 3;
4683 
4684  typedef map <uint32_t, const Decoder *> RegNumToDecoderMap;
4685  typedef pair <uint32_t, const Decoder *> RegNumToDecoderPair;
4686  typedef multimap <string, uint32_t> RegClassToRegNumMMap, StringToRegNumMMap;
4687  typedef pair <string, uint32_t> StringToRegNumPair;
4688  typedef RegClassToRegNumMMap::const_iterator RegClassToRegNumConstIter;
4689  typedef StringToRegNumMMap::const_iterator StringToRegNumConstIter;
4690 
4691  typedef pair <uint32_t, uint32_t> XptRegNumAndMaskIndex; // First: register number; second: mask index (0=0x000000FF, 1=0x0000FF00, 2=0x00FF0000, 3=0xFF000000)
4692  typedef map <NTV2InputCrosspointID, XptRegNumAndMaskIndex> InputXpt2XptRegNumMaskIndexMap;
4693  typedef map <XptRegNumAndMaskIndex, NTV2InputCrosspointID> XptRegNumMaskIndex2InputXptMap;
4694  typedef InputXpt2XptRegNumMaskIndexMap::const_iterator InputXpt2XptRegNumMaskIndexMapConstIter;
4695  typedef XptRegNumMaskIndex2InputXptMap::const_iterator XptRegNumMaskIndex2InputXptMapConstIter;
4696 
4697 private: // INSTANCE DATA
4698  mutable AJALock mGuardMutex;
4699  RegNumToStringMap mRegNumToStringMap;
4700  RegNumToDecoderMap mRegNumToDecoderMap;
4701  RegClassToRegNumMMap mRegClassToRegNumMMap;
4702  StringToRegNumMMap mStringToRegNumMMap;
4703  mutable NTV2StringSet mAllRegClasses; // Mutable -- caches results from 'const' method GetAllRegisterClasses
4704  InputXpt2XptRegNumMaskIndexMap mInputXpt2XptRegNumMaskIndexMap;
4705  XptRegNumMaskIndex2InputXptMap mXptRegNumMaskIndex2InputXptMap;
4706 
4707 }; // RegisterExpert
4708 
4709 
4710 static RegisterExpertPtr gpRegExpert; // Points to Register Expert Singleton
4711 static AJALock gRegExpertGuardMutex;
4712 
4713 
4714 RegisterExpertPtr RegisterExpert::GetInstance(const bool inCreateIfNecessary)
4715 {
4716  AJAAutoLock locker(&gRegExpertGuardMutex);
4717  if (!gpRegExpert && inCreateIfNecessary)
4718  gpRegExpert = new RegisterExpert;
4719  return gpRegExpert;
4720 }
4721 
4722 bool RegisterExpert::DisposeInstance(void)
4723 {
4724  AJAAutoLock locker(&gRegExpertGuardMutex);
4725  if (!gpRegExpert)
4726  return false;
4727  gpRegExpert = AJA_NULL;
4728  return true;
4729 }
4730 
4731 bool CNTV2RegisterExpert::Allocate(void)
4732 {
4733  AJAAutoLock lock(&gRegExpertGuardMutex);
4734  RegisterExpertPtr pInst(RegisterExpert::GetInstance(true));
4735  return pInst ? true : false;
4736 }
4737 
4738 bool CNTV2RegisterExpert::IsAllocated(void)
4739 {
4740  AJAAutoLock lock(&gRegExpertGuardMutex);
4741  RegisterExpertPtr pInst(RegisterExpert::GetInstance(false));
4742  return pInst ? true : false;
4743 }
4744 
4745 bool CNTV2RegisterExpert::Deallocate(void)
4746 {
4747  AJAAutoLock lock(&gRegExpertGuardMutex);
4748  RegisterExpertPtr pInst(RegisterExpert::GetInstance(false));
4749  return pInst ? pInst->DisposeInstance() : false;
4750 }
4751 
4752 string CNTV2RegisterExpert::GetDisplayName (const uint32_t inRegNum)
4753 {
4754  AJAAutoLock locker(&gRegExpertGuardMutex);
4755  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4756  if (pRegExpert)
4757  return pRegExpert->RegNameToString(inRegNum);
4758 
4759  ostringstream oss; oss << "Reg ";
4760  if (inRegNum <= kRegNumRegisters)
4761  oss << DEC(inRegNum);
4762  else if (inRegNum <= 0x0000FFFF)
4763  oss << xHEX0N(inRegNum,4);
4764  else
4765  oss << xHEX0N(inRegNum,8);
4766  return oss.str();
4767 }
4768 
4769 string CNTV2RegisterExpert::GetDisplayValue (const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID)
4770 {
4771  AJAAutoLock locker(&gRegExpertGuardMutex);
4772  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4773  return pRegExpert ? pRegExpert->RegValueToString(inRegNum, inRegValue, inDeviceID) : string();
4774 }
4775 
4776 bool CNTV2RegisterExpert::IsRegisterInClass (const uint32_t inRegNum, const string & inClassName)
4777 {
4778  AJAAutoLock locker(&gRegExpertGuardMutex);
4779  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4780  return pRegExpert ? pRegExpert->IsRegInClass(inRegNum, inClassName) : false;
4781 }
4782 
4783 NTV2StringSet CNTV2RegisterExpert::GetAllRegisterClasses (void)
4784 {
4785  AJAAutoLock locker(&gRegExpertGuardMutex);
4786  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4787  return pRegExpert ? pRegExpert->GetAllRegisterClasses() : NTV2StringSet();
4788 }
4789 
4790 NTV2StringSet CNTV2RegisterExpert::GetRegisterClasses (const uint32_t inRegNum, const bool inRemovePrefix)
4791 {
4792  AJAAutoLock locker(&gRegExpertGuardMutex);
4793  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4794  return pRegExpert ? pRegExpert->GetRegisterClasses(inRegNum, inRemovePrefix) : NTV2StringSet();
4795 }
4796 
4797 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForClass (const string & inClassName)
4798 {
4799  AJAAutoLock locker(&gRegExpertGuardMutex);
4800  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4801  return pRegExpert ? pRegExpert->GetRegistersForClass(inClassName) : NTV2RegNumSet();
4802 }
4803 
4804 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForChannel (const NTV2Channel inChannel)
4805 {
4806  AJAAutoLock locker(&gRegExpertGuardMutex);
4807  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4808  return NTV2_IS_VALID_CHANNEL(inChannel) ? (pRegExpert ? pRegExpert->GetRegistersForClass(gChlClasses[inChannel]):NTV2RegNumSet()) : NTV2RegNumSet();
4809 }
4810 
4811 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForDevice (const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude)
4812 {
4813  AJAAutoLock locker(&gRegExpertGuardMutex);
4814  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4815  return pRegExpert ? pRegExpert->GetRegistersForDevice(inDeviceID, inOtherRegsToInclude) : NTV2RegNumSet();
4816 }
4817 
4818 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersWithName (const string & inName, const int inSearchStyle)
4819 {
4820  AJAAutoLock locker(&gRegExpertGuardMutex);
4821  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4822  return pRegExpert ? pRegExpert->GetRegistersWithName(inName, inSearchStyle) : NTV2RegNumSet();
4823 }
4824 
4825 NTV2InputCrosspointID CNTV2RegisterExpert::GetInputCrosspointID (const uint32_t inXptRegNum, const uint32_t inMaskIndex)
4826 {
4827  AJAAutoLock locker(&gRegExpertGuardMutex);
4828  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4829  return pRegExpert ? pRegExpert->GetInputCrosspointID(inXptRegNum, inMaskIndex) : NTV2_INPUT_CROSSPOINT_INVALID;
4830 }
4831 
4832 bool CNTV2RegisterExpert::GetCrosspointSelectGroupRegisterInfo (const NTV2InputCrosspointID inInputXpt, uint32_t & outXptRegNum, uint32_t & outMaskIndex)
4833 {
4834  AJAAutoLock locker(&gRegExpertGuardMutex);
4835  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4836  return pRegExpert ? pRegExpert->GetXptRegNumAndMaskIndex(inInputXpt, outXptRegNum, outMaskIndex) : false;
4837 }
kRegSDIOut6VPIDB
@ kRegSDIOut6VPIDB
Definition: ntv2publicinterface.h:590
kVRegHDMIOutControl3
@ kVRegHDMIOutControl3
Definition: ntv2virtualregisters.h:657
kRegDMA1NextDescHigh
@ kRegDMA1NextDescHigh
Definition: ntv2publicinterface.h:226
kVRegServicesModeFinal
@ kVRegServicesModeFinal
Definition: ntv2virtualregisters.h:495
kRegSDIInput3GStatus
@ kRegSDIInput3GStatus
Definition: ntv2publicinterface.h:373
kVRegTxc_2EncodeBitDepth1
@ kVRegTxc_2EncodeBitDepth1
Definition: ntv2virtualregisters.h:430
NTV2DeviceGetNumLTCInputs
UWord NTV2DeviceGetNumLTCInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11990
regAncExtFID
@ regAncExtFID
Definition: ntv2publicinterface.h:5360
CNTV2RegisterExpert::GetCrosspointSelectGroupRegisterInfo
static bool GetCrosspointSelectGroupRegisterInfo(const NTV2InputCrosspointID inInputXpt, uint32_t &outXptRegNum, uint32_t &outMaskIndex)
Answers with the crosspoint select register and mask information for a given widget input.
Definition: ntv2registerexpert.cpp:4832
kRegMaskLEDGreenControl
@ kRegMaskLEDGreenControl
Definition: ntv2publicinterface.h:2321
kVRegTxc_2EncodeStreamType2
@ kVRegTxc_2EncodeStreamType2
Definition: ntv2virtualregisters.h:446
regNTV4FS_RasterOffsetRed
@ regNTV4FS_RasterOffsetRed
Definition: ntv2registerexpert.cpp:75
NTV2DeviceCanDoCustomAux
bool NTV2DeviceCanDoCustomAux(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2367
regAncExtField2AnalogCFilter
@ regAncExtField2AnalogCFilter
Definition: ntv2publicinterface.h:5372
kRegGlobalControlCh3
@ kRegGlobalControlCh3
Definition: ntv2publicinterface.h:546
kRegShiftLUTSelect
@ kRegShiftLUTSelect
Definition: ntv2publicinterface.h:2539
kVRegMonAncField1Offset
@ kVRegMonAncField1Offset
Monitor Anc Field1 byte offset from end of frame buffer (IoIP only, GUMP)
Definition: ntv2virtualregisters.h:332
kVRegVideoFormatCh4
@ kVRegVideoFormatCh4
Definition: ntv2virtualregisters.h:350
kRegHDMIV2VSyncDurationAndBackPorchField1
@ kRegHDMIV2VSyncDurationAndBackPorchField1
Definition: ntv2publicinterface.h:529
kRegSDIOut4Control
@ kRegSDIOut4Control
Definition: ntv2publicinterface.h:308
kVRegHDMIOutHDRMasterLuminance2
@ kVRegHDMIOutHDRMasterLuminance2
Definition: ntv2virtualregisters.h:653
kRegMaskBOBGPIIn3InterruptControl
@ kRegMaskBOBGPIIn3InterruptControl
Definition: ntv2publicinterface.h:2308
kRegGlobalControlCh5
@ kRegGlobalControlCh5
Definition: ntv2publicinterface.h:548
regAncExtTotalFrameLines
@ regAncExtTotalFrameLines
Definition: ntv2publicinterface.h:5359
kVRegAnalogAudioIOConfiguration
@ kVRegAnalogAudioIOConfiguration
Definition: ntv2virtualregisters.h:487
kRegSDIIn8VPIDB
@ kRegSDIIn8VPIDB
Definition: ntv2publicinterface.h:608
kVRegClearAllSubscriptions
@ kVRegClearAllSubscriptions
Definition: ntv2virtualregisters.h:65
kRegSDIWatchdogTimeout
@ kRegSDIWatchdogTimeout
Definition: ntv2publicinterface.h:458
kVRegProgressivePicture
@ kVRegProgressivePicture
Definition: ntv2virtualregisters.h:223
NTV2_XptDualLinkIn3DSInput
@ NTV2_XptDualLinkIn3DSInput
Definition: ntv2enums.h:2816
kRegHDMIV2VerticalMeasurementsField0
@ kRegHDMIV2VerticalMeasurementsField0
Definition: ntv2publicinterface.h:537
kRegXptSelectGroup32
@ kRegXptSelectGroup32
Definition: ntv2publicinterface.h:702
kRegHDMIHDRControl
@ kRegHDMIHDRControl
Definition: ntv2publicinterface.h:489
NTV2DeviceCanDo12GSDI
bool NTV2DeviceCanDo12GSDI(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:393
kVRegTxcSfp1RemotePort3
@ kVRegTxcSfp1RemotePort3
Definition: ntv2virtualregisters.h:400
kRegSDIOut2VPIDB
@ kRegSDIOut2VPIDB
Definition: ntv2publicinterface.h:378
NTV2_XptMixer4BGKeyInput
@ NTV2_XptMixer4BGKeyInput
Definition: ntv2enums.h:2847
kRegCh2OutputFrame
@ kRegCh2OutputFrame
Definition: ntv2publicinterface.h:127
kRegCh7Control
@ kRegCh7Control
Definition: ntv2publicinterface.h:563
kVRegHDMIInAviInfo2
@ kVRegHDMIInAviInfo2
Definition: ntv2virtualregisters.h:617
kVRegNTV2VPIDTransferCharacteristics7
@ kVRegNTV2VPIDTransferCharacteristics7
Definition: ntv2virtualregisters.h:524
NTV2_XptMixer3FGVidInput
@ NTV2_XptMixer3FGVidInput
Definition: ntv2enums.h:2846
kRegMaskLUTSelect
@ kRegMaskLUTSelect
Definition: ntv2publicinterface.h:1447
kRegCh8Control
@ kRegCh8Control
Definition: ntv2publicinterface.h:568
regAncInsPayloadIDControl
@ regAncInsPayloadIDControl
Definition: ntv2publicinterface.h:5394
regNTV4FS_RasterOffsetBlue
@ regNTV4FS_RasterOffsetBlue
Definition: ntv2registerexpert.cpp:74
kRegCS6Coefficients1_2
@ kRegCS6Coefficients1_2
Definition: ntv2publicinterface.h:646
kLHIRegMaskHDMIOutFPS
@ kLHIRegMaskHDMIOutFPS
Definition: ntv2publicinterface.h:1598
REiNOTE
#define REiNOTE(__x__)
Definition: ntv2registerexpert.cpp:38
kVRegETTDiagLastSerialTimestamp
@ kVRegETTDiagLastSerialTimestamp
Definition: ntv2virtualregisters.h:250
NTV2_XptHDMIOutInput
@ NTV2_XptHDMIOutInput
Definition: ntv2enums.h:2851
kRegXptSelectGroup25
@ kRegXptSelectGroup25
Definition: ntv2publicinterface.h:578
kRegXptSelectGroup13
@ kRegXptSelectGroup13
Definition: ntv2publicinterface.h:404
kVRegServicesForceInit
@ kVRegServicesForceInit
Definition: ntv2virtualregisters.h:494
kRegFlatMatteValue
@ kRegFlatMatteValue
Definition: ntv2publicinterface.h:133
kVRegDmaHardwareRateC2H4
@ kVRegDmaHardwareRateC2H4
Definition: ntv2virtualregisters.h:606
kRegShiftInputStatusFPS
@ kRegShiftInputStatusFPS
Definition: ntv2publicinterface.h:2715
regAncExtIgnorePacketReg_13_14_15_16
@ regAncExtIgnorePacketReg_13_14_15_16
Definition: ntv2publicinterface.h:5365
NTV2_Xpt425Mux1AInput
@ NTV2_Xpt425Mux1AInput
Definition: ntv2enums.h:2860
kVRegHdrMasterLumMaxCh1
@ kVRegHdrMasterLumMaxCh1
Definition: ntv2virtualregisters.h:547
kRegShiftHDRStaticMetadataDescriptorID
@ kRegShiftHDRStaticMetadataDescriptorID
Definition: ntv2publicinterface.h:3283
kVRegHDMIInDrmBluePrimary1
@ kVRegHDMIInDrmBluePrimary1
Definition: ntv2virtualregisters.h:612
kVRegRxcSfp2DestIp2
@ kVRegRxcSfp2DestIp2
Definition: ntv2virtualregisters.h:390
gLivingInstances
static uint32_t gLivingInstances(0)
kVRegSyncChannels
@ kVRegSyncChannels
Definition: ntv2virtualregisters.h:90
kRegCMW14835Out
@ kRegCMW14835Out
Definition: ntv2publicinterface.h:1099
kVRegTimeStampLastOutput3VerticalLo
@ kVRegTimeStampLastOutput3VerticalLo
Definition: ntv2virtualregisters.h:284
kVRegLastAJA
@ kVRegLastAJA
The last AJA virtual register slot.
Definition: ntv2virtualregisters.h:741
kRegXptSelectGroup22
@ kRegXptSelectGroup22
Definition: ntv2publicinterface.h:574
kRegShiftHDMIHDRWhitePointY
@ kRegShiftHDMIHDRWhitePointY
Definition: ntv2publicinterface.h:3273
kVReg4kOutputTransportSelection
@ kVReg4kOutputTransportSelection
Definition: ntv2virtualregisters.h:341
kRegClass_Virtual
#define kRegClass_Virtual
Definition: ntv2registerexpert.h:70
kRegEnhancedCSC1CoeffB2
@ kRegEnhancedCSC1CoeffB2
Definition: ntv2publicinterface.h:880
kVRegHdrBlueYCh1
@ kVRegHdrBlueYCh1
Definition: ntv2virtualregisters.h:542
kRegMaskAudioMixerChannelSelect
@ kRegMaskAudioMixerChannelSelect
Definition: ntv2publicinterface.h:2226
NTV2_XptDualLinkOut7Input
@ NTV2_XptDualLinkOut7Input
Definition: ntv2enums.h:2833
regAuxExtPacketMask0
@ regAuxExtPacketMask0
Definition: ntv2publicinterface.h:5466
kRegEnhancedCSC1OutOffsetC
@ kRegEnhancedCSC1OutOffsetC
Definition: ntv2publicinterface.h:885
kRegXptSelectGroup33
@ kRegXptSelectGroup33
Definition: ntv2publicinterface.h:703
kRegHDMIHDRWhitePoint
@ kRegHDMIHDRWhitePoint
Definition: ntv2publicinterface.h:486
kVRegRxcSfp1SourceIp1
@ kVRegRxcSfp1SourceIp1
Definition: ntv2virtualregisters.h:367
kVRegAudioMonitorChannelSelect
@ kVRegAudioMonitorChannelSelect
Definition: ntv2virtualregisters.h:469
kRegLTC6EmbeddedBits0_31
@ kRegLTC6EmbeddedBits0_31
Definition: ntv2publicinterface.h:594
kVRegProcAmpStandardDefHue
@ kVRegProcAmpStandardDefHue
Definition: ntv2virtualregisters.h:201
kRegMaskPWMFanTachPeriodStatus
@ kRegMaskPWMFanTachPeriodStatus
Definition: ntv2publicinterface.h:2294
kVRegTxc_2EncodeAudio1Pid1
@ kVRegTxc_2EncodeAudio1Pid1
Definition: ntv2virtualregisters.h:438
kRegXptSelectGroup6
@ kRegXptSelectGroup6
Definition: ntv2publicinterface.h:275
kRegCS3Coefficients9_10
@ kRegCS3Coefficients9_10
Definition: ntv2publicinterface.h:437
NTV2BitfileHeaderParser::GetDesignID
static ULWord GetDesignID(const ULWord userID)
Definition: ntv2bitfile.h:54
kRegHDMIV2i2c2Control
@ kRegHDMIV2i2c2Control
Definition: ntv2publicinterface.h:539
kVRegRxc_2DecodeAudioNumber1
@ kVRegRxc_2DecodeAudioNumber1
Definition: ntv2virtualregisters.h:421
kVRegHDMIOutHDRGreenPrimary4
@ kVRegHDMIOutHDRGreenPrimary4
Definition: ntv2virtualregisters.h:673
kRegAud5Delay
@ kRegAud5Delay
Definition: ntv2publicinterface.h:686
kRegMaskChannelDisable
@ kRegMaskChannelDisable
Definition: ntv2publicinterface.h:1309
regAncExtField1Status
@ regAncExtField1Status
Definition: ntv2publicinterface.h:5356
kRegRXSDI8Status
@ kRegRXSDI8Status
Definition: ntv2publicinterface.h:783
kRegOutputTimingControlch6
@ kRegOutputTimingControlch6
Definition: ntv2publicinterface.h:672
kRegRP188InOut3Bits32_63_2
@ kRegRP188InOut3Bits32_63_2
Definition: ntv2publicinterface.h:348
kRegShiftInputStatusStd
@ kRegShiftInputStatusStd
Definition: ntv2publicinterface.h:2713
RegisterExpert::PrintLabelValuePairs
static ostream & PrintLabelValuePairs(ostream &oss, const AJALabelValuePairs &inLabelValuePairs)
Definition: ntv2registerexpert.cpp:1815
NTV2DeviceGetNumHDMIVideoInputs
UWord NTV2DeviceGetNumHDMIVideoInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11711
kVRegChannelCrosspointFirst
@ kVRegChannelCrosspointFirst
Definition: ntv2virtualregisters.h:321
kVReg2022_7NetworkPathDiff
@ kVReg2022_7NetworkPathDiff
Definition: ntv2virtualregisters.h:453
CNTV2RegisterExpert::GetRegistersForDevice
static NTV2RegNumSet GetRegistersForDevice(const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude=0)
Definition: ntv2registerexpert.cpp:4811
kRegAud4Delay
@ kRegAud4Delay
Definition: ntv2publicinterface.h:450
kVRegUseProgressive
@ kVRegUseProgressive
Definition: ntv2virtualregisters.h:299
NTV2FrameGeometryToString
std::string NTV2FrameGeometryToString(const NTV2FrameGeometry inValue, const bool inForRetailDisplay=false)
defined(NTV2_DEPRECATE_17_6)
Definition: ntv2utils.cpp:7305
sNTV4FrameStoreRegNames
static const std::string sNTV4FrameStoreRegNames[]
Definition: ntv2registerexpert.cpp:82
regAncInsFrameLines
@ regAncInsFrameLines
Definition: ntv2publicinterface.h:5392
kRegAud1OutputLastAddr
@ kRegAud1OutputLastAddr
Definition: ntv2publicinterface.h:147
kVRegHDMIOutHDRWhitePoint3
@ kVRegHDMIOutHDRWhitePoint3
Definition: ntv2virtualregisters.h:664
kVRegDmaSerialize
@ kVRegDmaSerialize
Definition: ntv2virtualregisters.h:88
kRegRP188InOut3DBB
@ kRegRP188InOut3DBB
Definition: ntv2publicinterface.h:409
kRegEnhancedCSC1CoeffA1
@ kRegEnhancedCSC1CoeffA1
Definition: ntv2publicinterface.h:876
kRegAud7Delay
@ kRegAud7Delay
Definition: ntv2publicinterface.h:688
kRegMaskAud6PlayCapMode
@ kRegMaskAud6PlayCapMode
Definition: ntv2publicinterface.h:1261
kVRegUserInTransfer
@ kVRegUserInTransfer
Definition: ntv2virtualregisters.h:556
kVRegProcAmpHighDefSaturationCb
@ kVRegProcAmpHighDefSaturationCb
Definition: ntv2virtualregisters.h:209
kVRegTxcSfp2LocalPort3
@ kVRegTxcSfp2LocalPort3
Definition: ntv2virtualregisters.h:401
kVRegNTV2VPIDColorimetry5
@ kVRegNTV2VPIDColorimetry5
Definition: ntv2virtualregisters.h:517
kRegMaskHDMIInV2VideoStd
@ kRegMaskHDMIInV2VideoStd
Definition: ntv2publicinterface.h:1619
kRegBoardID
@ kRegBoardID
Definition: ntv2publicinterface.h:171
kRegMixer1Coefficient
@ kRegMixer1Coefficient
Definition: ntv2publicinterface.h:131
kRegMaskBOBGPIOut2Data
@ kRegMaskBOBGPIOut2Data
Definition: ntv2publicinterface.h:2312
kK2RegMaskConverterInRate
@ kK2RegMaskConverterInRate
Definition: ntv2publicinterface.h:1697
NTV2_XptSDIOut4InputDS2
@ NTV2_XptSDIOut4InputDS2
Definition: ntv2enums.h:2802
kRegMaskLED
@ kRegMaskLED
Definition: ntv2publicinterface.h:1242
kRegAudioMixerAux1GainCh2
@ kRegAudioMixerAux1GainCh2
Definition: ntv2publicinterface.h:818
kVRegHDMIOutProtocolMode
@ kVRegHDMIOutProtocolMode
Definition: ntv2virtualregisters.h:141
kRegRP188InOut6Bits32_63_2
@ kRegRP188InOut6Bits32_63_2
Definition: ntv2publicinterface.h:354
kVRegRxcSfp2Vlan2
@ kVRegRxcSfp2Vlan2
Definition: ntv2virtualregisters.h:393
kRegXptSelectGroup14
@ kRegXptSelectGroup14
Definition: ntv2publicinterface.h:405
kRegDMA4HostAddrHigh
@ kRegDMA4HostAddrHigh
Definition: ntv2publicinterface.h:231
kVRegHDMIInputControl2
@ kVRegHDMIInputControl2
Definition: ntv2virtualregisters.h:647
regAncInsRtpSSRC
@ regAncInsRtpSSRC
Definition: ntv2publicinterface.h:5402
kRegShiftAudioMixerOutputChannelsMute
@ kRegShiftAudioMixerOutputChannelsMute
Definition: ntv2publicinterface.h:3289
kRegCS8Coefficients9_10
@ kRegCS8Coefficients9_10
Definition: ntv2publicinterface.h:662
kVRegRxcSfp2RxMatch1
@ kVRegRxcSfp2RxMatch1
Definition: ntv2virtualregisters.h:372
kRegMaskBOBGPIIn2Data
@ kRegMaskBOBGPIIn2Data
Definition: ntv2publicinterface.h:2302
kRegEnhancedCSC1KeyClipOffset
@ kRegEnhancedCSC1KeyClipOffset
Definition: ntv2publicinterface.h:887
kVRegSubnetEth1
@ kVRegSubnetEth1
Definition: ntv2virtualregisters.h:362
kRegRP188InOut2Bits0_31
@ kRegRP188InOut2Bits0_31
Definition: ntv2publicinterface.h:186
kRegCS5Coefficients9_10
@ kRegCS5Coefficients9_10
Definition: ntv2publicinterface.h:510
kRegCh6OutputFrame
@ kRegCh6OutputFrame
Definition: ntv2publicinterface.h:559
kVRegSubnetEth0
@ kVRegSubnetEth0
Definition: ntv2virtualregisters.h:358
kVRegUseThermostat
@ kVRegUseThermostat
Definition: ntv2virtualregisters.h:343
NTV2DeviceHasNTV4FrameStores
bool NTV2DeviceHasNTV4FrameStores(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7503
kVRegTimeStampLastOutputVerticalLo
@ kVRegTimeStampLastOutputVerticalLo
Definition: ntv2virtualregisters.h:79
kVRegNTV2VPIDRGBRange4
@ kVRegNTV2VPIDRGBRange4
Definition: ntv2virtualregisters.h:579
kVRegProcAmpEndStandardDefRange
@ kVRegProcAmpEndStandardDefRange
Definition: ntv2virtualregisters.h:204
kVRegHDMIOutControl2
@ kVRegHDMIOutControl2
Definition: ntv2virtualregisters.h:645
kRegCS5Coefficients3_4
@ kRegCS5Coefficients3_4
Definition: ntv2publicinterface.h:507
kRegMRQ3Control
@ kRegMRQ3Control
Definition: ntv2publicinterface.h:1052
kVRegHdrInGreenXCh1
@ kVRegHdrInGreenXCh1
Definition: ntv2virtualregisters.h:562
NTV2_XptDualLinkIn2DSInput
@ NTV2_XptDualLinkIn2DSInput
Definition: ntv2enums.h:2814
kVRegChannel2UserBufferLevel
@ kVRegChannel2UserBufferLevel
Definition: ntv2virtualregisters.h:218
kRegClass_HDR
#define kRegClass_HDR
Definition: ntv2registerexpert.h:55
NTV2_XptMixer2BGKeyInput
@ NTV2_XptMixer2BGKeyInput
Definition: ntv2enums.h:2839
kRegClass_Info
#define kRegClass_Info
Definition: ntv2registerexpert.h:57
kVRegAudioCapMixerSourceAux2Enable
@ kVRegAudioCapMixerSourceAux2Enable
Definition: ntv2virtualregisters.h:479
kRegRP188InOut1Bits0_31
@ kRegRP188InOut1Bits0_31
Definition: ntv2publicinterface.h:151
kVRegHdrInRedYCh1
@ kVRegHdrInRedYCh1
Definition: ntv2virtualregisters.h:567
kRegDMA2XferCount
@ kRegDMA2XferCount
Definition: ntv2publicinterface.h:159
kRegSDIIn6VPIDB
@ kRegSDIIn6VPIDB
Definition: ntv2publicinterface.h:588
kRegRXSDI4Status
@ kRegRXSDI4Status
Definition: ntv2publicinterface.h:747
kRegAudioMixerAux1InputLevels
@ kRegAudioMixerAux1InputLevels
Definition: ntv2publicinterface.h:823
kRegRP188InOut7Bits32_63
@ kRegRP188InOut7Bits32_63
Definition: ntv2publicinterface.h:602
kRegShiftHDMIHDRGreenPrimaryX
@ kRegShiftHDMIHDRGreenPrimaryX
Definition: ntv2publicinterface.h:3266
kVRegDSKMode
@ kVRegDSKMode
Definition: ntv2virtualregisters.h:118
kRegInvalidValidXptROMRegister
@ kRegInvalidValidXptROMRegister
Definition: ntv2publicinterface.h:866
kVRegAnalogOutputSelect
@ kVRegAnalogOutputSelect
Definition: ntv2virtualregisters.h:46
kRegMaskLUT5Select
@ kRegMaskLUT5Select
Definition: ntv2publicinterface.h:1446
kVRegVANCMode
@ kVRegVANCMode
Definition: ntv2virtualregisters.h:115
kVRegIpConfigStreamRefresh
@ kVRegIpConfigStreamRefresh
Definition: ntv2virtualregisters.h:189
kVRegChannel1UserBufferLevel
@ kVRegChannel1UserBufferLevel
Definition: ntv2virtualregisters.h:217
kVRegTxc_2EncodeUllMode1
@ kVRegTxc_2EncodeUllMode1
Definition: ntv2virtualregisters.h:429
NTV2_XptMixer2FGKeyInput
@ NTV2_XptMixer2FGKeyInput
Definition: ntv2enums.h:2841
kRegShiftHDMISampling
@ kRegShiftHDMISampling
Definition: ntv2publicinterface.h:2691
kVRegDigitalOutput1Select
@ kVRegDigitalOutput1Select
Definition: ntv2virtualregisters.h:44
kRegCS3Coefficients5_6
@ kRegCS3Coefficients5_6
Definition: ntv2publicinterface.h:435
NTV2_XptLUT7Input
@ NTV2_XptLUT7Input
Definition: ntv2enums.h:2789
NTV2_XptSDIOut3InputDS2
@ NTV2_XptSDIOut3InputDS2
Definition: ntv2enums.h:2800
NTV2StringSet
std::set< std::string > NTV2StringSet
Definition: ntv2utils.h:1158
kVRegHDMIOutHDRGreenPrimary3
@ kVRegHDMIOutHDRGreenPrimary3
Definition: ntv2virtualregisters.h:661
kVRegHDMIOutStatus1
@ kVRegHDMIOutStatus1
Definition: ntv2virtualregisters.h:626
kRegDMA2NextDesc
@ kRegDMA2NextDesc
Definition: ntv2publicinterface.h:160
kRegCh5InputFrame
@ kRegCh5InputFrame
Definition: ntv2publicinterface.h:555
kRegMask425FB56
@ kRegMask425FB56
Definition: ntv2publicinterface.h:1274
kRegSDIIn7VPIDA
@ kRegSDIIn7VPIDA
Definition: ntv2publicinterface.h:597
kVRegDmaTransferRateH2C1
@ kVRegDmaTransferRateH2C1
Definition: ntv2virtualregisters.h:595
kRegAud2Delay
@ kRegAud2Delay
Definition: ntv2publicinterface.h:210
kVRegResetCycleCount
@ kVRegResetCycleCount
Definition: ntv2virtualregisters.h:298
regNTV4FS_Status
@ regNTV4FS_Status
Definition: ntv2registerexpert.cpp:69
kVRegHdrInColorimetryCh1
@ kVRegHdrInColorimetryCh1
Definition: ntv2virtualregisters.h:559
kRegClass_NULL
#define kRegClass_NULL
Definition: ntv2registerexpert.h:38
kRegMaskHDMIHDRBluePrimaryY
@ kRegMaskHDMIHDRBluePrimaryY
Definition: ntv2publicinterface.h:2207
kRegColorCorrectionLUTOddShift
#define kRegColorCorrectionLUTOddShift
Definition: ntv2publicinterface.h:4294
kRegCS6Coefficients3_4
@ kRegCS6Coefficients3_4
Definition: ntv2publicinterface.h:647
kVRegHDMIOutAudioChannels
@ kVRegHDMIOutAudioChannels
Definition: ntv2virtualregisters.h:465
kVRegAcquireReferenceCounter
@ kVRegAcquireReferenceCounter
Definition: ntv2virtualregisters.h:312
kRegHDMIV2HorizontalMeasurements
@ kRegHDMIV2HorizontalMeasurements
Definition: ntv2publicinterface.h:534
kRegMaskIsDNXIV
@ kRegMaskIsDNXIV
Definition: ntv2publicinterface.h:1271
kVRegAudioMixerSourceMainEnable
@ kVRegAudioMixerSourceMainEnable
Definition: ntv2virtualregisters.h:471
kVRegApplicationPID
@ kVRegApplicationPID
Definition: ntv2virtualregisters.h:184
kRegMaskAud8PlayCapMode
@ kRegMaskAud8PlayCapMode
Definition: ntv2publicinterface.h:1263
NTV2_XptCSC7VidInput
@ NTV2_XptCSC7VidInput
Definition: ntv2enums.h:2779
kRegOutputTimingControlch7
@ kRegOutputTimingControlch7
Definition: ntv2publicinterface.h:673
kRegInput78Status
@ kRegInput78Status
Definition: ntv2publicinterface.h:644
NTV2DeviceCanDoEnhancedCSC
bool NTV2DeviceCanDoEnhancedCSC(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2743
kRegMaskHDMIHDREnable
@ kRegMaskHDMIHDREnable
Definition: ntv2publicinterface.h:2219
kVRegHDMIOutHDRRedPrimary1
@ kVRegHDMIOutHDRRedPrimary1
Definition: ntv2virtualregisters.h:639
kVRegIPAddrEth1
@ kVRegIPAddrEth1
Definition: ntv2virtualregisters.h:361
kVRegInput2UserBufferLevel
@ kVRegInput2UserBufferLevel
Definition: ntv2virtualregisters.h:220
kRegShiftCCOutputBankSelect
@ kRegShiftCCOutputBankSelect
Definition: ntv2publicinterface.h:2534
NTV2Channel
NTV2Channel
These enum values are mostly used to identify a specific widget_framestore. They're also commonly use...
Definition: ntv2enums.h:1353
kRegShiftAudioMixerChannelSelect
@ kRegShiftAudioMixerChannelSelect
Definition: ntv2publicinterface.h:3288
kRegAudioMixerAux1GainCh1
@ kRegAudioMixerAux1GainCh1
Definition: ntv2publicinterface.h:814
kVRegAnalogInStandard
@ kVRegAnalogInStandard
Definition: ntv2virtualregisters.h:180
NTV2_XptCSC5KeyInput
@ NTV2_XptCSC5KeyInput
Definition: ntv2enums.h:2776
kRegNumRegisters
@ kRegNumRegisters
Definition: ntv2publicinterface.h:709
kVRegNTV2VPIDLuminance1
@ kVRegNTV2VPIDLuminance1
Definition: ntv2virtualregisters.h:499
kVRegTimeCodeIn8Delay
@ kVRegTimeCodeIn8Delay
Definition: ntv2virtualregisters.h:107
kVRegNumberAudioMappingRegisters
@ kVRegNumberAudioMappingRegisters
Definition: ntv2virtualregisters.h:86
kRegMaskHDMIHDRRedPrimaryX
@ kRegMaskHDMIHDRRedPrimaryX
Definition: ntv2publicinterface.h:2208
regAncExtIgnorePacketReg_9_10_11_12
@ regAncExtIgnorePacketReg_9_10_11_12
Definition: ntv2publicinterface.h:5364
kRegCS3Coefficients7_8
@ kRegCS3Coefficients7_8
Definition: ntv2publicinterface.h:436
kRegCS5Coefficients7_8
@ kRegCS5Coefficients7_8
Definition: ntv2publicinterface.h:509
kVRegFanControl
@ kVRegFanControl
Definition: ntv2virtualregisters.h:59
NTV2_XptDualLinkIn1Input
@ NTV2_XptDualLinkIn1Input
Definition: ntv2enums.h:2811
AJARefPtr
I am a reference-counted pointer template class. I am intended to be a proxy for an underlying object...
Definition: ajarefptr.h:89
kVRegBitFileDownload
@ kVRegBitFileDownload
Definition: ntv2virtualregisters.h:62
NTV2_XptSDIOut5InputDS2
@ NTV2_XptSDIOut5InputDS2
Definition: ntv2enums.h:2804
kRegLTC5EmbeddedBits0_31
@ kRegLTC5EmbeddedBits0_31
Definition: ntv2publicinterface.h:501
aja::join
std::string join(const std::vector< std::string > &parts, const std::string &delim)
Definition: common.cpp:468
kRegAud6InputLastAddr
@ kRegAud6InputLastAddr
Definition: ntv2publicinterface.h:627
kK2RegMaskConverterInStandard
@ kK2RegMaskConverterInStandard
Definition: ntv2publicinterface.h:1696
kVRegFlashState
@ kVRegFlashState
Definition: ntv2virtualregisters.h:303
kVRegHDMIInDrmRedPrimary1
@ kVRegHDMIInDrmRedPrimary1
Definition: ntv2virtualregisters.h:613
kVRegTimelapseEnable
@ kVRegTimelapseEnable
Definition: ntv2virtualregisters.h:173
kRegLTC2EmbeddedBits0_31
@ kRegLTC2EmbeddedBits0_31
Definition: ntv2publicinterface.h:393
sShifts
static const ULWord sShifts[]
Definition: ntv2regroute.cpp:27
VIRTUALREG_START
#define VIRTUALREG_START
Definition: ntv2virtualregisters.h:12
kRegShiftAudioMixerAux2InputEnable
@ kRegShiftAudioMixerAux2InputEnable
Definition: ntv2publicinterface.h:3308
NTV2_ASSERT
#define NTV2_ASSERT(_expr_)
Definition: ajatypes.h:529
kRegBOBGPIInData
@ kRegBOBGPIInData
Definition: ntv2publicinterface.h:1077
kVRegTimelapseCaptureValue
@ kVRegTimelapseCaptureValue
Definition: ntv2virtualregisters.h:174
gChlClasses
static const string gChlClasses[]
Definition: ntv2registerexpert.cpp:46
kVRegHdrInGreenYCh1
@ kVRegHdrInGreenYCh1
Definition: ntv2virtualregisters.h:563
NTV2_XptCSC4VidInput
@ NTV2_XptCSC4VidInput
Definition: ntv2enums.h:2773
kRegAud8OutputLastAddr
@ kRegAud8OutputLastAddr
Definition: ntv2publicinterface.h:636
kRegSDIWatchdogKick1
@ kRegSDIWatchdogKick1
Definition: ntv2publicinterface.h:459
kRegCh3PCIAccessFrame
@ kRegCh3PCIAccessFrame
Definition: ntv2publicinterface.h:430
kRegCS2Coefficients9_10
@ kRegCS2Coefficients9_10
Definition: ntv2publicinterface.h:287
kVRegHDMIOutStatus3
@ kVRegHDMIOutStatus3
Definition: ntv2virtualregisters.h:660
RegisterExpert::Print
ostream & Print(ostream &inOutStream) const
Definition: ntv2registerexpert.cpp:2150
kRegShiftFrameRate
@ kRegShiftFrameRate
Definition: ntv2publicinterface.h:2328
kRegMixer4Coefficient
@ kRegMixer4Coefficient
Definition: ntv2publicinterface.h:681
kVRegUserTransfer
@ kVRegUserTransfer
Definition: ntv2virtualregisters.h:533
NTV2_FIRST_INPUT_CROSSPOINT
@ NTV2_FIRST_INPUT_CROSSPOINT
Originally 0x01. Changed to 0x00 in SDK 17.1.
Definition: ntv2enums.h:2750
kVRegHdrInRedXCh1
@ kVRegHdrInRedXCh1
Definition: ntv2virtualregisters.h:566
kRegXptSelectGroup5
@ kRegXptSelectGroup5
Definition: ntv2publicinterface.h:274
kRegRP188InOut6Bits0_31
@ kRegRP188InOut6Bits0_31
Definition: ntv2publicinterface.h:591
kVRegTxc_2EncodeBitDepth2
@ kVRegTxc_2EncodeBitDepth2
Definition: ntv2virtualregisters.h:442
kRegClass_LUT
#define kRegClass_LUT
Definition: ntv2registerexpert.h:60
NTV2DownConvertModeToString
std::string NTV2DownConvertModeToString(const NTV2DownConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6594
kRegAudioMixerMutes
@ kRegAudioMixerMutes
Definition: ntv2publicinterface.h:817
kRegEnhancedCSC1InOffset2
@ kRegEnhancedCSC1InOffset2
Definition: ntv2publicinterface.h:874
kRegAud8Control
@ kRegAud8Control
Definition: ntv2publicinterface.h:634
DEVICE_ID_IOX3
@ DEVICE_ID_IOX3
See Io X3.
Definition: ntv2enums.h:41
kRegMaskHDMIOutAudioSource
@ kRegMaskHDMIOutAudioSource
Definition: ntv2publicinterface.h:1972
kVRegAnalogInputType
@ kVRegAnalogInputType
Definition: ntv2virtualregisters.h:139
NTV2_XptMixer3BGKeyInput
@ NTV2_XptMixer3BGKeyInput
Definition: ntv2enums.h:2843
kVRegAcquireLinuxReferenceCount
@ kVRegAcquireLinuxReferenceCount
Definition: ntv2virtualregisters.h:263
kRegColorCorrectionLUTEvenShift
#define kRegColorCorrectionLUTEvenShift
Definition: ntv2publicinterface.h:4295
NTV2_XptMultiLinkOut1Input
@ NTV2_XptMultiLinkOut1Input
New in SDK 16.0.
Definition: ntv2enums.h:2791
kK2RegMaskEnableConverter
@ kK2RegMaskEnableConverter
Definition: ntv2publicinterface.h:1702
kRegMaskHDMIHDRGreenPrimaryX
@ kRegMaskHDMIHDRGreenPrimaryX
Definition: ntv2publicinterface.h:2204
kRegMaskHDMIHDRMaxMasteringLuminance
@ kRegMaskHDMIHDRMaxMasteringLuminance
Definition: ntv2publicinterface.h:2212
kVRegTimeStampLastInput8VerticalLo
@ kVRegTimeStampLastInput8VerticalLo
Definition: ntv2virtualregisters.h:278
kVRegSerialSuspended
@ kVRegSerialSuspended
Definition: ntv2virtualregisters.h:248
kK2RegMaskUpConvertMode
@ kK2RegMaskUpConvertMode
Definition: ntv2publicinterface.h:1694
kVRegNTV2VPIDColorimetry7
@ kVRegNTV2VPIDColorimetry7
Definition: ntv2virtualregisters.h:525
regNTV4FS_RasterVideoFill_YCb_GB
@ regNTV4FS_RasterVideoFill_YCb_GB
Definition: ntv2registerexpert.cpp:66
NTV2_XptDualLinkIn8Input
@ NTV2_XptDualLinkIn8Input
Definition: ntv2enums.h:2825
kRegMRSupport
@ kRegMRSupport
Definition: ntv2publicinterface.h:1055
kVRegSDIInput2Stereo3DMode
@ kVRegSDIInput2Stereo3DMode
Definition: ntv2virtualregisters.h:132
sNull
static const string sNull
Definition: ntv2registerexpert.cpp:49
kVRegAudioMixerSourceAux2Gain
@ kVRegAudioMixerSourceAux2Gain
Definition: ntv2virtualregisters.h:476
NTV2_XptDualLinkIn5DSInput
@ NTV2_XptDualLinkIn5DSInput
Definition: ntv2enums.h:2820
kVRegLatencyTimerValue
@ kVRegLatencyTimerValue
Definition: ntv2virtualregisters.h:245
kVRegProcAmpHighDefContrast
@ kVRegProcAmpHighDefContrast
Definition: ntv2virtualregisters.h:208
kRegShiftHDMIHDRMaxContentLightLevel
@ kRegShiftHDMIHDRMaxContentLightLevel
Definition: ntv2publicinterface.h:3276
kVRegSDIOutput2ColorSpaceMode
@ kVRegSDIOutput2ColorSpaceMode
Definition: ntv2virtualregisters.h:171
kRegCS6Coefficients5_6
@ kRegCS6Coefficients5_6
Definition: ntv2publicinterface.h:648
kVRegHdmiHdrOutChanged
@ kVRegHdmiHdrOutChanged
Definition: ntv2virtualregisters.h:488
kVRegNTV2VPIDColorimetry4
@ kVRegNTV2VPIDColorimetry4
Definition: ntv2virtualregisters.h:513
kRegDMA4LocalAddr
@ kRegDMA4LocalAddr
Definition: ntv2publicinterface.h:166
kVRegNTV2VPIDTransferCharacteristics3
@ kVRegNTV2VPIDTransferCharacteristics3
Definition: ntv2virtualregisters.h:508
regAuxExtField1EndAddress
@ regAuxExtField1EndAddress
Definition: ntv2publicinterface.h:5456
RegisterExpert::DisposeInstance
static bool DisposeInstance(void)
Definition: ntv2registerexpert.cpp:4722
kRegRXSDI5Status
@ kRegRXSDI5Status
Definition: ntv2publicinterface.h:756
kRegAudDetect2
@ kRegAudDetect2
Definition: ntv2publicinterface.h:423
NTV2_XptFrameBuffer3DS2Input
@ NTV2_XptFrameBuffer3DS2Input
Definition: ntv2enums.h:2756
kColorCorrectionLUTOffset_Green
#define kColorCorrectionLUTOffset_Green
Definition: ntv2publicinterface.h:4300
kVRegNTV2VPIDTransferCharacteristics8
@ kVRegNTV2VPIDTransferCharacteristics8
Definition: ntv2virtualregisters.h:528
kRegHDMIHDRGreenPrimary
@ kRegHDMIHDRGreenPrimary
Definition: ntv2publicinterface.h:483
kRegHDMIV2HActive
@ kRegHDMIV2HActive
Definition: ntv2publicinterface.h:528
kRegOutputTimingControlch3
@ kRegOutputTimingControlch3
Definition: ntv2publicinterface.h:669
kRegSDIOut3VPIDB
@ kRegSDIOut3VPIDB
Definition: ntv2publicinterface.h:413
kRegMaskAnalogIOControl_58
@ kRegMaskAnalogIOControl_58
Definition: ntv2publicinterface.h:1286
NTV2_XptLUT3Input
@ NTV2_XptLUT3Input
Definition: ntv2enums.h:2785
kRegAud1Counter
@ kRegAud1Counter
Definition: ntv2publicinterface.h:149
kVRegDriverType
@ kVRegDriverType
Definition: ntv2virtualregisters.h:39
regAncExtField1EndAddress
@ regAncExtField1EndAddress
Definition: ntv2publicinterface.h:5351
regAncExtTotalStatus
@ regAncExtTotalStatus
Definition: ntv2publicinterface.h:5355
kVRegAudioCapMixerSourceAux2Gain
@ kVRegAudioCapMixerSourceAux2Gain
Definition: ntv2virtualregisters.h:482
kVRegSDIOutput1Stereo3DMode
@ kVRegSDIOutput1Stereo3DMode
Definition: ntv2virtualregisters.h:149
ntv2endian.h
Defines a number of handy byte-swapping macros.
kVRegIsDefaultDevice
@ kVRegIsDefaultDevice
Definition: ntv2virtualregisters.h:167
regNTV4FS_RasterROIFillAlpha
@ regNTV4FS_RasterROIFillAlpha
Definition: ntv2registerexpert.cpp:68
kRegShiftLUT5Select
@ kRegShiftLUT5Select
Definition: ntv2publicinterface.h:2538
kVRegCaptureReferenceSelect
@ kVRegCaptureReferenceSelect
Definition: ntv2virtualregisters.h:123
NTV2DeviceGetLUTVersion
ULWord NTV2DeviceGetLUTVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:9467
kRegMaskAudioMixerPresent
@ kRegMaskAudioMixerPresent
Definition: ntv2publicinterface.h:1270
kVRegHDMIOutStatus2
@ kVRegHDMIOutStatus2
Definition: ntv2virtualregisters.h:648
kRegSDIIn5VPIDA
@ kRegSDIIn5VPIDA
Definition: ntv2publicinterface.h:584
kRegXptSelectGroup30
@ kRegXptSelectGroup30
Definition: ntv2publicinterface.h:575
EnabDisab
#define EnabDisab(__x__)
Definition: ntv2registerexpert.h:28
kRegMaskVidProcBGMatteEnable
@ kRegMaskVidProcBGMatteEnable
Definition: ntv2publicinterface.h:1346
kVRegThermalSamplingRate
@ kVRegThermalSamplingRate
Definition: ntv2virtualregisters.h:344
kRegClass_Channel5
#define kRegClass_Channel5
Definition: ntv2registerexpert.h:48
kRegMaskAudioMixerAux1InputEnable
@ kRegMaskAudioMixerAux1InputEnable
Definition: ntv2publicinterface.h:2245
kRegMaskGeometry
@ kRegMaskGeometry
Definition: ntv2publicinterface.h:1237
kVRegBA1MemorySize
@ kVRegBA1MemorySize
Definition: ntv2virtualregisters.h:258
kRegRP188InOut4Bits0_31
@ kRegRP188InOut4Bits0_31
Definition: ntv2publicinterface.h:415
kK2RegShiftDownConvertMode
@ kK2RegShiftDownConvertMode
Definition: ntv2publicinterface.h:2773
regAuxExtTotalFrameLines
@ regAuxExtTotalFrameLines
Definition: ntv2publicinterface.h:5464
kVRegMacKernelModePingLevel
@ kVRegMacKernelModePingLevel
Definition: ntv2virtualregisters.h:244
kRegSDIIn2VPIDA
@ kRegSDIIn2VPIDA
Definition: ntv2publicinterface.h:379
kVRegHDMIOutHDRLightLevel4
@ kVRegHDMIOutHDRLightLevel4
Definition: ntv2virtualregisters.h:678
kRegXptSelectGroup8
@ kRegXptSelectGroup8
Definition: ntv2publicinterface.h:302
kRegCS2Coefficients5_6
@ kRegCS2Coefficients5_6
Definition: ntv2publicinterface.h:285
kVRegStrictTiming
@ kVRegStrictTiming
Definition: ntv2virtualregisters.h:36
kRegCS4Coefficients9_10
@ kRegCS4Coefficients9_10
Definition: ntv2publicinterface.h:443
ThruDeviceOrBypassed
#define ThruDeviceOrBypassed(__x__)
Definition: ntv2registerexpert.h:34
kVRegDualStreamTransportType
@ kVRegDualStreamTransportType
Definition: ntv2virtualregisters.h:116
kVRegTxcSfp1RemotePort4
@ kVRegTxcSfp1RemotePort4
Definition: ntv2virtualregisters.h:408
kRegLEDSDI1Control
@ kRegLEDSDI1Control
Definition: ntv2publicinterface.h:1089
kRegMaskAud7PlayCapMode
@ kRegMaskAud7PlayCapMode
Definition: ntv2publicinterface.h:1262
sMasks
static const ULWord sMasks[]
Definition: ntv2regroute.cpp:26
kRegMaskSmpte372Enable
@ kRegMaskSmpte372Enable
Definition: ntv2publicinterface.h:1241
kVRegHDMIOutHDRGreenPrimary2
@ kVRegHDMIOutHDRGreenPrimary2
Definition: ntv2virtualregisters.h:649
kRegEnhancedCSC1KeyMode
@ kRegEnhancedCSC1KeyMode
Definition: ntv2publicinterface.h:886
kRegHDMIHDRBluePrimary
@ kRegHDMIHDRBluePrimary
Definition: ntv2publicinterface.h:484
kRegXptSelectGroup34
@ kRegXptSelectGroup34
Definition: ntv2publicinterface.h:704
kRegGlobalControlCh4
@ kRegGlobalControlCh4
Definition: ntv2publicinterface.h:547
kVReg2022_7Enable
@ kVReg2022_7Enable
Definition: ntv2virtualregisters.h:452
CNTV2RegisterExpert::IsRegisterInClass
static bool IsRegisterInClass(const uint32_t inRegNum, const std::string &inClassName)
Definition: ntv2registerexpert.cpp:4776
kRegMaskBOBGPIIn4InterruptControl
@ kRegMaskBOBGPIIn4InterruptControl
Definition: ntv2publicinterface.h:2309
NTV2DeviceID
NTV2DeviceID
Identifies a specific AJA NTV2 device model number. The NTV2DeviceID is actually the PROM part number...
Definition: ntv2enums.h:20
kVRegTimeStampLastInput3VerticalHi
@ kVRegTimeStampLastInput3VerticalHi
Definition: ntv2virtualregisters.h:269
NTV2_Xpt3DLUT1Input
@ NTV2_Xpt3DLUT1Input
New in SDK 16.0.
Definition: ntv2enums.h:2869
regAncExtField1AnalogCFilter
@ regAncExtField1AnalogCFilter
Definition: ntv2publicinterface.h:5371
DEC0N
#define DEC0N(__x__, __n__)
Definition: ntv2publicinterface.h:5771
kVRegNTV2VPIDColorimetry2
@ kVRegNTV2VPIDColorimetry2
Definition: ntv2virtualregisters.h:505
NTV2_Xpt4KDCQ2Input
@ NTV2_Xpt4KDCQ2Input
Definition: ntv2enums.h:2857
kVRegRxcSfp2SourceIp1
@ kVRegRxcSfp2SourceIp1
Definition: ntv2virtualregisters.h:373
kColorCorrectionLUTOffset_Blue
#define kColorCorrectionLUTOffset_Blue
Definition: ntv2publicinterface.h:4301
kVRegSDIInput1FormatSelect
@ kVRegSDIInput1FormatSelect
Definition: ntv2virtualregisters.h:127
kRegMaskRP188ModeCh5
@ kRegMaskRP188ModeCh5
Definition: ntv2publicinterface.h:1278
kRegClass_SDIError
#define kRegClass_SDIError
Definition: ntv2registerexpert.h:65
kVRegRelativeVideoPlaybackDelay
@ kVRegRelativeVideoPlaybackDelay
Definition: ntv2virtualregisters.h:33
kRegMaskBOBAnalogLevelControl
@ kRegMaskBOBAnalogLevelControl
Definition: ntv2publicinterface.h:2317
kRegAud3SourceSelect
@ kRegAud3SourceSelect
Definition: ntv2publicinterface.h:421
kRegMask425FB12
@ kRegMask425FB12
Definition: ntv2publicinterface.h:1272
kRegMaskElectroOpticalTransferFunction
@ kRegMaskElectroOpticalTransferFunction
Definition: ntv2publicinterface.h:2220
kVRegDefaultInput
@ kVRegDefaultInput
Definition: ntv2virtualregisters.h:234
kRegAudioOutputSourceMap
@ kRegAudioOutputSourceMap
Definition: ntv2publicinterface.h:331
kRegClass_Channel2
#define kRegClass_Channel2
Definition: ntv2registerexpert.h:45
NTV2_WIDGET_INVALID
@ NTV2_WIDGET_INVALID
Definition: ntv2enums.h:3030
regAuxExtField2StartAddress
@ regAuxExtField2StartAddress
Definition: ntv2publicinterface.h:5457
kRegEnhancedCSC1Mode
@ kRegEnhancedCSC1Mode
Definition: ntv2publicinterface.h:872
kRegRP188InOut5DBB
@ kRegRP188InOut5DBB
Definition: ntv2publicinterface.h:497
kRegHDMIV2i2c2Data
@ kRegHDMIV2i2c2Data
Definition: ntv2publicinterface.h:540
NTV2_XptMixer3FGKeyInput
@ NTV2_XptMixer3FGKeyInput
Definition: ntv2enums.h:2845
kRegMaskBOBADAV801DIRLocked
@ kRegMaskBOBADAV801DIRLocked
Definition: ntv2publicinterface.h:2299
regAncExtIgnorePacketReg_5_6_7_8
@ regAncExtIgnorePacketReg_5_6_7_8
Definition: ntv2publicinterface.h:5363
kRegGlobalControlCh7
@ kRegGlobalControlCh7
Definition: ntv2publicinterface.h:550
kRegClass_Interrupt
#define kRegClass_Interrupt
Definition: ntv2registerexpert.h:58
kRegMaskBOBGPIIn1Data
@ kRegMaskBOBGPIIn1Data
Definition: ntv2publicinterface.h:2301
kRegShiftCC5OutputBankSelect
@ kRegShiftCC5OutputBankSelect
Definition: ntv2publicinterface.h:2537
kRegRP188InOut3Bits0_31
@ kRegRP188InOut3Bits0_31
Definition: ntv2publicinterface.h:410
kK2RegMaskDownConvertMode
@ kK2RegMaskDownConvertMode
Definition: ntv2publicinterface.h:1695
kRegMaskPWMFanStatus
@ kRegMaskPWMFanStatus
Definition: ntv2publicinterface.h:2295
regAncExtFieldCutoffLine
@ regAncExtFieldCutoffLine
Definition: ntv2publicinterface.h:5354
NTV2_XptSDIOut7Input
@ NTV2_XptSDIOut7Input
Definition: ntv2enums.h:2807
kVRegTimeStampLastInput7VerticalHi
@ kVRegTimeStampLastInput7VerticalHi
Definition: ntv2virtualregisters.h:277
kVRegTxc_2EncodeAudioChannels1
@ kVRegTxc_2EncodeAudioChannels1
Definition: ntv2virtualregisters.h:433
kRegDMA4XferCount
@ kRegDMA4XferCount
Definition: ntv2publicinterface.h:167
kVRegFlashProgramKey
@ kVRegFlashProgramKey
Definition: ntv2virtualregisters.h:35
kVRegProcAmpStandardDefSaturation
@ kVRegProcAmpStandardDefSaturation
Definition: ntv2virtualregisters.h:200
kVRegHDMIOutHDRBluePrimary4
@ kVRegHDMIOutHDRBluePrimary4
Definition: ntv2virtualregisters.h:674
NTV2_Xpt4KDCQ4Input
@ NTV2_Xpt4KDCQ4Input
Definition: ntv2enums.h:2859
kVRegDmaHardwareRateH2C3
@ kVRegDmaHardwareRateH2C3
Definition: ntv2virtualregisters.h:604
kRegCh8OutputFrame
@ kRegCh8OutputFrame
Definition: ntv2publicinterface.h:569
kRegSDIIn7VPIDB
@ kRegSDIIn7VPIDB
Definition: ntv2publicinterface.h:598
kVRegTxc_2EncodeVideoPid1
@ kVRegTxc_2EncodeVideoPid1
Definition: ntv2virtualregisters.h:436
regNTV4FS_RasterOffsetAlpha
@ regNTV4FS_RasterOffsetAlpha
Definition: ntv2registerexpert.cpp:76
regNTV4FS_FIRST
@ regNTV4FS_FIRST
Definition: ntv2registerexpert.cpp:53
kVRegChannelCrosspointLast
@ kVRegChannelCrosspointLast
Definition: ntv2virtualregisters.h:328
kVRegHDMIInputControl1
@ kVRegHDMIInputControl1
Definition: ntv2virtualregisters.h:635
kRegMaskCC5OutputBankSelect
@ kRegMaskCC5OutputBankSelect
Definition: ntv2publicinterface.h:1445
kRegCS4Coefficients3_4
@ kRegCS4Coefficients3_4
Definition: ntv2publicinterface.h:440
kRegMaskQuadQuadMode
@ kRegMaskQuadQuadMode
Definition: ntv2publicinterface.h:1287
kVRegTxc_2EncodeProgramPid1
@ kVRegTxc_2EncodeProgramPid1
Definition: ntv2virtualregisters.h:435
kVRegHDMIOutColorSpaceModeStatus
@ kVRegHDMIOutColorSpaceModeStatus
Definition: ntv2virtualregisters.h:165
kRegMaskCC4OutputBankSelect
@ kRegMaskCC4OutputBankSelect
Definition: ntv2publicinterface.h:1449
kRegRXSDI1Status
@ kRegRXSDI1Status
Definition: ntv2publicinterface.h:720
kRegAudioMixerAux2GainCh1
@ kRegAudioMixerAux2GainCh1
Definition: ntv2publicinterface.h:815
kVRegTxc_2EncodeProgramPid2
@ kVRegTxc_2EncodeProgramPid2
Definition: ntv2virtualregisters.h:447
kVRegDisableAutoVPID
@ kVRegDisableAutoVPID
Definition: ntv2virtualregisters.h:490
NTV2DeviceGetNumCSCs
UWord NTV2DeviceGetNumCSCs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:10955
kVRegProcAmpSDRegsInitialized
@ kVRegProcAmpSDRegsInitialized
Definition: ntv2virtualregisters.h:197
kVRegTimeCodeCh5Delay
@ kVRegTimeCodeCh5Delay
Definition: ntv2virtualregisters.h:100
kVRegInputChangedCount
@ kVRegInputChangedCount
Definition: ntv2virtualregisters.h:191
NTV2_XptHDMIOutQ3Input
@ NTV2_XptHDMIOutQ3Input
Definition: ntv2enums.h:2854
kVRegRxcSfp1DestIp1
@ kVRegRxcSfp1DestIp1
Definition: ntv2virtualregisters.h:368
kVRegSDIOutput2RGBRange
@ kVRegSDIOutput2RGBRange
Definition: ntv2virtualregisters.h:148
kRegAud7InputLastAddr
@ kRegAud7InputLastAddr
Definition: ntv2publicinterface.h:632
regNTV4FS_InputSourceSelect
@ regNTV4FS_InputSourceSelect
Definition: ntv2registerexpert.cpp:77
kVRegSyncChannel
@ kVRegSyncChannel
Definition: ntv2virtualregisters.h:89
NTV2_XptSDIOut2InputDS2
@ NTV2_XptSDIOut2InputDS2
Definition: ntv2enums.h:2798
kVRegPCILinkWidth
@ kVRegPCILinkWidth
Definition: ntv2virtualregisters.h:630
kRegShiftCC5HostAccessBankSelect
@ kRegShiftCC5HostAccessBankSelect
Definition: ntv2publicinterface.h:2536
kRegDMA3NextDescHigh
@ kRegDMA3NextDescHigh
Definition: ntv2publicinterface.h:230
kRegVidProc3Control
@ kRegVidProc3Control
Definition: ntv2publicinterface.h:676
NTV2_XptFrameBuffer4Input
@ NTV2_XptFrameBuffer4Input
Definition: ntv2enums.h:2757
kRegEnhancedCSC1KeyGain
@ kRegEnhancedCSC1KeyGain
Definition: ntv2publicinterface.h:888
kRegMaskQuadQuadSquaresMode
@ kRegMaskQuadQuadSquaresMode
Definition: ntv2publicinterface.h:1289
kVRegMacUserModePingLevel
@ kVRegMacUserModePingLevel
Definition: ntv2virtualregisters.h:243
kVRegRxcSfp1RxMatch2
@ kVRegRxcSfp1RxMatch2
Definition: ntv2virtualregisters.h:382
kRegHDMIV2HSyncDurationAndBackPorch
@ kRegHDMIV2HSyncDurationAndBackPorch
Definition: ntv2publicinterface.h:527
kVRegRxcSfp2SourceIp2
@ kVRegRxcSfp2SourceIp2
Definition: ntv2virtualregisters.h:389
kVRegTimeStampLastOutput3VerticalHi
@ kVRegTimeStampLastOutput3VerticalHi
Definition: ntv2virtualregisters.h:285
NTV2_XptSDIOut8InputDS2
@ NTV2_XptSDIOut8InputDS2
Definition: ntv2enums.h:2810
NTV2InputXptID
enum NTV2InputCrosspointID NTV2InputXptID
kRegAudioMixerMainOutputLevelsPair0
@ kRegAudioMixerMainOutputLevelsPair0
Definition: ntv2publicinterface.h:834
NTV2_XptFrameBuffer3Input
@ NTV2_XptFrameBuffer3Input
Definition: ntv2enums.h:2755
kRegClass_WriteOnly
#define kRegClass_WriteOnly
Definition: ntv2registerexpert.h:72
NTV2PixelFormat
NTV2FrameBufferFormat NTV2PixelFormat
An alias for NTV2FrameBufferFormat.
Definition: ntv2enums.h:256
kRegMaskCC5HostAccessBankSelect
@ kRegMaskCC5HostAccessBankSelect
Definition: ntv2publicinterface.h:1444
kRegLTC7EmbeddedBits0_31
@ kRegLTC7EmbeddedBits0_31
Definition: ntv2publicinterface.h:604
NTV2_XptDualLinkOut5Input
@ NTV2_XptDualLinkOut5Input
Definition: ntv2enums.h:2831
kRegAud1Delay
@ kRegAud1Delay
Definition: ntv2publicinterface.h:140
kRegXptSelectGroup3
@ kRegXptSelectGroup3
Definition: ntv2publicinterface.h:272
kK2RegMaskIsoConvertMode
@ kK2RegMaskIsoConvertMode
Definition: ntv2publicinterface.h:1700
NTV2_XptSDIOut4Input
@ NTV2_XptSDIOut4Input
Definition: ntv2enums.h:2801
kRegAudioMixerMainOutputLevelsPair6
@ kRegAudioMixerMainOutputLevelsPair6
Definition: ntv2publicinterface.h:840
kRegAud7OutputLastAddr
@ kRegAud7OutputLastAddr
Definition: ntv2publicinterface.h:631
NTV2_XptMixer4BGVidInput
@ NTV2_XptMixer4BGVidInput
Definition: ntv2enums.h:2848
regNTV4FS_LineLengthPitch
@ regNTV4FS_LineLengthPitch
Definition: ntv2registerexpert.cpp:54
kRegXptSelectGroup27
@ kRegXptSelectGroup27
Definition: ntv2publicinterface.h:580
ntv2debug.h
kVRegRGB10Range
@ kVRegRGB10Range
Definition: ntv2virtualregisters.h:57
kRegMaskFramePulseEnable
@ kRegMaskFramePulseEnable
Definition: ntv2publicinterface.h:1291
kRegMaskCCOutputBankSelect
@ kRegMaskCCOutputBankSelect
Definition: ntv2publicinterface.h:1442
NTV2StringSetConstIter
NTV2StringSet::const_iterator NTV2StringSetConstIter
Definition: ntv2utils.h:1159
kRegLTC2AnalogBits32_63
@ kRegLTC2AnalogBits32_63
Definition: ntv2publicinterface.h:396
NTV2_XptCSC1VidInput
@ NTV2_XptCSC1VidInput
Definition: ntv2enums.h:2767
kRegAud8InputLastAddr
@ kRegAud8InputLastAddr
Definition: ntv2publicinterface.h:637
CNTV2RegisterExpert::Allocate
static bool Allocate(void)
Explicitly allocates the Register Expert singleton.
Definition: ntv2registerexpert.cpp:4731
NTV2_Xpt425Mux3AInput
@ NTV2_Xpt425Mux3AInput
Definition: ntv2enums.h:2864
kRegShiftHDMIHDRGreenPrimaryY
@ kRegShiftHDMIHDRGreenPrimaryY
Definition: ntv2publicinterface.h:3267
CNTV2RegisterExpert::GetRegistersWithName
static NTV2RegNumSet GetRegistersWithName(const std::string &inName, const int inSearchStyle=EXACTMATCH)
Definition: ntv2registerexpert.cpp:4818
kRegClass_NTV4FrameStore
#define kRegClass_NTV4FrameStore
Definition: ntv2registerexpert.h:74
kVRegGlobalAudioPlaybackMode
@ kVRegGlobalAudioPlaybackMode
Definition: ntv2virtualregisters.h:34
kRegRP188InOut4Bits32_63
@ kRegRP188InOut4Bits32_63
Definition: ntv2publicinterface.h:416
kRegAudioMixerMainInputLevelsPair1
@ kRegAudioMixerMainInputLevelsPair1
Definition: ntv2publicinterface.h:826
kRegLEDClockDivide
@ kRegLEDClockDivide
Definition: ntv2publicinterface.h:1086
kVRegLUT4Type
@ kVRegLUT4Type
Definition: ntv2virtualregisters.h:226
kVRegHDMIInDrmLightLevel2
@ kVRegHDMIInDrmLightLevel2
Definition: ntv2virtualregisters.h:624
kRegClass_VPID
#define kRegClass_VPID
Definition: ntv2registerexpert.h:71
kRegLEDReserved2
@ kRegLEDReserved2
Definition: ntv2publicinterface.h:1087
CNTV2RegisterExpert::GetRegistersForChannel
static NTV2RegNumSet GetRegistersForChannel(const NTV2Channel inChannel)
Definition: ntv2registerexpert.cpp:4804
NTV2_XptCSC4KeyInput
@ NTV2_XptCSC4KeyInput
Definition: ntv2enums.h:2774
NTV2_XptCSC6KeyInput
@ NTV2_XptCSC6KeyInput
Definition: ntv2enums.h:2778
kVRegDmaHardwareRateC2H3
@ kVRegDmaHardwareRateC2H3
Definition: ntv2virtualregisters.h:602
regAncInsPixelDelay
@ regAncInsPixelDelay
Definition: ntv2publicinterface.h:5389
CNTV2RegisterExpert::IsAllocated
static bool IsAllocated(void)
Definition: ntv2registerexpert.cpp:4738
kVRegSecondaryFormatSelect
@ kVRegSecondaryFormatSelect
Definition: ntv2virtualregisters.h:43
kVRegDmaHardwareRateC2H1
@ kVRegDmaHardwareRateC2H1
Definition: ntv2virtualregisters.h:594
kRegAudioMixerMainInputLevelsPair5
@ kRegAudioMixerMainInputLevelsPair5
Definition: ntv2publicinterface.h:830
kVRegDTVersionDurian
@ kVRegDTVersionDurian
Definition: ntv2virtualregisters.h:75
kVRegHDMIInDrmInfo1
@ kVRegHDMIInDrmInfo1
Definition: ntv2virtualregisters.h:610
nlohmann::json_abiNLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON_v3_11_NLOHMANN_JSON_VERSION_PATCH::detail::void
j template void())
Definition: json.hpp:4893
kVRegDTAudioMux1
@ kVRegDTAudioMux1
Definition: ntv2virtualregisters.h:71
NTV2_XptFrameBuffer7DS2Input
@ NTV2_XptFrameBuffer7DS2Input
Definition: ntv2enums.h:2764
kRegCh2PCIAccessFrame
@ kRegCh2PCIAccessFrame
Definition: ntv2publicinterface.h:126
kRegSDIOut4VPIDB
@ kRegSDIOut4VPIDB
Definition: ntv2publicinterface.h:418
kRegSysmonVccIntDieTemp
@ kRegSysmonVccIntDieTemp
Definition: ntv2publicinterface.h:251
kVRegDefaultVideoOutMode
@ kVRegDefaultVideoOutMode
Definition: ntv2virtualregisters.h:235
NTV2_XptCSC3KeyInput
@ NTV2_XptCSC3KeyInput
Definition: ntv2enums.h:2772
kVRegHDMIInDrmBluePrimary2
@ kVRegHDMIInDrmBluePrimary2
Definition: ntv2virtualregisters.h:620
NTV2HDMIOutputStatus
Reports HDMI output status information.
Definition: ntv2publicinterface.h:7149
kVRegHDMIOutHDRBluePrimary3
@ kVRegHDMIOutHDRBluePrimary3
Definition: ntv2virtualregisters.h:662
regNTV4FS_ROIF2VHOffsets
@ regNTV4FS_ROIF2VHOffsets
Definition: ntv2registerexpert.cpp:59
NTV2DeviceCanDo425Mux
bool NTV2DeviceCanDo425Mux(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:863
kVRegHdrInTransferCh1
@ kVRegHdrInTransferCh1
Definition: ntv2virtualregisters.h:560
kRegXptSelectGroup28
@ kRegXptSelectGroup28
Definition: ntv2publicinterface.h:581
kRegShiftFrameRateHiBit
@ kRegShiftFrameRateHiBit
Definition: ntv2publicinterface.h:2329
kVRegHDMIOutHDRControl3
@ kVRegHDMIOutHDRControl3
Definition: ntv2virtualregisters.h:667
kVRegAudioMixerOutputEnable
@ kVRegAudioMixerOutputEnable
Definition: ntv2virtualregisters.h:588
regAuxExtField1StartAddress
@ regAuxExtField1StartAddress
Definition: ntv2publicinterface.h:5455
NTV2_Xpt425Mux2BInput
@ NTV2_Xpt425Mux2BInput
Definition: ntv2enums.h:2863
kVRegRxcPlayoutDelay1
@ kVRegRxcPlayoutDelay1
Definition: ntv2virtualregisters.h:379
kVRegHDMIInDrmMasteringLuminence1
@ kVRegHDMIInDrmMasteringLuminence1
Definition: ntv2virtualregisters.h:615
kRegClass_Channel1
#define kRegClass_Channel1
Definition: ntv2registerexpert.h:44
NTV2FrameRate
NTV2FrameRate
Identifies a particular video frame rate.
Definition: ntv2enums.h:408
kVRegFlashSize
@ kVRegFlashSize
Definition: ntv2virtualregisters.h:301
kVRegNTV2VPIDTransferCharacteristics2
@ kVRegNTV2VPIDTransferCharacteristics2
Definition: ntv2virtualregisters.h:504
kVRegNTV2VPIDColorimetry
@ kVRegNTV2VPIDColorimetry
Definition: ntv2virtualregisters.h:501
NTV2_IS_VALID_InputCrosspointID
#define NTV2_IS_VALID_InputCrosspointID(__s__)
Definition: ntv2enums.h:2896
kVRegHDRInOverrideState
@ kVRegHDRInOverrideState
Definition: ntv2virtualregisters.h:574
kVRegHDMIOutControl1
@ kVRegHDMIOutControl1
Definition: ntv2virtualregisters.h:633
kIncludeOtherRegs_VRegs
#define kIncludeOtherRegs_VRegs
Definition: ntv2registerexpert.h:78
kK2RegMaskConverterOutRate
@ kK2RegMaskConverterOutRate
Definition: ntv2publicinterface.h:1693
NTV2AudioChannelQuadToString
std::string NTV2AudioChannelQuadToString(const NTV2Audio4ChannelSelect inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6432
kVRegNTV2VPIDRGBRange1
@ kVRegNTV2VPIDRGBRange1
Definition: ntv2virtualregisters.h:576
kVRegHDMIOutControl4
@ kVRegHDMIOutControl4
Definition: ntv2virtualregisters.h:669
NTV2_XptLUT2Input
@ NTV2_XptLUT2Input
Definition: ntv2enums.h:2784
kVRegMonAncField2Offset
@ kVRegMonAncField2Offset
Monitor Anc Field2 byte offset from end of frame buffer (IoIP only, GUMP)
Definition: ntv2virtualregisters.h:333
kRegLTC6EmbeddedBits32_63
@ kRegLTC6EmbeddedBits32_63
Definition: ntv2publicinterface.h:595
kRegDMA4NextDescHigh
@ kRegDMA4NextDescHigh
Definition: ntv2publicinterface.h:232
NTV2_XptDualLinkIn7DSInput
@ NTV2_XptDualLinkIn7DSInput
Definition: ntv2enums.h:2824
NTV2_XptFrameBuffer6Input
@ NTV2_XptFrameBuffer6Input
Definition: ntv2enums.h:2761
kVRegUseQTTimecode
@ kVRegUseQTTimecode
Definition: ntv2virtualregisters.h:161
NTV2_Xpt4KDCQ3Input
@ NTV2_Xpt4KDCQ3Input
Definition: ntv2enums.h:2858
NTV2_XptDualLinkIn3Input
@ NTV2_XptDualLinkIn3Input
Definition: ntv2enums.h:2815
kVRegDmaHardwareRateH2C1
@ kVRegDmaHardwareRateH2C1
Definition: ntv2virtualregisters.h:596
kRegShiftHDMIHDRWhitePointX
@ kRegShiftHDMIHDRWhitePointX
Definition: ntv2publicinterface.h:3272
kRegAud5Control
@ kRegAud5Control
Definition: ntv2publicinterface.h:619
kRegMaskHDMIHDRNonContantLuminance
@ kRegMaskHDMIHDRNonContantLuminance
Definition: ntv2publicinterface.h:2217
kVRegHDMIInDrmGreenPrimary1
@ kVRegHDMIInDrmGreenPrimary1
Definition: ntv2virtualregisters.h:611
NTV2RegNumSet
NTV2RegisterNumberSet NTV2RegNumSet
A set of distinct NTV2RegisterNumbers.
Definition: ntv2publicinterface.h:7661
ntv2signalrouter.h
Declares CNTV2SignalRouter class.
RegisterExpert::GetRegistersWithName
NTV2RegNumSet GetRegistersWithName(const string &inName, const int inMatchStyle=EXACTMATCH) const
Definition: ntv2registerexpert.cpp:2092
kVRegProcAmpHighDefHue
@ kVRegProcAmpHighDefHue
Definition: ntv2virtualregisters.h:211
kRegAud3InputLastAddr
@ kRegAud3InputLastAddr
Definition: ntv2publicinterface.h:425
kVRegAncField2Offset
@ kVRegAncField2Offset
Anc Field2 byte offset from end of frame buffer (GUMP on all boards except RTP for SMPTE2022/IP)
Definition: ntv2virtualregisters.h:337
kVRegAudioGainDisable
@ kVRegAudioGainDisable
Definition: ntv2virtualregisters.h:153
kVRegHdrTransferCh1
@ kVRegHdrTransferCh1
Definition: ntv2virtualregisters.h:537
kRegAudioMixerAux2GainCh2
@ kRegAudioMixerAux2GainCh2
Definition: ntv2publicinterface.h:819
NTV2BitfileHeaderParser::GetDesignVersion
static ULWord GetDesignVersion(const ULWord userID)
Definition: ntv2bitfile.h:55
NTV2DeviceGetNumSerialPorts
UWord NTV2DeviceGetNumSerialPorts(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12641
kVRegHDMIInDrmGreenPrimary2
@ kVRegHDMIInDrmGreenPrimary2
Definition: ntv2virtualregisters.h:619
kRegEnhancedCSC1CoeffC2
@ kRegEnhancedCSC1CoeffC2
Definition: ntv2publicinterface.h:883
kRegSDIIn6VPIDA
@ kRegSDIIn6VPIDA
Definition: ntv2publicinterface.h:587
regNTV4FS_REGISTER_COUNT
@ regNTV4FS_REGISTER_COUNT
Definition: ntv2registerexpert.cpp:79
kRegAud5InputLastAddr
@ kRegAud5InputLastAddr
Definition: ntv2publicinterface.h:622
kRegSDIOut6VPIDA
@ kRegSDIOut6VPIDA
Definition: ntv2publicinterface.h:589
kVRegKIPDecCfgError
@ kVRegKIPDecCfgError
Definition: ntv2virtualregisters.h:458
kRegRP188InOut6Bits32_63
@ kRegRP188InOut6Bits32_63
Definition: ntv2publicinterface.h:592
NTV2_XptMixer4FGVidInput
@ NTV2_XptMixer4FGVidInput
Definition: ntv2enums.h:2850
kRegCh3Control
@ kRegCh3Control
Definition: ntv2publicinterface.h:398
gRegExpertGuardMutex
static AJALock gRegExpertGuardMutex
Definition: ntv2registerexpert.cpp:4711
NTV2_XptDualLinkIn7Input
@ NTV2_XptDualLinkIn7Input
Definition: ntv2enums.h:2823
kVRegTestPatternChoice
@ kVRegTestPatternChoice
Definition: ntv2virtualregisters.h:231
kVRegAudioOutputToneSelect
@ kVRegAudioOutputToneSelect
Definition: ntv2virtualregisters.h:627
kVRegReleaseApplication
@ kVRegReleaseApplication
Definition: ntv2virtualregisters.h:186
kRegMaskSDIRelayPosition34
@ kRegMaskSDIRelayPosition34
Definition: ntv2publicinterface.h:2101
kRegAud8Delay
@ kRegAud8Delay
Definition: ntv2publicinterface.h:689
NTV2DriverVersionDecode_Point
#define NTV2DriverVersionDecode_Point(__vers__)
Definition: ntv2publicinterface.h:5556
regNTV4FS_ROIF1VHOffsets
@ regNTV4FS_ROIF1VHOffsets
Definition: ntv2registerexpert.cpp:58
kRegClass_Mixer
#define kRegClass_Mixer
Definition: ntv2registerexpert.h:61
kRegMaskBOBAnalogInputSelect
@ kRegMaskBOBAnalogInputSelect
Definition: ntv2publicinterface.h:2318
kVRegTimeStampLastOutput2VerticalHi
@ kVRegTimeStampLastOutput2VerticalHi
Definition: ntv2virtualregisters.h:282
kRegMaskSDIWatchdogEnable12
@ kRegMaskSDIWatchdogEnable12
Definition: ntv2publicinterface.h:2098
kRegOutputTimingControlch5
@ kRegOutputTimingControlch5
Definition: ntv2publicinterface.h:671
NTV2_XptLUT1Input
@ NTV2_XptLUT1Input
Definition: ntv2enums.h:2783
regAncExt_LAST
@ regAncExt_LAST
Definition: ntv2publicinterface.h:5379
kRegCS8Coefficients7_8
@ kRegCS8Coefficients7_8
Definition: ntv2publicinterface.h:661
regNTV4FS_F2ActiveLines
@ regNTV4FS_F2ActiveLines
Definition: ntv2registerexpert.cpp:63
kVRegNTV2VPIDRGBRange2
@ kVRegNTV2VPIDRGBRange2
Definition: ntv2virtualregisters.h:577
NTV2DeviceGetHDMIVersion
ULWord NTV2DeviceGetHDMIVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:9374
kRegCh2Control
@ kRegCh2Control
Definition: ntv2publicinterface.h:125
kVRegHdrInBlueYCh1
@ kVRegHdrInBlueYCh1
Definition: ntv2virtualregisters.h:565
kRegHDMIOutControl
@ kRegHDMIOutControl
Definition: ntv2publicinterface.h:258
regAuxExtPacketMask1
@ regAuxExtPacketMask1
Definition: ntv2publicinterface.h:5468
kVRegAdvancedIndexing
@ kVRegAdvancedIndexing
Definition: ntv2virtualregisters.h:267
kRegLTC3EmbeddedBits0_31
@ kRegLTC3EmbeddedBits0_31
Definition: ntv2publicinterface.h:464
kVRegTimeCodeCh2Delay
@ kVRegTimeCodeCh2Delay
Definition: ntv2virtualregisters.h:93
kRegMaskHDMIHDRDolbyVisionEnable
@ kRegMaskHDMIHDRDolbyVisionEnable
Definition: ntv2publicinterface.h:2218
kVRegRxcSfp1Vlan2
@ kVRegRxcSfp1Vlan2
Definition: ntv2virtualregisters.h:387
kRegClass_Timecode
#define kRegClass_Timecode
Definition: ntv2registerexpert.h:67
NTV2DeviceGetUFCVersion
ULWord NTV2DeviceGetUFCVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:13292
kVRegMailBoxAbort
@ kVRegMailBoxAbort
Definition: ntv2virtualregisters.h:415
PresNotPres
#define PresNotPres(__x__)
Definition: ntv2registerexpert.h:33
kRegMaskVUMeterSelect
@ kRegMaskVUMeterSelect
Definition: ntv2publicinterface.h:1290
kVRegRxcSfp2DestPort2
@ kVRegRxcSfp2DestPort2
Definition: ntv2virtualregisters.h:392
kVRegEFTNeedsUpdating
@ kVRegEFTNeedsUpdating
Definition: ntv2virtualregisters.h:309
kVRegTimeStampLastOutput8VerticalLo
@ kVRegTimeStampLastOutput8VerticalLo
Definition: ntv2virtualregisters.h:296
kVRegTimeStampLastOutput6VerticalLo
@ kVRegTimeStampLastOutput6VerticalLo
Definition: ntv2virtualregisters.h:292
kRegHDMIHDRMasteringLuminence
@ kRegHDMIHDRMasteringLuminence
Definition: ntv2publicinterface.h:487
kVRegAudioInputDelay
@ kVRegAudioInputDelay
Definition: ntv2virtualregisters.h:158
kRegRXSDIFreeRunningClockHigh
@ kRegRXSDIFreeRunningClockHigh
Definition: ntv2publicinterface.h:793
kVRegLUT2Type
@ kVRegLUT2Type
Definition: ntv2virtualregisters.h:224
kVRegUserColorimetry
@ kVRegUserColorimetry
Definition: ntv2virtualregisters.h:532
kVRegAudioCapMixerSourceAux1Enable
@ kVRegAudioCapMixerSourceAux1Enable
Definition: ntv2virtualregisters.h:478
kVRegNTV2VPIDColorimetry6
@ kVRegNTV2VPIDColorimetry6
Definition: ntv2virtualregisters.h:521
kVRegNTV2VPIDLuminance5
@ kVRegNTV2VPIDLuminance5
Definition: ntv2virtualregisters.h:518
kRegCS2Coefficients1_2
@ kRegCS2Coefficients1_2
Definition: ntv2publicinterface.h:283
kRegGlobalControlCh8
@ kRegGlobalControlCh8
Definition: ntv2publicinterface.h:551
kVRegRxcSfp2DestIp1
@ kVRegRxcSfp2DestIp1
Definition: ntv2virtualregisters.h:374
kRegMaskBOBGPIIn2InterruptControl
@ kRegMaskBOBGPIIn2InterruptControl
Definition: ntv2publicinterface.h:2307
kRegMaskSDIRelayControl34
@ kRegMaskSDIRelayControl34
Definition: ntv2publicinterface.h:2097
kVRegAudioSyncTolerance
@ kVRegAudioSyncTolerance
Definition: ntv2virtualregisters.h:87
OnOff
#define OnOff(__x__)
Definition: ntv2registerexpert.h:26
regAncInsField1StartAddr
@ regAncInsField1StartAddr
Definition: ntv2publicinterface.h:5387
kRegMaskAudioMixerInputLeftLevel
@ kRegMaskAudioMixerInputLeftLevel
Definition: ntv2publicinterface.h:2269
kVRegForceApplicationPID
@ kVRegForceApplicationPID
Definition: ntv2virtualregisters.h:187
kVRegVideoFormatCh8
@ kVRegVideoFormatCh8
Definition: ntv2virtualregisters.h:354
kVRegHDMIOutHDRWhitePoint2
@ kVRegHDMIOutHDRWhitePoint2
Definition: ntv2virtualregisters.h:652
kRegMaskQuadMode
@ kRegMaskQuadMode
Definition: ntv2publicinterface.h:1255
kRegHDMIV2I2C1Data
@ kRegHDMIV2I2C1Data
Definition: ntv2publicinterface.h:525
kVRegNTV2VPIDLuminance3
@ kVRegNTV2VPIDLuminance3
Definition: ntv2virtualregisters.h:510
kVRegDSKAudioMode
@ kVRegDSKAudioMode
Definition: ntv2virtualregisters.h:120
aja::lower
std::string & lower(std::string &str)
Definition: common.cpp:436
kVRegRecallRegistersFromRegistry
@ kVRegRecallRegistersFromRegistry
Definition: ntv2virtualregisters.h:64
kVRegTimeCodeCh3Delay
@ kVRegTimeCodeCh3Delay
Definition: ntv2virtualregisters.h:96
NTV2DownConvertMode
NTV2DownConvertMode
Definition: ntv2enums.h:2238
kRegSDIOut3Control
@ kRegSDIOut3Control
Definition: ntv2publicinterface.h:307
kRegCS4Coefficients7_8
@ kRegCS4Coefficients7_8
Definition: ntv2publicinterface.h:442
kVRegEveryFrameTaskFilter
@ kVRegEveryFrameTaskFilter
Definition: ntv2virtualregisters.h:233
kRegAud6SourceSelect
@ kRegAud6SourceSelect
Definition: ntv2publicinterface.h:625
kRegCMWHDMIOut
@ kRegCMWHDMIOut
Definition: ntv2publicinterface.h:1102
NTV2_XptFrameBuffer7Input
@ NTV2_XptFrameBuffer7Input
Definition: ntv2enums.h:2763
kRegMaskHDRStaticMetadataDescriptorID
@ kRegMaskHDRStaticMetadataDescriptorID
Definition: ntv2publicinterface.h:2221
kVRegHDMIInRgbRange
@ kVRegHDMIInRgbRange
Definition: ntv2virtualregisters.h:136
kVRegHdmiHdrOutMode
@ kVRegHdmiHdrOutMode
Definition: ntv2virtualregisters.h:492
NTV2BitfileHeaderParser::GetBitfileID
static ULWord GetBitfileID(const ULWord userID)
Definition: ntv2bitfile.h:56
CNTV2RegisterExpert::GetRegisterClasses
static NTV2StringSet GetRegisterClasses(const uint32_t inRegNum, const bool inRemovePrefix=false)
Definition: ntv2registerexpert.cpp:4790
regAncInsIpChannel
@ regAncInsIpChannel
Definition: ntv2publicinterface.h:5403
kVRegNTV2VPIDLuminance2
@ kVRegNTV2VPIDLuminance2
Definition: ntv2virtualregisters.h:506
NTV2_XptFrameBuffer1Input
@ NTV2_XptFrameBuffer1Input
Definition: ntv2enums.h:2751
kRegSDIWatchdogKick2
@ kRegSDIWatchdogKick2
Definition: ntv2publicinterface.h:460
regAncExtField1AnalogYFilter
@ regAncExtField1AnalogYFilter
Definition: ntv2publicinterface.h:5369
kRegCh5OutputFrame
@ kRegCh5OutputFrame
Definition: ntv2publicinterface.h:554
kRegLEDHDMIInControl
@ kRegLEDHDMIInControl
Definition: ntv2publicinterface.h:1091
kVRegVideoOutPauseMode
@ kVRegVideoOutPauseMode
Definition: ntv2virtualregisters.h:52
kIncludeOtherRegs_XptROM
#define kIncludeOtherRegs_XptROM
Definition: ntv2registerexpert.h:79
RegisterExpert::GetXptRegNumAndMaskIndex
bool GetXptRegNumAndMaskIndex(const NTV2InputCrosspointID inInputXpt, uint32_t &outXptRegNum, uint32_t &outMaskIndex) const
Definition: ntv2registerexpert.cpp:2127
regNTV4FS_RasterSmpteFramePulse
@ regNTV4FS_RasterSmpteFramePulse
Definition: ntv2registerexpert.cpp:72
kRegAud4InputLastAddr
@ kRegAud4InputLastAddr
Definition: ntv2publicinterface.h:427
kVRegFrameBuffer2Stereo3DMode
@ kVRegFrameBuffer2Stereo3DMode
Definition: ntv2virtualregisters.h:152
kRegRP188InOut2Bits0_31_2
@ kRegRP188InOut2Bits0_31_2
Definition: ntv2publicinterface.h:345
kRegRP188InOut8Bits32_63
@ kRegRP188InOut8Bits32_63
Definition: ntv2publicinterface.h:612
kVRegRxcSfp1Vlan1
@ kVRegRxcSfp1Vlan1
Definition: ntv2virtualregisters.h:371
kVRegColorSpaceMode
@ kVRegColorSpaceMode
Definition: ntv2virtualregisters.h:54
NTV2_XptDualLinkIn2Input
@ NTV2_XptDualLinkIn2Input
Definition: ntv2enums.h:2813
NTV2Standard
NTV2Standard
Identifies a particular video standard.
Definition: ntv2enums.h:161
kVRegSDIInput2FormatSelect
@ kVRegSDIInput2FormatSelect
Definition: ntv2virtualregisters.h:128
kVRegTimeStampLastOutputVerticalHi
@ kVRegTimeStampLastOutputVerticalHi
Definition: ntv2virtualregisters.h:80
kK2RegShiftConverterInRate
@ kK2RegShiftConverterInRate
Definition: ntv2publicinterface.h:2775
regAuxExtField2Status
@ regAuxExtField2Status
Definition: ntv2publicinterface.h:5462
kRegVidProc4Control
@ kRegVidProc4Control
Definition: ntv2publicinterface.h:680
kVRegNTV2VPIDColorimetry8
@ kVRegNTV2VPIDColorimetry8
Definition: ntv2virtualregisters.h:529
kRegLTC8EmbeddedBits32_63
@ kRegLTC8EmbeddedBits32_63
Definition: ntv2publicinterface.h:615
kRegFS1ReferenceSelect
@ kRegFS1ReferenceSelect
Definition: ntv2publicinterface.h:219
lock.h
Declares the AJALock class.
kRegMaskFrameFormatHiBit
@ kRegMaskFrameFormatHiBit
Definition: ntv2publicinterface.h:1308
aja::replace
std::string & replace(std::string &str, const std::string &from, const std::string &to)
Definition: common.cpp:110
NTV2AudioChannelPairToString
std::string NTV2AudioChannelPairToString(const NTV2AudioChannelPair inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6420
CNTV2SignalRouter::GetRouteROMInfoFromReg
static bool GetRouteROMInfoFromReg(const ULWord inROMRegNum, const ULWord inROMRegValue, NTV2InputXptID &outInputXpt, NTV2OutputXptIDSet &outOutputXpts, const bool inAppendOutputXpts=false)
Answers with the NTV2InputXptID and NTV2OutputXptIDSet for the given ROM register value.
Definition: ntv2signalrouter.cpp:1059
ULWord
uint32_t ULWord
Definition: ajatypes.h:276
kRegXptSelectGroup2
@ kRegXptSelectGroup2
Definition: ntv2publicinterface.h:271
NTV2DriverVersionDecode_Major
#define NTV2DriverVersionDecode_Major(__vers__)
Definition: ntv2publicinterface.h:5554
NTV2_XptMultiLinkOut1InputDS2
@ NTV2_XptMultiLinkOut1InputDS2
New in SDK 16.0.
Definition: ntv2enums.h:2792
NTV2DeviceCanDoAudioMixer
bool NTV2DeviceCanDoAudioMixer(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:1803
kRegMaskHDMIHDRBluePrimaryX
@ kRegMaskHDMIHDRBluePrimaryX
Definition: ntv2publicinterface.h:2206
kRegShiftAudioMixerInputRightLevel
@ kRegShiftAudioMixerInputRightLevel
Definition: ntv2publicinterface.h:3332
regAncExtField2Status
@ regAncExtField2Status
Definition: ntv2publicinterface.h:5357
kRegRP188InOut5Bits32_63
@ kRegRP188InOut5Bits32_63
Definition: ntv2publicinterface.h:496
kRegRP188InOut2DBB
@ kRegRP188InOut2DBB
Definition: ntv2publicinterface.h:185
kVRegSDIOutput1RGBRange
@ kVRegSDIOutput1RGBRange
Definition: ntv2virtualregisters.h:126
kRegXptSelectGroup10
@ kRegXptSelectGroup10
Definition: ntv2publicinterface.h:392
kRegGlobalControlCh6
@ kRegGlobalControlCh6
Definition: ntv2publicinterface.h:549
kVRegDTFirmware
@ kVRegDTFirmware
Definition: ntv2virtualregisters.h:73
kRegSDIIn5VPIDB
@ kRegSDIIn5VPIDB
Definition: ntv2publicinterface.h:585
kRegMaskFrameSizeSetBySW
@ kRegMaskFrameSizeSetBySW
Definition: ntv2publicinterface.h:1326
NTV2_XptMixer1FGKeyInput
@ NTV2_XptMixer1FGKeyInput
Definition: ntv2enums.h:2837
kVRegHDMIOutHDRRedPrimary3
@ kVRegHDMIOutHDRRedPrimary3
Definition: ntv2virtualregisters.h:663
kVRegHDMIInputStatus2
@ kVRegHDMIInputStatus2
Definition: ntv2virtualregisters.h:646
kVRegVideoFormatCh2
@ kVRegVideoFormatCh2
Definition: ntv2virtualregisters.h:348
regNTV4FS_DisplayHorzPixelsPerLine
@ regNTV4FS_DisplayHorzPixelsPerLine
Definition: ntv2registerexpert.cpp:60
kRegMaskFrameFormat
@ kRegMaskFrameFormat
Definition: ntv2publicinterface.h:1306
kK2RegMaskConverterPulldown
@ kK2RegMaskConverterPulldown
Definition: ntv2publicinterface.h:1698
kVRegAvailable164
@ kVRegAvailable164
Definition: ntv2virtualregisters.h:162
kRegXptSelectGroup12
@ kRegXptSelectGroup12
Definition: ntv2publicinterface.h:334
kRegClass_Input
#define kRegClass_Input
Definition: ntv2registerexpert.h:56
kVRegHDMIInAviInfo1
@ kVRegHDMIInAviInfo1
Definition: ntv2virtualregisters.h:609
kVRegAncField1Offset
@ kVRegAncField1Offset
Anc Field1 byte offset from end of frame buffer (GUMP on all boards except RTP for SMPTE2022/IP)
Definition: ntv2virtualregisters.h:336
kRegMRQ1Control
@ kRegMRQ1Control
Definition: ntv2publicinterface.h:1050
CNTV2RegisterExpert::GetDisplayName
static std::string GetDisplayName(const uint32_t inRegNum)
Definition: ntv2registerexpert.cpp:4752
kVRegTimeStampLastOutput8VerticalHi
@ kVRegTimeStampLastOutput8VerticalHi
Definition: ntv2virtualregisters.h:314
NTV2ReferenceSource
NTV2ReferenceSource
These enum values identify a specific source for the device's (output) reference clock.
Definition: ntv2enums.h:1450
kRegMaskHDMIHDRMinMasteringLuminance
@ kRegMaskHDMIHDRMinMasteringLuminance
Definition: ntv2publicinterface.h:2213
kRegCh4InputFrame
@ kRegCh4InputFrame
Definition: ntv2publicinterface.h:403
NTV2BitfileHeaderParser::GetBitfileVersion
static ULWord GetBitfileVersion(const ULWord userID)
Definition: ntv2bitfile.h:57
NTV2EndianSwap32
#define NTV2EndianSwap32(__val__)
Definition: ntv2endian.h:19
kVRegRxcEnable2
@ kVRegRxcEnable2
Definition: ntv2virtualregisters.h:381
kVRegHDMIInDrmWhitePoint2
@ kVRegHDMIInDrmWhitePoint2
Definition: ntv2virtualregisters.h:622
kVRegSDIOutConfig
@ kVRegSDIOutConfig
Definition: ntv2virtualregisters.h:178
kVRegSoftwareUartFifo
@ kVRegSoftwareUartFifo
Definition: ntv2virtualregisters.h:91
regAncExtAnalogActiveLineLength
@ regAncExtAnalogActiveLineLength
Definition: ntv2publicinterface.h:5378
kVRegLTCOnRefInSelect
@ kVRegLTCOnRefInSelect
Definition: ntv2virtualregisters.h:154
kVRegTimeCodeCh7Delay
@ kVRegTimeCodeCh7Delay
Definition: ntv2virtualregisters.h:104
NTV2_XptSDIOut2Input
@ NTV2_XptSDIOut2Input
Definition: ntv2enums.h:2797
CNTV2VPID
A convenience class that simplifies encoding or decoding the 4-byte VPID payload that can be read or ...
Definition: ntv2vpid.h:23
NTV2DeviceHasBiDirectionalSDI
bool NTV2DeviceHasBiDirectionalSDI(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:6926
kRegAudioMixerMainOutputLevelsPair5
@ kRegAudioMixerMainOutputLevelsPair5
Definition: ntv2publicinterface.h:839
kRegRXSDI7Status
@ kRegRXSDI7Status
Definition: ntv2publicinterface.h:774
regAncExtIgnorePacketReg_17_18_19_20
@ regAncExtIgnorePacketReg_17_18_19_20
Definition: ntv2publicinterface.h:5366
kRegMaskAudioMixerLevelSampleCount
@ kRegMaskAudioMixerLevelSampleCount
Definition: ntv2publicinterface.h:2271
kRegCh4PCIAccessFrame
@ kRegCh4PCIAccessFrame
Definition: ntv2publicinterface.h:431
kRegHDMIV2I2C1Control
@ kRegHDMIV2I2C1Control
Definition: ntv2publicinterface.h:524
kRegMaskSaturationValue
@ kRegMaskSaturationValue
Definition: ntv2publicinterface.h:1441
kVRegHDMIOutputSelect
@ kVRegHDMIOutputSelect
Definition: ntv2virtualregisters.h:229
NTV2_XptIICT1Input
@ NTV2_XptIICT1Input
Definition: ntv2enums.h:2874
RegisterExpert::IsRegisterWriteOnly
bool IsRegisterWriteOnly(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1874
regNTV4FS_ROIF2StartAddr
@ regNTV4FS_ROIF2StartAddr
Definition: ntv2registerexpert.cpp:57
NTV2DeviceCanDoIDSwitch
bool NTV2DeviceCanDoIDSwitch(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:3682
kRegRP188InOut1Bits32_63
@ kRegRP188InOut1Bits32_63
Definition: ntv2publicinterface.h:152
kVRegDSKForegroundMode
@ kVRegDSKForegroundMode
Definition: ntv2virtualregisters.h:121
kRegAud1InputLastAddr
@ kRegAud1InputLastAddr
Definition: ntv2publicinterface.h:148
kRegClass_Channel6
#define kRegClass_Channel6
Definition: ntv2registerexpert.h:49
kRegAud3Control
@ kRegAud3Control
Definition: ntv2publicinterface.h:419
kVRegTimeStampLastInput1VerticalHi
@ kVRegTimeStampLastInput1VerticalHi
Definition: ntv2virtualregisters.h:82
kVRegKIPTxCfgError
@ kVRegKIPTxCfgError
Definition: ntv2virtualregisters.h:456
kVRegPCILinkSpeed
@ kVRegPCILinkSpeed
Definition: ntv2virtualregisters.h:629
NTV2DeviceCanDoSDIErrorChecks
bool NTV2DeviceCanDoSDIErrorChecks(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:5330
kVRegTimeStampLastInput2VerticalHi
@ kVRegTimeStampLastInput2VerticalHi
Definition: ntv2virtualregisters.h:84
kRegClass_IP
#define kRegClass_IP
Definition: ntv2registerexpert.h:59
NTV2DeviceSoftwareCanChangeFrameBufferSize
bool NTV2DeviceSoftwareCanChangeFrameBufferSize(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8908
NTV2DeviceIDToString
std::string NTV2DeviceIDToString(const NTV2DeviceID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:4608
kVRegLUT5Type
@ kVRegLUT5Type
Definition: ntv2virtualregisters.h:238
NTV2_XptWaterMarker1Input
@ NTV2_XptWaterMarker1Input
Definition: ntv2enums.h:2875
kRegSDIIn1VPIDA
@ kRegSDIIn1VPIDA
Definition: ntv2publicinterface.h:329
kRegShiftAudioMixerLevelSampleCount
@ kRegShiftAudioMixerLevelSampleCount
Definition: ntv2publicinterface.h:3333
kRegCh2InputFrame
@ kRegCh2InputFrame
Definition: ntv2publicinterface.h:128
kVRegNumDmaDriverBuffers
@ kVRegNumDmaDriverBuffers
Definition: ntv2virtualregisters.h:260
kRegHDMIV2VerticalMeasurementsField1
@ kRegHDMIV2VerticalMeasurementsField1
Definition: ntv2publicinterface.h:538
kRegMaskCCMode
@ kRegMaskCCMode
Definition: ntv2publicinterface.h:1443
kVRegTimecodeBurnInMode
@ kVRegTimecodeBurnInMode
Definition: ntv2virtualregisters.h:160
kVRegDebugLastFormat
@ kVRegDebugLastFormat
Definition: ntv2virtualregisters.h:110
regAuxExt_LAST
@ regAuxExt_LAST
Definition: ntv2publicinterface.h:5473
kVRegHDMIOutHDRMasterLuminance1
@ kVRegHDMIOutHDRMasterLuminance1
Definition: ntv2virtualregisters.h:641
kRegMaskHDMIHDRWhitePointX
@ kRegMaskHDMIHDRWhitePointX
Definition: ntv2publicinterface.h:2210
kVRegTxc_2EncodeAudio1Pid2
@ kVRegTxc_2EncodeAudio1Pid2
Definition: ntv2virtualregisters.h:450
kRegDMA2NextDescHigh
@ kRegDMA2NextDescHigh
Definition: ntv2publicinterface.h:228
kVRegTimeStampLastOutput4VerticalHi
@ kVRegTimeStampLastOutput4VerticalHi
Definition: ntv2virtualregisters.h:287
kVRegProcAmpHighDefCbOffset
@ kVRegProcAmpHighDefCbOffset
Definition: ntv2virtualregisters.h:212
kRegCS8Coefficients1_2
@ kRegCS8Coefficients1_2
Definition: ntv2publicinterface.h:658
kRegMaskHDMIHDRRedPrimaryY
@ kRegMaskHDMIHDRRedPrimaryY
Definition: ntv2publicinterface.h:2209
kRegCMW1485Out
@ kRegCMW1485Out
Definition: ntv2publicinterface.h:1098
kVRegBA2MemorySize
@ kVRegBA2MemorySize
Definition: ntv2virtualregisters.h:262
kVRegFramesPerVertical
@ kVRegFramesPerVertical
Definition: ntv2virtualregisters.h:316
regAncInsRtpPayloadID
@ regAncInsRtpPayloadID
Definition: ntv2publicinterface.h:5401
kVRegSDIOutput2Stereo3DMode
@ kVRegSDIOutput2Stereo3DMode
Definition: ntv2virtualregisters.h:150
kVRegNTV2VPIDRGBRange5
@ kVRegNTV2VPIDRGBRange5
Definition: ntv2virtualregisters.h:580
kRegDMA4HostAddr
@ kRegDMA4HostAddr
Definition: ntv2publicinterface.h:165
kRegMaskHDMISampling
@ kRegMaskHDMISampling
Definition: ntv2publicinterface.h:1603
kRegIDSwitch
@ kRegIDSwitch
Definition: ntv2publicinterface.h:1065
kRegCh5PCIAccessFrame
@ kRegCh5PCIAccessFrame
Definition: ntv2publicinterface.h:556
kRegLTC7EmbeddedBits32_63
@ kRegLTC7EmbeddedBits32_63
Definition: ntv2publicinterface.h:605
regAncInsBlankField1CLines
@ regAncInsBlankField1CLines
Definition: ntv2publicinterface.h:5397
kRegMaskFrameRateHiBit
@ kRegMaskFrameRateHiBit
Definition: ntv2publicinterface.h:1236
NTV2IsoConvertModeToString
std::string NTV2IsoConvertModeToString(const NTV2IsoConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6619
kVRegUserDefinedDBB
@ kVRegUserDefinedDBB
Definition: ntv2virtualregisters.h:463
kRegMaskHDMIHDRGreenPrimaryY
@ kRegMaskHDMIHDRGreenPrimaryY
Definition: ntv2publicinterface.h:2205
regAncExtField2EndAddress
@ regAncExtField2EndAddress
Definition: ntv2publicinterface.h:5353
kVRegHdrInLuminanceCh1
@ kVRegHdrInLuminanceCh1
Definition: ntv2virtualregisters.h:561
kRegMaskAud1PlayCapMode
@ kRegMaskAud1PlayCapMode
Definition: ntv2publicinterface.h:1256
NTV2_XptConversionModInput
@ NTV2_XptConversionModInput
Definition: ntv2enums.h:2880
kVRegVideoFormatCh1
@ kVRegVideoFormatCh1
Definition: ntv2virtualregisters.h:347
kRegMaskVidProcVANCShift
@ kRegMaskVidProcVANCShift
Definition: ntv2publicinterface.h:1327
regAuxExtFillData
@ regAuxExtFillData
Definition: ntv2publicinterface.h:5472
kRegSDIIn1VPIDB
@ kRegSDIIn1VPIDB
Definition: ntv2publicinterface.h:330
kVRegSDIInput1RGBRange
@ kVRegSDIInput1RGBRange
Definition: ntv2virtualregisters.h:129
kRegGlobalControl2
@ kRegGlobalControl2
Definition: ntv2publicinterface.h:408
kRegClass_Channel3
#define kRegClass_Channel3
Definition: ntv2registerexpert.h:46
kVRegRxcSfp1DestIp2
@ kVRegRxcSfp1DestIp2
Definition: ntv2virtualregisters.h:384
NTV2_AudioChannel3_4
@ NTV2_AudioChannel3_4
This selects audio channels 3 and 4 (Group 1 channels 3 and 4)
Definition: ntv2enums.h:3122
NTV2StandardToString
std::string NTV2StandardToString(const NTV2Standard inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:6899
kVRegSaveRegistersToRegistry
@ kVRegSaveRegistersToRegistry
Definition: ntv2virtualregisters.h:63
kVRegHDMIOutHDRLightLevel1
@ kVRegHDMIOutHDRLightLevel1
Definition: ntv2virtualregisters.h:642
NTV2InputCrosspointIDToString
std::string NTV2InputCrosspointIDToString(const NTV2InputCrosspointID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:5811
kVRegAnalogInBlackLevel
@ kVRegAnalogInBlackLevel
Definition: ntv2virtualregisters.h:138
kRegAudioDetect5678
@ kRegAudioDetect5678
Definition: ntv2publicinterface.h:639
kVRegAudioInputMapSelect
@ kVRegAudioInputMapSelect
Definition: ntv2virtualregisters.h:156
kVRegHDMIOutHDRWhitePoint1
@ kVRegHDMIOutHDRWhitePoint1
Definition: ntv2virtualregisters.h:640
NTV2DeviceGetNumVideoInputs
UWord NTV2DeviceGetNumVideoInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12920
NTV2DeviceGetNumHDMIVideoOutputs
UWord NTV2DeviceGetNumHDMIVideoOutputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11804
kRegLUTV2Control
@ kRegLUTV2Control
Definition: ntv2publicinterface.h:542
SuppNotsupp
#define SuppNotsupp(__x__)
Definition: ntv2registerexpert.h:32
kVRegAudioHeadphoneGain
@ kVRegAudioHeadphoneGain
Definition: ntv2virtualregisters.h:587
kRegAudioMixerInputSelects
@ kRegAudioMixerInputSelects
Definition: ntv2publicinterface.h:812
kVRegUnfilterAnc
@ kVRegUnfilterAnc
Definition: ntv2virtualregisters.h:125
kVRegProcAmpHighDefSaturationCr
@ kVRegProcAmpHighDefSaturationCr
Definition: ntv2virtualregisters.h:210
kVRegOutputTimecodeType
@ kVRegOutputTimecodeType
Definition: ntv2virtualregisters.h:182
NTV2AudioChannelPair
NTV2AudioChannelPair
Identifies a pair of audio channels.
Definition: ntv2enums.h:3119
kRegDMA3NextDesc
@ kRegDMA3NextDesc
Definition: ntv2publicinterface.h:164
kVRegProcAmpHDRegsInitialized
@ kVRegProcAmpHDRegsInitialized
Definition: ntv2virtualregisters.h:206
kRegEnhancedCSC1OutOffsetA_B
@ kRegEnhancedCSC1OutOffsetA_B
Definition: ntv2publicinterface.h:884
kRegXptSelectGroup26
@ kRegXptSelectGroup26
Definition: ntv2publicinterface.h:579
kRegGlobalControl3
@ kRegGlobalControl3
Definition: ntv2publicinterface.h:234
NTV2DeviceGetNumLUTs
UWord NTV2DeviceGetNumLUTs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12269
kColorCorrectionLUTOffset_Red
#define kColorCorrectionLUTOffset_Red
Definition: ntv2publicinterface.h:4299
kRegMaskSmpte372Enable4
@ kRegMaskSmpte372Enable4
Definition: ntv2publicinterface.h:1265
kVRegDmaTransferRateC2H1
@ kVRegDmaTransferRateC2H1
Definition: ntv2virtualregisters.h:593
kRegRP188InOut7Bits0_31
@ kRegRP188InOut7Bits0_31
Definition: ntv2publicinterface.h:601
UWord
uint16_t UWord
Definition: ajatypes.h:274
kVRegHDMIOutHDRRedPrimary4
@ kVRegHDMIOutHDRRedPrimary4
Definition: ntv2virtualregisters.h:675
kVRegTimeCodeIn2Delay
@ kVRegTimeCodeIn2Delay
Definition: ntv2virtualregisters.h:95
kRegDMA3HostAddr
@ kRegDMA3HostAddr
Definition: ntv2publicinterface.h:161
kRegAudioMixerMainInputLevelsPair7
@ kRegAudioMixerMainInputLevelsPair7
Definition: ntv2publicinterface.h:832
NTV2_Xpt4KDCQ1Input
@ NTV2_Xpt4KDCQ1Input
Definition: ntv2enums.h:2856
kK2RegShiftConverterOutStandard
@ kK2RegShiftConverterOutStandard
Definition: ntv2publicinterface.h:2770
kVRegMailBoxTimeoutNS
@ kVRegMailBoxTimeoutNS
Definition: ntv2virtualregisters.h:416
kVRegDTAudioMux2
@ kVRegDTAudioMux2
Definition: ntv2virtualregisters.h:72
kRegSDIOut5Control
@ kRegSDIOut5Control
Definition: ntv2publicinterface.h:491
kVRegHDMIInputStatus1
@ kVRegHDMIInputStatus1
Definition: ntv2virtualregisters.h:634
kRegAud6OutputLastAddr
@ kRegAud6OutputLastAddr
Definition: ntv2publicinterface.h:626
regNTV4FS_ROIF1StartAddr
@ regNTV4FS_ROIF1StartAddr
Definition: ntv2registerexpert.cpp:56
kVRegProcAmpStandardDefContrast
@ kVRegProcAmpStandardDefContrast
Definition: ntv2virtualregisters.h:199
kVRegDesktopFrameBufferStatus
@ kVRegDesktopFrameBufferStatus
Definition: ntv2virtualregisters.h:169
kRegAud3OutputLastAddr
@ kRegAud3OutputLastAddr
Definition: ntv2publicinterface.h:424
kVRegAudioHeadphoneEnable
@ kVRegAudioHeadphoneEnable
Definition: ntv2virtualregisters.h:589
kRegHDMIV2VActiveField2
@ kRegHDMIV2VActiveField2
Definition: ntv2publicinterface.h:532
kRegDMA4NextDesc
@ kRegDMA4NextDesc
Definition: ntv2publicinterface.h:168
kRegRP188InOut6Bits0_31_2
@ kRegRP188InOut6Bits0_31_2
Definition: ntv2publicinterface.h:353
kRegDMA1HostAddr
@ kRegDMA1HostAddr
Definition: ntv2publicinterface.h:153
NTV2_XptCSC8VidInput
@ NTV2_XptCSC8VidInput
Definition: ntv2enums.h:2781
kRegMaskMRStandard
@ kRegMaskMRStandard
Definition: ntv2publicinterface.h:2280
kVRegIsoConvertEnable
@ kVRegIsoConvertEnable
Definition: ntv2virtualregisters.h:119
kVRegTimeCodeIn5Delay
@ kVRegTimeCodeIn5Delay
Definition: ntv2virtualregisters.h:101
NTV2_XptDualLinkOut4Input
@ NTV2_XptDualLinkOut4Input
Definition: ntv2enums.h:2830
kVRegRGB10Endian
@ kVRegRGB10Endian
Definition: ntv2virtualregisters.h:58
kRegHDMIInputControl
@ kRegHDMIInputControl
Definition: ntv2publicinterface.h:260
kVRegProcAmpStandardDefBrightness
@ kVRegProcAmpStandardDefBrightness
Definition: ntv2virtualregisters.h:198
kRegCS3Coefficients3_4
@ kRegCS3Coefficients3_4
Definition: ntv2publicinterface.h:434
kRegLTC4EmbeddedBits32_63
@ kRegLTC4EmbeddedBits32_63
Definition: ntv2publicinterface.h:468
kRegMaskStandard
@ kRegMaskStandard
Definition: ntv2publicinterface.h:1238
kRegSDIIn8VPIDA
@ kRegSDIIn8VPIDA
Definition: ntv2publicinterface.h:607
NTV2_XptCSC3VidInput
@ NTV2_XptCSC3VidInput
Definition: ntv2enums.h:2771
NTV2UpConvertMode
NTV2UpConvertMode
Definition: ntv2enums.h:2215
kK2RegMaskDeinterlaceMode
@ kK2RegMaskDeinterlaceMode
Definition: ntv2publicinterface.h:1701
ntv2utils.h
Declares numerous NTV2 utility functions.
kRegInputStatus2
@ kRegInputStatus2
Definition: ntv2publicinterface.h:429
NTV2_XptLUT8Input
@ NTV2_XptLUT8Input
Definition: ntv2enums.h:2790
kRegXptSelectGroup35
@ kRegXptSelectGroup35
Definition: ntv2publicinterface.h:705
kVRegFrameBufferGangCount
@ kVRegFrameBufferGangCount
Definition: ntv2virtualregisters.h:319
NTV2_XptFrameBuffer8DS2Input
@ NTV2_XptFrameBuffer8DS2Input
Definition: ntv2enums.h:2766
kRegXptSelectGroup21
@ kRegXptSelectGroup21
Definition: ntv2publicinterface.h:573
NTV2_XptMixer2FGVidInput
@ NTV2_XptMixer2FGVidInput
Definition: ntv2enums.h:2842
YesNo
#define YesNo(__x__)
Definition: ntv2registerexpert.h:25
NTV2DeviceCanDo3GLevelConversion
bool NTV2DeviceCanDo3GLevelConversion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:769
kVRegFrameBuffer1RGBRange
@ kVRegFrameBuffer1RGBRange
Definition: ntv2virtualregisters.h:133
kRegLTC2EmbeddedBits32_63
@ kRegLTC2EmbeddedBits32_63
Definition: ntv2publicinterface.h:394
regAncExtIgnorePacketReg_1_2_3_4
@ regAncExtIgnorePacketReg_1_2_3_4
Definition: ntv2publicinterface.h:5361
kRegLEDReserved0
@ kRegLEDReserved0
Definition: ntv2publicinterface.h:1085
kRegXptSelectGroup7
@ kRegXptSelectGroup7
Definition: ntv2publicinterface.h:301
kRegDMA1NextDesc
@ kRegDMA1NextDesc
Definition: ntv2publicinterface.h:156
kNumNTV4FrameStoreRegisters
static const ULWord kNumNTV4FrameStoreRegisters(regNTV4FS_REGISTER_COUNT)
kRegMaskVidProcMode
@ kRegMaskVidProcMode
Definition: ntv2publicinterface.h:1349
DisabEnab
#define DisabEnab(__x__)
Definition: ntv2registerexpert.h:30
kVRegNTV2VPIDTransferCharacteristics6
@ kVRegNTV2VPIDTransferCharacteristics6
Definition: ntv2virtualregisters.h:520
kRegShiftHDMIHDRMaxMasteringLuminance
@ kRegShiftHDMIHDRMaxMasteringLuminance
Definition: ntv2publicinterface.h:3274
kVRegAcquireReferenceCount
@ kVRegAcquireReferenceCount
Definition: ntv2virtualregisters.h:67
kRegInput56Status
@ kRegInput56Status
Definition: ntv2publicinterface.h:643
NTV2IsoConvertMode
NTV2IsoConvertMode
Definition: ntv2enums.h:2249
NTV2InputCrosspointID
NTV2InputCrosspointID
Identifies a widget input that potentially can accept a signal emitted from another widget's output (...
Definition: ntv2enums.h:2748
kRegMaskFramePulseRefSelect
@ kRegMaskFramePulseRefSelect
Definition: ntv2publicinterface.h:1292
kRegMask425FB78
@ kRegMask425FB78
Definition: ntv2publicinterface.h:1275
kRegClass_Routing
#define kRegClass_Routing
Definition: ntv2registerexpert.h:64
kVRegFanSpeed
@ kVRegFanSpeed
Definition: ntv2virtualregisters.h:345
kRegMaskSDIWatchdogEnable34
@ kRegMaskSDIWatchdogEnable34
Definition: ntv2publicinterface.h:2099
NTV2_UNUSED
#define NTV2_UNUSED(__p__)
Definition: ajatypes.h:185
kRegCSCoefficients7_8
@ kRegCSCoefficients7_8
Definition: ntv2publicinterface.h:280
kRegCS2Coefficients3_4
@ kRegCS2Coefficients3_4
Definition: ntv2publicinterface.h:284
kRegMaskPWMFanSpeedControl
@ kRegMaskPWMFanSpeedControl
Definition: ntv2publicinterface.h:2292
kVRegTimeStampLastInput4VerticalHi
@ kVRegTimeStampLastInput4VerticalHi
Definition: ntv2virtualregisters.h:271
kVRegPCIDeviceID
@ kVRegPCIDeviceID
Definition: ntv2virtualregisters.h:305
kVRegVideoFormatCh3
@ kVRegVideoFormatCh3
Definition: ntv2virtualregisters.h:349
kVRegDmaHardwareRateC2H2
@ kVRegDmaHardwareRateC2H2
Definition: ntv2virtualregisters.h:598
kRegClass_CSC
#define kRegClass_CSC
Definition: ntv2registerexpert.h:52
kRegBitfileDate
@ kRegBitfileDate
Definition: ntv2publicinterface.h:211
kRegMaskRP188ModeCh7
@ kRegMaskRP188ModeCh7
Definition: ntv2publicinterface.h:1280
gInstanceTally
static uint32_t gInstanceTally(0)
kRegStatus2
@ kRegStatus2
Definition: ntv2publicinterface.h:406
kRegBOBStatus
@ kRegBOBStatus
Definition: ntv2publicinterface.h:1076
kRegHDMIV2VActiveField1
@ kRegHDMIV2VActiveField1
Definition: ntv2publicinterface.h:531
kVRegAnalogIoSelect
@ kVRegAnalogIoSelect
Definition: ntv2virtualregisters.h:193
NTV2OutputXptIDSet
std::set< NTV2OutputXptID > NTV2OutputXptIDSet
A collection of distinct NTV2OutputXptID values.
Definition: ntv2signalrouter.h:18
DEVICE_ID_KONA5_8K_MV_TX
@ DEVICE_ID_KONA5_8K_MV_TX
See KONA 5.
Definition: ntv2enums.h:51
kRegCMW27Out
@ kRegCMW27Out
Definition: ntv2publicinterface.h:1100
kRegClass_ReadOnly
#define kRegClass_ReadOnly
Definition: ntv2registerexpert.h:63
kRegCS3Coefficients1_2
@ kRegCS3Coefficients1_2
Definition: ntv2publicinterface.h:433
NTV2_XptSDIOut1InputDS2
@ NTV2_XptSDIOut1InputDS2
Definition: ntv2enums.h:2796
kVRegTimeCodeCh6Delay
@ kVRegTimeCodeCh6Delay
Definition: ntv2virtualregisters.h:102
NTV2DeviceGetNumFrameStores
UWord NTV2DeviceGetNumFrameStores(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11420
kRegMask425FB34
@ kRegMask425FB34
Definition: ntv2publicinterface.h:1273
kVRegAudioOutputDelay
@ kVRegAudioOutputDelay
Definition: ntv2virtualregisters.h:172
kVRegHdrInBlueXCh1
@ kVRegHdrInBlueXCh1
Definition: ntv2virtualregisters.h:564
kVRegAudioMixerSourceMainGain
@ kVRegAudioMixerSourceMainGain
Definition: ntv2virtualregisters.h:474
kVRegHDMIOutStereoCodecSelect
@ kVRegHDMIOutStereoCodecSelect
Definition: ntv2virtualregisters.h:143
regAncInsFieldBytes
@ regAncInsFieldBytes
Definition: ntv2publicinterface.h:5385
kRegMaskMREnable
@ kRegMaskMREnable
Definition: ntv2publicinterface.h:2283
regAuxExtFieldVBLStartLine
@ regAuxExtFieldVBLStartLine
Definition: ntv2publicinterface.h:5463
NTV2RegisterNameString
const char * NTV2RegisterNameString(const ULWord inRegNum)
Definition: ntv2debug.cpp:1161
NTV2DeviceCanDoClockMonitor
bool NTV2DeviceCanDoClockMonitor(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2179
kVRegHdmiOutSubSample
@ kVRegHdmiOutSubSample
Definition: ntv2virtualregisters.h:144
kRegCS6Coefficients9_10
@ kRegCS6Coefficients9_10
Definition: ntv2publicinterface.h:650
kRegMaskQuadQuadMode2
@ kRegMaskQuadQuadMode2
Definition: ntv2publicinterface.h:1288
NTV2_XptFrameBuffer1DS2Input
@ NTV2_XptFrameBuffer1DS2Input
Definition: ntv2enums.h:2752
kRegMaskRefSource2
@ kRegMaskRefSource2
Definition: ntv2publicinterface.h:1253
kRegMaskMode
@ kRegMaskMode
Definition: ntv2publicinterface.h:1305
kVRegNTV2VPIDLuminance
@ kVRegNTV2VPIDLuminance
Definition: ntv2virtualregisters.h:502
NTV4FrameStoreRegs
NTV4FrameStoreRegs
Definition: ntv2registerexpert.cpp:51
NTV2_IS_VALID_HDR_PRIMARY
#define NTV2_IS_VALID_HDR_PRIMARY(__val__)
Definition: ntv2publicinterface.h:10343
kVRegNTV2VPIDLuminance6
@ kVRegNTV2VPIDLuminance6
Definition: ntv2virtualregisters.h:522
kRegMaskSDIRelayControl12
@ kRegMaskSDIRelayControl12
Definition: ntv2publicinterface.h:2096
NTV2WidgetID
NTV2WidgetID
Definition: ntv2enums.h:2905
kRegMaskHDMIHDRMaxContentLightLevel
@ kRegMaskHDMIHDRMaxContentLightLevel
Definition: ntv2publicinterface.h:2214
regAncInsPayloadID
@ regAncInsPayloadID
Definition: ntv2publicinterface.h:5395
kRegAud4Control
@ kRegAud4Control
Definition: ntv2publicinterface.h:420
kRegLTC3EmbeddedBits32_63
@ kRegLTC3EmbeddedBits32_63
Definition: ntv2publicinterface.h:465
kRegMaskAudioMixerMainInputEnable
@ kRegMaskAudioMixerMainInputEnable
Definition: ntv2publicinterface.h:2244
kVRegHdrBlueXCh1
@ kVRegHdrBlueXCh1
Definition: ntv2virtualregisters.h:541
kRegAud8SourceSelect
@ kRegAud8SourceSelect
Definition: ntv2publicinterface.h:635
kVRegTxcSfp1RemoteIp3
@ kVRegTxcSfp1RemoteIp3
Definition: ntv2virtualregisters.h:399
regNTV4FS_F1ActiveLines
@ regNTV4FS_F1ActiveLines
Definition: ntv2registerexpert.cpp:62
kVRegDmaTransferRateH2C4
@ kVRegDmaTransferRateH2C4
Definition: ntv2virtualregisters.h:607
kRegClass_Channel7
#define kRegClass_Channel7
Definition: ntv2registerexpert.h:50
regAncExtField1StartAddress
@ regAncExtField1StartAddress
Definition: ntv2publicinterface.h:5350
kVRegNTV2VPIDLuminance8
@ kVRegNTV2VPIDLuminance8
Definition: ntv2virtualregisters.h:530
kRegSDIOut8VPIDB
@ kRegSDIOut8VPIDB
Definition: ntv2publicinterface.h:610
kVRegRotaryGainOverrideEnable
@ kVRegRotaryGainOverrideEnable
Definition: ntv2virtualregisters.h:585
NTV2_Xpt425Mux3BInput
@ NTV2_Xpt425Mux3BInput
Definition: ntv2enums.h:2865
NTV2_XptHDMIOutQ1Input
@ NTV2_XptHDMIOutQ1Input
Definition: ntv2enums.h:2852
kRegSDIOut7VPIDB
@ kRegSDIOut7VPIDB
Definition: ntv2publicinterface.h:600
kRegAudioMixerMainInputLevelsPair0
@ kRegAudioMixerMainInputLevelsPair0
Definition: ntv2publicinterface.h:825
NTV2DeviceHasPWMFanControl
bool NTV2DeviceHasPWMFanControl(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7785
kRegDMAControl
@ kRegDMAControl
Definition: ntv2publicinterface.h:169
kVRegFrameBuffer1Stereo3DMode
@ kVRegFrameBuffer1Stereo3DMode
Definition: ntv2virtualregisters.h:134
kVRegUserInLuminance
@ kVRegUserInLuminance
Definition: ntv2virtualregisters.h:557
kRegSDIOut7Control
@ kRegSDIOut7Control
Definition: ntv2publicinterface.h:665
kRegAudioMixerMainOutputLevelsPair3
@ kRegAudioMixerMainOutputLevelsPair3
Definition: ntv2publicinterface.h:837
kRegOutputTimingControlch4
@ kRegOutputTimingControlch4
Definition: ntv2publicinterface.h:670
kVRegTxcSfp1RemoteIp4
@ kVRegTxcSfp1RemoteIp4
Definition: ntv2virtualregisters.h:407
RegisterExpertPtr
AJARefPtr< RegisterExpert > RegisterExpertPtr
Definition: ntv2registerexpert.cpp:109
kVRegMailBoxAcquire
@ kVRegMailBoxAcquire
Definition: ntv2virtualregisters.h:413
kVRegAnalogOutputType
@ kVRegAnalogOutputType
Definition: ntv2virtualregisters.h:47
kRegSDIWatchdogControlStatus
@ kRegSDIWatchdogControlStatus
Definition: ntv2publicinterface.h:457
kRegDMA3LocalAddr
@ kRegDMA3LocalAddr
Definition: ntv2publicinterface.h:162
kRegAud7Control
@ kRegAud7Control
Definition: ntv2publicinterface.h:629
kVRegSwizzle4kOutput
@ kVRegSwizzle4kOutput
Definition: ntv2virtualregisters.h:485
kVRegHDMIOutHDRRedPrimary2
@ kVRegHDMIOutHDRRedPrimary2
Definition: ntv2virtualregisters.h:651
kVRegNTV2VPIDTransferCharacteristics
@ kVRegNTV2VPIDTransferCharacteristics
Definition: ntv2virtualregisters.h:500
kRegCS4Coefficients5_6
@ kRegCS4Coefficients5_6
Definition: ntv2publicinterface.h:441
kRegShiftHDMIHDRBluePrimaryY
@ kRegShiftHDMIHDRBluePrimaryY
Definition: ntv2publicinterface.h:3269
kRegAud4OutputLastAddr
@ kRegAud4OutputLastAddr
Definition: ntv2publicinterface.h:426
kVRegLUTType
@ kVRegLUTType
Definition: ntv2virtualregisters.h:56
kRegAud5OutputLastAddr
@ kRegAud5OutputLastAddr
Definition: ntv2publicinterface.h:621
kRegRP188InOut1DBB
@ kRegRP188InOut1DBB
Definition: ntv2publicinterface.h:150
kVRegRxcSfp1DestPort2
@ kVRegRxcSfp1DestPort2
Definition: ntv2virtualregisters.h:386
kVRegTxcEnable3
@ kVRegTxcEnable3
Definition: ntv2virtualregisters.h:397
kRegAud5SourceSelect
@ kRegAud5SourceSelect
Definition: ntv2publicinterface.h:620
kVRegTimelapseIntervalValue
@ kVRegTimelapseIntervalValue
Definition: ntv2virtualregisters.h:176
kRegShiftAudioMixerMainInputEnable
@ kRegShiftAudioMixerMainInputEnable
Definition: ntv2publicinterface.h:3306
kVRegSDIInput2RGBRange
@ kVRegSDIInput2RGBRange
Definition: ntv2virtualregisters.h:130
kVRegProcAmpHighDefBrightness
@ kVRegProcAmpHighDefBrightness
Definition: ntv2virtualregisters.h:207
NTV2StringList
std::vector< std::string > NTV2StringList
Definition: ntv2utils.h:1155
kRegFlatMatte3Value
@ kRegFlatMatte3Value
Definition: ntv2publicinterface.h:678
kRegClass_Channel4
#define kRegClass_Channel4
Definition: ntv2registerexpert.h:47
kVRegHDMIOutHDRMasterLuminance4
@ kVRegHDMIOutHDRMasterLuminance4
Definition: ntv2virtualregisters.h:677
kVRegDTAudioMux0
@ kVRegDTAudioMux0
Definition: ntv2virtualregisters.h:70
kVRegAudioEncoderOutputEnable
@ kVRegAudioEncoderOutputEnable
Definition: ntv2virtualregisters.h:590
NTV2_XptLUT4Input
@ NTV2_XptLUT4Input
Definition: ntv2enums.h:2786
NTV2_XptBlack
@ NTV2_XptBlack
Definition: ntv2enums.h:2526
kVRegDmaTransferRateC2H4
@ kVRegDmaTransferRateC2H4
Definition: ntv2virtualregisters.h:605
kRegLEDHDMIOutControl
@ kRegLEDHDMIOutControl
Definition: ntv2publicinterface.h:1092
kRegSDIOut2Control
@ kRegSDIOut2Control
Definition: ntv2publicinterface.h:264
AJALock
Definition: lock.h:28
kRegAud1SourceSelect
@ kRegAud1SourceSelect
Definition: ntv2publicinterface.h:146
kVRegNTV2VPIDRGBRange3
@ kVRegNTV2VPIDRGBRange3
Definition: ntv2virtualregisters.h:578
NTV2_INPUT_CROSSPOINT_INVALID
@ NTV2_INPUT_CROSSPOINT_INVALID
Definition: ntv2enums.h:2885
kVRegNTV2VPIDTransferCharacteristics1
@ kVRegNTV2VPIDTransferCharacteristics1
Definition: ntv2virtualregisters.h:497
kRegSDIOut1VPIDA
@ kRegSDIOut1VPIDA
Definition: ntv2publicinterface.h:375
regNTV4FS_RasterOutputTimingPreset
@ regNTV4FS_RasterOutputTimingPreset
Definition: ntv2registerexpert.cpp:70
kRegLTCOutBits0_31
@ kRegLTCOutBits0_31
Definition: ntv2publicinterface.h:241
NTV2_XptFrameSync2Input
@ NTV2_XptFrameSync2Input
Definition: ntv2enums.h:2882
kVRegHDROverrideState
@ kVRegHDROverrideState
Definition: ntv2virtualregisters.h:551
NTV2_XptFrameBuffer4DS2Input
@ NTV2_XptFrameBuffer4DS2Input
Definition: ntv2enums.h:2758
kVRegNTV2VPIDLuminance7
@ kVRegNTV2VPIDLuminance7
Definition: ntv2virtualregisters.h:526
kRegDMA3HostAddrHigh
@ kRegDMA3HostAddrHigh
Definition: ntv2publicinterface.h:229
kVRegTimeStampLastInput5VerticalHi
@ kVRegTimeStampLastInput5VerticalHi
Definition: ntv2virtualregisters.h:273
kVRegHDMIInputControl4
@ kVRegHDMIInputControl4
Definition: ntv2virtualregisters.h:671
AJA_NULL
#define AJA_NULL
Definition: ajatypes.h:220
kRegXptSelectGroup16
@ kRegXptSelectGroup16
Definition: ntv2publicinterface.h:447
kVRegPCIMaxReadRequestSize
@ kVRegPCIMaxReadRequestSize
Definition: ntv2virtualregisters.h:553
kRegConversionControl
@ kRegConversionControl
Definition: ntv2publicinterface.h:265
kVRegHDMIOutHDRBluePrimary2
@ kVRegHDMIOutHDRBluePrimary2
Definition: ntv2virtualregisters.h:650
kVRegUseHDMI420Mode
@ kVRegUseHDMI420Mode
Definition: ntv2virtualregisters.h:460
kRegAud4SourceSelect
@ kRegAud4SourceSelect
Definition: ntv2publicinterface.h:422
kRegMaskAud2PlayCapMode
@ kRegMaskAud2PlayCapMode
Definition: ntv2publicinterface.h:1257
NTV2_IS_VALID_CHANNEL
#define NTV2_IS_VALID_CHANNEL(__x__)
Definition: ntv2enums.h:1367
kVRegTimeCodeCh4Delay
@ kVRegTimeCodeCh4Delay
Definition: ntv2virtualregisters.h:97
kRegAudioMixerMainOutputLevelsPair4
@ kRegAudioMixerMainOutputLevelsPair4
Definition: ntv2publicinterface.h:838
kRegMaskCC3OutputBankSelect
@ kRegMaskCC3OutputBankSelect
Definition: ntv2publicinterface.h:1448
kRegRP188InOut3Bits0_31_2
@ kRegRP188InOut3Bits0_31_2
Definition: ntv2publicinterface.h:347
kVRegHdrInMaxFALLCh1
@ kVRegHdrInMaxFALLCh1
Definition: ntv2virtualregisters.h:573
NTV2_XptSDIOut5Input
@ NTV2_XptSDIOut5Input
Definition: ntv2enums.h:2803
kRegSDIIn2VPIDB
@ kRegSDIIn2VPIDB
Definition: ntv2publicinterface.h:380
kVRegRP188SourceSelect
@ kVRegRP188SourceSelect
Definition: ntv2virtualregisters.h:163
kRegHDMIInputStatus
@ kRegHDMIInputStatus
Definition: ntv2publicinterface.h:259
kVRegAnalogOutBlackLevel
@ kVRegAnalogOutBlackLevel
Definition: ntv2virtualregisters.h:48
RegisterExpert::GetAllRegisterClasses
NTV2StringSet GetAllRegisterClasses(void) const
Definition: ntv2registerexpert.cpp:1877
kRegCh3OutputFrame
@ kRegCh3OutputFrame
Definition: ntv2publicinterface.h:399
regNTV4FS_RasterPixelSkip
@ regNTV4FS_RasterPixelSkip
Definition: ntv2registerexpert.cpp:65
kVRegTimeCodeIn6Delay
@ kVRegTimeCodeIn6Delay
Definition: ntv2virtualregisters.h:103
kRegMaskRP188ModeCh6
@ kRegMaskRP188ModeCh6
Definition: ntv2publicinterface.h:1279
kRegRP188InOut4Bits0_31_2
@ kRegRP188InOut4Bits0_31_2
Definition: ntv2publicinterface.h:349
AJALabelValuePairsConstIter
AJALabelValuePairs::const_iterator AJALabelValuePairsConstIter
Definition: info.h:72
kRegMRQ4Control
@ kRegMRQ4Control
Definition: ntv2publicinterface.h:1053
NTV2_AudioChannel5_6
@ NTV2_AudioChannel5_6
This selects audio channels 5 and 6 (Group 2 channels 1 and 2)
Definition: ntv2enums.h:3123
kRegDMA1XferCount
@ kRegDMA1XferCount
Definition: ntv2publicinterface.h:155
kRegMaskBOBAbsent
@ kRegMaskBOBAbsent
Definition: ntv2publicinterface.h:2297
NTV2OutputCrosspointID
NTV2OutputCrosspointID
Identifies a widget output, a signal source, that potentially can drive another widget's input (ident...
Definition: ntv2enums.h:2523
kVRegHDMIInDrmLightLevel1
@ kVRegHDMIInDrmLightLevel1
Definition: ntv2virtualregisters.h:616
kRegXptSelectGroup1
@ kRegXptSelectGroup1
Definition: ntv2publicinterface.h:270
kRegXptSelectGroup19
@ kRegXptSelectGroup19
Definition: ntv2publicinterface.h:518
kRegSDIOut6Control
@ kRegSDIOut6Control
Definition: ntv2publicinterface.h:664
kVRegTimeStampLastInput2VerticalLo
@ kVRegTimeStampLastInput2VerticalLo
Definition: ntv2virtualregisters.h:83
AJAAutoLock
Definition: lock.h:89
kRegStatus
@ kRegStatus
Definition: ntv2publicinterface.h:142
ntv2devicefeatures.hh
Declares NTV2DeviceCanDo... and NTV2DeviceGetNum... functions. This module is included at compile tim...
kRegCh7PCIAccessFrame
@ kRegCh7PCIAccessFrame
Definition: ntv2publicinterface.h:566
NTV2_XptDualLinkIn4Input
@ NTV2_XptDualLinkIn4Input
Definition: ntv2enums.h:2817
kRegVidProc1Control
@ kRegVidProc1Control
Definition: ntv2publicinterface.h:129
regAncExtField2AnalogYFilter
@ regAncExtField2AnalogYFilter
Definition: ntv2publicinterface.h:5370
kVRegHdrRedXCh1
@ kVRegHdrRedXCh1
Definition: ntv2virtualregisters.h:543
kRegAudioMixerMainInputLevelsPair6
@ kRegAudioMixerMainInputLevelsPair6
Definition: ntv2publicinterface.h:831
kVRegEnableBT2020
@ kVRegEnableBT2020
Definition: ntv2virtualregisters.h:491
kRegCSCoefficients3_4
@ kRegCSCoefficients3_4
Definition: ntv2publicinterface.h:278
kRegMaskSmpte372Enable6
@ kRegMaskSmpte372Enable6
Definition: ntv2publicinterface.h:1266
kRegSDI5678Input3GStatus
@ kRegSDI5678Input3GStatus
Definition: ntv2publicinterface.h:641
kVRegActiveVideoOutFilter
@ kVRegActiveVideoOutFilter
Definition: ntv2virtualregisters.h:155
regNTV4FS_RasterVideoFill_Cr_AR
@ regNTV4FS_RasterVideoFill_Cr_AR
Definition: ntv2registerexpert.cpp:67
kRegMask2MFrameSupport
@ kRegMask2MFrameSupport
Definition: ntv2publicinterface.h:1269
kRegSDIOut5VPIDA
@ kRegSDIOut5VPIDA
Definition: ntv2publicinterface.h:492
kVRegMacUserModeDebugLevel
@ kVRegMacUserModeDebugLevel
Definition: ntv2virtualregisters.h:241
kRegDMA1HostAddrHigh
@ kRegDMA1HostAddrHigh
Definition: ntv2publicinterface.h:225
kVRegTimeStampLastOutput2VerticalLo
@ kVRegTimeStampLastOutput2VerticalLo
Definition: ntv2virtualregisters.h:281
NTV2_XptSDIOut8Input
@ NTV2_XptSDIOut8Input
Definition: ntv2enums.h:2809
kRegAudioMixerMainInputLevelsPair2
@ kRegAudioMixerMainInputLevelsPair2
Definition: ntv2publicinterface.h:827
kVRegInputSelect
@ kVRegInputSelect
Definition: ntv2virtualregisters.h:42
NTV2_XptLUT5Input
@ NTV2_XptLUT5Input
Definition: ntv2enums.h:2787
kRegCSCoefficients1_2
@ kRegCSCoefficients1_2
Definition: ntv2publicinterface.h:277
kRegAudioMixerChannelSelect
@ kRegAudioMixerChannelSelect
Definition: ntv2publicinterface.h:816
kVRegAudioMixerSourceAux2Enable
@ kVRegAudioMixerSourceAux2Enable
Definition: ntv2virtualregisters.h:473
kVRegSuspendSystemAudio
@ kVRegSuspendSystemAudio
Definition: ntv2virtualregisters.h:311
kVRegRGBRangeConverterLUTType
@ kVRegRGBRangeConverterLUTType
Definition: ntv2virtualregisters.h:230
kRegCMWControl
@ kRegCMWControl
Definition: ntv2publicinterface.h:1097
kRegCPLDVersion
@ kRegCPLDVersion
Definition: ntv2publicinterface.h:184
kRegOutputTimingControlch2
@ kRegOutputTimingControlch2
Definition: ntv2publicinterface.h:668
kRegXptSelectGroup17
@ kRegXptSelectGroup17
Definition: ntv2publicinterface.h:445
kRegMaskAud3PlayCapMode
@ kRegMaskAud3PlayCapMode
Definition: ntv2publicinterface.h:1258
kRegCS7Coefficients7_8
@ kRegCS7Coefficients7_8
Definition: ntv2publicinterface.h:655
kRegLTC8EmbeddedBits0_31
@ kRegLTC8EmbeddedBits0_31
Definition: ntv2publicinterface.h:614
kVRegHdrMaxCLLCh1
@ kVRegHdrMaxCLLCh1
Definition: ntv2virtualregisters.h:549
ntv2bitfile.h
Declares the CNTV2Bitfile class.
kRegMROutControl
@ kRegMROutControl
Definition: ntv2publicinterface.h:1054
kVRegAudioMixerOverrideState
@ kVRegAudioMixerOverrideState
Definition: ntv2virtualregisters.h:470
regAuxExtControl
@ regAuxExtControl
Definition: ntv2publicinterface.h:5454
kRegEnhancedCSC1InOffset0_1
@ kRegEnhancedCSC1InOffset0_1
Definition: ntv2publicinterface.h:873
RegisterExpert::IsRegisterReadOnly
bool IsRegisterReadOnly(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1875
fDEC
#define fDEC(__x__, __w__, __p__)
Definition: ntv2publicinterface.h:5803
kRegMaskRP188ModeCh2
@ kRegMaskRP188ModeCh2
Definition: ntv2publicinterface.h:1249
regAncInsBlankCStartLine
@ regAncInsBlankCStartLine
Definition: ntv2publicinterface.h:5396
kVRegHDMIOutHDRLightLevel3
@ kVRegHDMIOutHDRLightLevel3
Definition: ntv2virtualregisters.h:666
kRegAud1Control
@ kRegAud1Control
Definition: ntv2publicinterface.h:145
kVRegProcAmpStandardDefCbOffset
@ kVRegProcAmpStandardDefCbOffset
Definition: ntv2virtualregisters.h:202
NTV2_XptCSC8KeyInput
@ NTV2_XptCSC8KeyInput
Definition: ntv2enums.h:2782
kVRegRxcSfp2SourcePort1
@ kVRegRxcSfp2SourcePort1
Definition: ntv2virtualregisters.h:375
kK2RegShiftConverterOutRate
@ kK2RegShiftConverterOutRate
Definition: ntv2publicinterface.h:2771
NTV2_XptMixer1FGVidInput
@ NTV2_XptMixer1FGVidInput
Definition: ntv2enums.h:2838
kRegDMA3XferCount
@ kRegDMA3XferCount
Definition: ntv2publicinterface.h:163
kVRegNTV2VPIDLuminance4
@ kVRegNTV2VPIDLuminance4
Definition: ntv2virtualregisters.h:514
AJAAtomic::Increment
static int32_t Increment(int32_t volatile *pTarget)
Definition: atomic.cpp:82
kVRegStartupStatusFlags
@ kVRegStartupStatusFlags
Definition: ntv2virtualregisters.h:252
kVRegTxcEnable4
@ kVRegTxcEnable4
Definition: ntv2virtualregisters.h:405
OddEven
#define OddEven(__x__)
Definition: ntv2registerexpert.h:29
kVRegKIPRxCfgError
@ kVRegKIPRxCfgError
Definition: ntv2virtualregisters.h:455
CNTV2RegisterExpert::GetRegistersForClass
static NTV2RegNumSet GetRegistersForClass(const std::string &inClassName)
Definition: ntv2registerexpert.cpp:4797
CNTV2SignalRouter::GetWidgetForOutput
static bool GetWidgetForOutput(const NTV2OutputXptID inOutputXpt, NTV2WidgetID &outWidgetID, const NTV2DeviceID inDeviceID=DEVICE_ID_NOTFOUND)
Returns the widget that "owns" the specified output crosspoint.
Definition: ntv2signalrouter.cpp:422
kRegPWMFanControl
@ kRegPWMFanControl
Definition: ntv2publicinterface.h:1070
NTV2_XptFrameBuffer8Input
@ NTV2_XptFrameBuffer8Input
Definition: ntv2enums.h:2765
kVRegNTV2VPIDColorimetry3
@ kVRegNTV2VPIDColorimetry3
Definition: ntv2virtualregisters.h:509
ntv2vpid.h
Declares the CNTV2VPID class. See SMPTE 352 standard for details.
regNTV4FS_DisplayFID
@ regNTV4FS_DisplayFID
Definition: ntv2registerexpert.cpp:61
kRegHDMIV2VSyncDurationAndBackPorchField2
@ kRegHDMIV2VSyncDurationAndBackPorchField2
Definition: ntv2publicinterface.h:530
NTV2_XptMixer4FGKeyInput
@ NTV2_XptMixer4FGKeyInput
Definition: ntv2enums.h:2849
kVRegFlashStatus
@ kVRegFlashStatus
Definition: ntv2virtualregisters.h:302
kVRegGammaMode
@ kVRegGammaMode
Definition: ntv2virtualregisters.h:55
kRegShiftCC4OutputBankSelect
@ kRegShiftCC4OutputBankSelect
Definition: ntv2publicinterface.h:2541
RegisterExpert::GetRegistersForDevice
NTV2RegNumSet GetRegistersForDevice(const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude) const
Definition: ntv2registerexpert.cpp:1914
NTV2_AudioChannel7_8
@ NTV2_AudioChannel7_8
This selects audio channels 7 and 8 (Group 2 channels 3 and 4)
Definition: ntv2enums.h:3124
kVRegDebug1
@ kVRegDebug1
Definition: ntv2virtualregisters.h:109
kRegRXSDIFreeRunningClockLow
@ kRegRXSDIFreeRunningClockLow
Definition: ntv2publicinterface.h:792
kVRegFirstOEM
@ kVRegFirstOEM
The first virtual register slot available for general use.
Definition: ntv2virtualregisters.h:742
kRegRP188InOut2Bits32_63
@ kRegRP188InOut2Bits32_63
Definition: ntv2publicinterface.h:187
NTV2DeviceHasSDIRelays
bool NTV2DeviceHasSDIRelays(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8067
kVRegTxcSfp2RemotePort3
@ kVRegTxcSfp2RemotePort3
Definition: ntv2virtualregisters.h:403
kVRegTxc_2EncodeStreamType1
@ kVRegTxc_2EncodeStreamType1
Definition: ntv2virtualregisters.h:434
NTV2_XptFrameSync1Input
@ NTV2_XptFrameSync1Input
Definition: ntv2enums.h:2883
kVRegTimeStampLastOutput7VerticalLo
@ kVRegTimeStampLastOutput7VerticalLo
Definition: ntv2virtualregisters.h:294
NTV2RegisterNumber
NTV2RegisterNumber
Definition: ntv2publicinterface.h:118
kRegSDIInput3GStatus2
@ kRegSDIInput3GStatus2
Definition: ntv2publicinterface.h:428
DEC
#define DEC(__x__)
Definition: ntv2publicinterface.h:5769
kVRegHdrMaxFALLCh1
@ kVRegHdrMaxFALLCh1
Definition: ntv2virtualregisters.h:550
NTV2_XptDualLinkIn6DSInput
@ NTV2_XptDualLinkIn6DSInput
Definition: ntv2enums.h:2822
NTV2_XptFrameBuffer2Input
@ NTV2_XptFrameBuffer2Input
Definition: ntv2enums.h:2753
kRegSDIOut1Control
@ kRegSDIOut1Control
Definition: ntv2publicinterface.h:262
kRegSDIOut3VPIDA
@ kRegSDIOut3VPIDA
Definition: ntv2publicinterface.h:412
kRegRP188InOut5Bits32_63_2
@ kRegRP188InOut5Bits32_63_2
Definition: ntv2publicinterface.h:352
NTV2DeviceIDString
const char * NTV2DeviceIDString(const NTV2DeviceID id)
Definition: ntv2debug.cpp:15
regAncInsField2StartAddr
@ regAncInsField2StartAddr
Definition: ntv2publicinterface.h:5388
regAuxExtPacketMask3
@ regAuxExtPacketMask3
Definition: ntv2publicinterface.h:5470
kRegShiftFramePulseRefSelect
@ kRegShiftFramePulseRefSelect
Definition: ntv2publicinterface.h:2383
NTV2DeviceHasXilinxDMA
bool NTV2DeviceHasXilinxDMA(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8347
regNTV4FS_RasterControl
@ regNTV4FS_RasterControl
Definition: ntv2registerexpert.cpp:64
NTV2_XptDualLinkIn8DSInput
@ NTV2_XptDualLinkIn8DSInput
Definition: ntv2enums.h:2826
NTV2OutputXptIDSetConstIter
NTV2OutputXptIDSet::const_iterator NTV2OutputXptIDSetConstIter
A const iterator for iterating over an NTV2OutputXptIDSet.
Definition: ntv2signalrouter.h:19
kRegMaskIndependentMode
@ kRegMaskIndependentMode
Definition: ntv2publicinterface.h:1268
kK2RegMaskUCPassLine21
@ kK2RegMaskUCPassLine21
Definition: ntv2publicinterface.h:1699
common.h
Private include file for all ajabase sources.
kRegHDMIV2VideoSetup
@ kRegHDMIV2VideoSetup
Definition: ntv2publicinterface.h:526
RegisterExpert::GetRegistersForClass
NTV2RegNumSet GetRegistersForClass(const string &inClassName) const
Definition: ntv2registerexpert.cpp:1904
NTV2UpConvertModeToString
std::string NTV2UpConvertModeToString(const NTV2UpConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6580
NTV2_XptMixer1BGVidInput
@ NTV2_XptMixer1BGVidInput
Definition: ntv2enums.h:2836
kVRegTimeStampLastInput5VerticalLo
@ kVRegTimeStampLastInput5VerticalLo
Definition: ntv2virtualregisters.h:272
kVRegDmaTransferRateH2C2
@ kVRegDmaTransferRateH2C2
Definition: ntv2virtualregisters.h:599
kVRegTimeStampLastOutput5VerticalLo
@ kVRegTimeStampLastOutput5VerticalLo
Definition: ntv2virtualregisters.h:289
kVRegDeviceOnline
@ kVRegDeviceOnline
Definition: ntv2virtualregisters.h:166
kVRegTimeCodeIn1Delay
@ kVRegTimeCodeIn1Delay
Definition: ntv2virtualregisters.h:94
kRegMaskBOBGPIIn4Data
@ kRegMaskBOBGPIIn4Data
Definition: ntv2publicinterface.h:2304
kRegHDMIHDRRedPrimary
@ kRegHDMIHDRRedPrimary
Definition: ntv2publicinterface.h:485
NTV2DriverVersionDecode_Minor
#define NTV2DriverVersionDecode_Minor(__vers__)
Definition: ntv2publicinterface.h:5555
kVRegTimeStampLastOutput5VerticalHi
@ kVRegTimeStampLastOutput5VerticalHi
Definition: ntv2virtualregisters.h:291
kRegRXSDI6Status
@ kRegRXSDI6Status
Definition: ntv2publicinterface.h:765
kRegMaskLEDBlueControl
@ kRegMaskLEDBlueControl
Definition: ntv2publicinterface.h:2320
kVRegZeroHostAncPostCapture
@ kVRegZeroHostAncPostCapture
Definition: ntv2virtualregisters.h:467
kRegPCMControl4321
@ kRegPCMControl4321
Definition: ntv2publicinterface.h:691
kRegEnhancedCSC1CoeffA0
@ kRegEnhancedCSC1CoeffA0
Definition: ntv2publicinterface.h:875
kVRegVideoFormatCh6
@ kVRegVideoFormatCh6
Definition: ntv2virtualregisters.h:352
kRegXptSelectGroup36
@ kRegXptSelectGroup36
Definition: ntv2publicinterface.h:312
kRegShiftHDMIInV2VideoStd
@ kRegShiftHDMIInV2VideoStd
Definition: ntv2publicinterface.h:2705
kVRegBA0MemorySize
@ kVRegBA0MemorySize
Definition: ntv2virtualregisters.h:257
kVRegHDMIOutRgbRange
@ kVRegHDMIOutRgbRange
Definition: ntv2virtualregisters.h:137
REiDBG
#define REiDBG(__x__)
Definition: ntv2registerexpert.cpp:40
kRegRXSDI2Status
@ kRegRXSDI2Status
Definition: ntv2publicinterface.h:729
kNTV4FrameStoreFirstRegNum
static const ULWord kNTV4FrameStoreFirstRegNum(0x0000D000/sizeof(ULWord))
regAncInsLinePixels
@ regAncInsLinePixels
Definition: ntv2publicinterface.h:5391
kVRegTxc_2EncodePcrPid1
@ kVRegTxc_2EncodePcrPid1
Definition: ntv2virtualregisters.h:437
NTV2_XptMixer3BGVidInput
@ NTV2_XptMixer3BGVidInput
Definition: ntv2enums.h:2844
kRegClass_Anc
#define kRegClass_Anc
Definition: ntv2registerexpert.h:41
kRegAudioMixerAux2InputLevels
@ kRegAudioMixerAux2InputLevels
Definition: ntv2publicinterface.h:824
kVRegHDMIOutStereoSelect
@ kVRegHDMIOutStereoSelect
Definition: ntv2virtualregisters.h:142
kRegClass_Channel8
#define kRegClass_Channel8
Definition: ntv2registerexpert.h:51
kVRegTimeStampLastInput6VerticalLo
@ kVRegTimeStampLastInput6VerticalLo
Definition: ntv2virtualregisters.h:274
HEX0N
#define HEX0N(__x__, __n__)
Definition: debug.cpp:1175
kRegCh6Control
@ kRegCh6Control
Definition: ntv2publicinterface.h:558
kVRegTimeStampLastInput1VerticalLo
@ kVRegTimeStampLastInput1VerticalLo
Definition: ntv2virtualregisters.h:81
kVRegDmaTransferRateC2H3
@ kVRegDmaTransferRateC2H3
Definition: ntv2virtualregisters.h:601
kVRegTimeStampLastOutput4VerticalLo
@ kVRegTimeStampLastOutput4VerticalLo
Definition: ntv2virtualregisters.h:286
kVRegFrameBuffer2RGBRange
@ kVRegFrameBuffer2RGBRange
Definition: ntv2virtualregisters.h:151
kVRegDigitalOutput4Select
@ kVRegDigitalOutput4Select
Definition: ntv2virtualregisters.h:228
kRegShiftHDMIHDRRedPrimaryY
@ kRegShiftHDMIHDRRedPrimaryY
Definition: ntv2publicinterface.h:3271
kK2RegShiftUCAutoLine21
@ kK2RegShiftUCAutoLine21
Definition: ntv2publicinterface.h:2778
NTV2FrameBufferFormatToString
std::string NTV2FrameBufferFormatToString(const NTV2FrameBufferFormat inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:6925
kVRegNTV2VPIDRGBRange6
@ kVRegNTV2VPIDRGBRange6
Definition: ntv2virtualregisters.h:581
NTV2_XptCSC7KeyInput
@ NTV2_XptCSC7KeyInput
Definition: ntv2enums.h:2780
NTV2RegisterWriteMode
NTV2RegisterWriteMode
These values are used to determine when certain register writes actually take effect....
Definition: ntv2enums.h:1675
kRegLTCInBits0_31
@ kRegLTCInBits0_31
Definition: ntv2publicinterface.h:243
kRegRP188InOut5Bits0_31_2
@ kRegRP188InOut5Bits0_31_2
Definition: ntv2publicinterface.h:351
kVRegSDIInput2ColorSpaceMode
@ kVRegSDIInput2ColorSpaceMode
Definition: ntv2virtualregisters.h:147
kVRegDMADriverBufferPhysicalAddress
@ kVRegDMADriverBufferPhysicalAddress
Definition: ntv2virtualregisters.h:261
kRegRP188InOut4DBB
@ kRegRP188InOut4DBB
Definition: ntv2publicinterface.h:414
kVRegAudioCapMixerSourceMainEnable
@ kVRegAudioCapMixerSourceMainEnable
Definition: ntv2virtualregisters.h:477
regAncExtAnalogStartLine
@ regAncExtAnalogStartLine
Definition: ntv2publicinterface.h:5368
kRegRXSDI3Status
@ kRegRXSDI3Status
Definition: ntv2publicinterface.h:738
kRegSDIOut1VPIDB
@ kRegSDIOut1VPIDB
Definition: ntv2publicinterface.h:376
kVRegHDMIInputStatus3
@ kVRegHDMIInputStatus3
Definition: ntv2virtualregisters.h:658
LOGGING_MAPPINGS
#define LOGGING_MAPPINGS
Definition: ntv2registerexpert.cpp:33
kVRegHDMIInDrmMasteringLuminence2
@ kVRegHDMIInDrmMasteringLuminence2
Definition: ntv2virtualregisters.h:623
kVRegTxc_2EncodeVideoFormat1
@ kVRegTxc_2EncodeVideoFormat1
Definition: ntv2virtualregisters.h:428
kVRegUserInColorimetry
@ kVRegUserInColorimetry
Definition: ntv2virtualregisters.h:555
NTV2_XptCompressionModInput
@ NTV2_XptCompressionModInput
Definition: ntv2enums.h:2879
NTV2_XptDualLinkOut3Input
@ NTV2_XptDualLinkOut3Input
Definition: ntv2enums.h:2829
kVRegAudioCapMixerSourceMainGain
@ kVRegAudioCapMixerSourceMainGain
Definition: ntv2virtualregisters.h:480
CNTV2RegisterExpert::GetAllRegisterClasses
static NTV2StringSet GetAllRegisterClasses(void)
Definition: ntv2registerexpert.cpp:4783
CNTV2RegisterExpert::Deallocate
static bool Deallocate(void)
Explicitly deallocates the Register Expert singleton.
Definition: ntv2registerexpert.cpp:4745
kRegMaskVidProcBGControl
@ kRegMaskVidProcBGControl
Definition: ntv2publicinterface.h:1348
kRegMaskRefSource
@ kRegMaskRefSource
Definition: ntv2publicinterface.h:1239
kVRegHdrLuminanceCh1
@ kVRegHdrLuminanceCh1
Definition: ntv2virtualregisters.h:538
kRegXptSelectGroup9
@ kRegXptSelectGroup9
Definition: ntv2publicinterface.h:391
kRegCh4Control
@ kRegCh4Control
Definition: ntv2publicinterface.h:401
DEF_REGNAME
#define DEF_REGNAME(_num_)
Definition: ntv2registerexpert.cpp:42
NTV2DeviceCanDoHDMIHDROut
bool NTV2DeviceCanDoHDMIHDROut(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:3118
kRegRP188InOut7Bits32_63_2
@ kRegRP188InOut7Bits32_63_2
Definition: ntv2publicinterface.h:356
kRegRP188InOut7Bits0_31_2
@ kRegRP188InOut7Bits0_31_2
Definition: ntv2publicinterface.h:355
NTV2DeviceHasBracketLED
bool NTV2DeviceHasBracketLED(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7020
kVRegTxcSfp2RemotePort4
@ kVRegTxcSfp2RemotePort4
Definition: ntv2virtualregisters.h:411
kVRegHdrRedYCh1
@ kVRegHdrRedYCh1
Definition: ntv2virtualregisters.h:544
kRegCh1OutputFrame
@ kRegCh1OutputFrame
Definition: ntv2publicinterface.h:123
kVRegQuicktimeUsingBoard
@ kVRegQuicktimeUsingBoard
Definition: ntv2virtualregisters.h:183
kVRegAudioEncoderHeadphoneEnable
@ kVRegAudioEncoderHeadphoneEnable
Definition: ntv2virtualregisters.h:591
kRegInputStatus
@ kRegInputStatus
Definition: ntv2publicinterface.h:143
std
Definition: json.hpp:5362
kVRegGatewayEth0
@ kVRegGatewayEth0
Definition: ntv2virtualregisters.h:359
kRegRP188InOut8Bits0_31_2
@ kRegRP188InOut8Bits0_31_2
Definition: ntv2publicinterface.h:357
kRegCS7Coefficients5_6
@ kRegCS7Coefficients5_6
Definition: ntv2publicinterface.h:654
NTV2DeviceCanDoBreakoutBoard
bool NTV2DeviceCanDoBreakoutBoard(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:1897
regAncInsBlankField2CLines
@ regAncInsBlankField2CLines
Definition: ntv2publicinterface.h:5398
kRegVidIntControl2
@ kRegVidIntControl2
Definition: ntv2publicinterface.h:407
kRegSplitControl
@ kRegSplitControl
Definition: ntv2publicinterface.h:132
kRegCMW12288Out
@ kRegCMW12288Out
Definition: ntv2publicinterface.h:1101
kRegBOBGPIInterruptControl
@ kRegBOBGPIInterruptControl
Definition: ntv2publicinterface.h:1078
kVRegHDMIOutHDRMasterLuminance3
@ kVRegHDMIOutHDRMasterLuminance3
Definition: ntv2virtualregisters.h:665
NTV2_XptFrameBuffer5DS2Input
@ NTV2_XptFrameBuffer5DS2Input
Definition: ntv2enums.h:2760
kRegCS2Coefficients7_8
@ kRegCS2Coefficients7_8
Definition: ntv2publicinterface.h:286
kRegFirstValidXptROMRegister
@ kRegFirstValidXptROMRegister
Definition: ntv2publicinterface.h:863
kRegXptSelectGroup24
@ kRegXptSelectGroup24
Definition: ntv2publicinterface.h:577
kRegSDIIn3VPIDB
@ kRegSDIIn3VPIDB
Definition: ntv2publicinterface.h:453
kVRegRxcSfp1DestPort1
@ kVRegRxcSfp1DestPort1
Definition: ntv2virtualregisters.h:370
kVRegKIPNetCfgError
@ kVRegKIPNetCfgError
Definition: ntv2virtualregisters.h:459
kRegFlatMatte4Value
@ kRegFlatMatte4Value
Definition: ntv2publicinterface.h:682
kVRegRxc_2DecodeProgramNumber1
@ kVRegRxc_2DecodeProgramNumber1
Definition: ntv2virtualregisters.h:419
kRegMaskSDIWatchdogStatus
@ kRegMaskSDIWatchdogStatus
Definition: ntv2publicinterface.h:2102
kVRegAudioMixerSourceAux1Gain
@ kVRegAudioMixerSourceAux1Gain
Definition: ntv2virtualregisters.h:475
NTV2_XptDualLinkIn5Input
@ NTV2_XptDualLinkIn5Input
Definition: ntv2enums.h:2819
kRegAud2InputLastAddr
@ kRegAud2InputLastAddr
Definition: ntv2publicinterface.h:384
kVRegHDMIInputControl3
@ kVRegHDMIInputControl3
Definition: ntv2virtualregisters.h:659
regNTV4FS_RasterOddLineStartAddress
@ regNTV4FS_RasterOddLineStartAddress
Definition: ntv2registerexpert.cpp:73
kVRegHDMIInDrmWhitePoint1
@ kVRegHDMIInDrmWhitePoint1
Definition: ntv2virtualregisters.h:614
kRegMaskDitherOn8BitInput
@ kRegMaskDitherOn8BitInput
Definition: ntv2publicinterface.h:1316
kRegSDIOut4VPIDA
@ kRegSDIOut4VPIDA
Definition: ntv2publicinterface.h:417
kVRegRxcSfp2Vlan1
@ kVRegRxcSfp2Vlan1
Definition: ntv2virtualregisters.h:377
kVRegReleaseLinuxReferenceCount
@ kVRegReleaseLinuxReferenceCount
Definition: ntv2virtualregisters.h:264
gpRegExpert
static RegisterExpertPtr gpRegExpert
Definition: ntv2registerexpert.cpp:4710
NTV2_XptSDIOut6Input
@ NTV2_XptSDIOut6Input
Definition: ntv2enums.h:2805
kVRegTimeCodeCh1Delay
@ kVRegTimeCodeCh1Delay
Definition: ntv2virtualregisters.h:92
kVRegDigitalOutput2Select
@ kVRegDigitalOutput2Select
Definition: ntv2virtualregisters.h:45
kRegClass_HDMI
#define kRegClass_HDMI
Definition: ntv2registerexpert.h:54
kVRegAudioCapMixerSourceAux1Gain
@ kVRegAudioCapMixerSourceAux1Gain
Definition: ntv2virtualregisters.h:481
NTV2_XptMixer2BGVidInput
@ NTV2_XptMixer2BGVidInput
Definition: ntv2enums.h:2840
NTV2RegisterWriteModeToString
std::string NTV2RegisterWriteModeToString(const NTV2RegisterWriteMode inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7438
kVRegNTV2VPIDColorimetry1
@ kVRegNTV2VPIDColorimetry1
Definition: ntv2virtualregisters.h:498
kRegXptSelectGroup29
@ kRegXptSelectGroup29
Definition: ntv2publicinterface.h:582
kRegGlobalControlCh2
@ kRegGlobalControlCh2
Definition: ntv2publicinterface.h:545
kVRegHDMIOutHDRControl2
@ kVRegHDMIOutHDRControl2
Definition: ntv2virtualregisters.h:655
kRegXptSelectGroup20
@ kRegXptSelectGroup20
Definition: ntv2publicinterface.h:520
kK2RegShiftIsoConvertMode
@ kK2RegShiftIsoConvertMode
Definition: ntv2publicinterface.h:2779
kRegCh7InputFrame
@ kRegCh7InputFrame
Definition: ntv2publicinterface.h:565
kRegRP188InOut1Bits32_63_2
@ kRegRP188InOut1Bits32_63_2
Definition: ntv2publicinterface.h:344
kRegXptSelectGroup4
@ kRegXptSelectGroup4
Definition: ntv2publicinterface.h:273
kRegClass_XptROM
#define kRegClass_XptROM
Definition: ntv2registerexpert.h:73
kVRegKIPEncCfgError
@ kVRegKIPEncCfgError
Definition: ntv2virtualregisters.h:457
kRegMaskHDMIHDRWhitePointY
@ kRegMaskHDMIHDRWhitePointY
Definition: ntv2publicinterface.h:2211
kRegMaskAnalogIOControl_14
@ kRegMaskAnalogIOControl_14
Definition: ntv2publicinterface.h:1285
kVRegETTDiagLastSerialTimecode
@ kVRegETTDiagLastSerialTimecode
Definition: ntv2virtualregisters.h:251
kRegVidProc2Control
@ kRegVidProc2Control
Definition: ntv2publicinterface.h:388
kVRegRxcSfp2DestPort1
@ kVRegRxcSfp2DestPort1
Definition: ntv2virtualregisters.h:376
NTV2_XptDualLinkIn6Input
@ NTV2_XptDualLinkIn6Input
Definition: ntv2enums.h:2821
kRegMaskFrameRate
@ kRegMaskFrameRate
Definition: ntv2publicinterface.h:1235
kRegCS8Coefficients5_6
@ kRegCS8Coefficients5_6
Definition: ntv2publicinterface.h:660
regAncIns_LAST
@ regAncIns_LAST
Definition: ntv2publicinterface.h:5404
regNTV4FS_ROIVHSize
@ regNTV4FS_ROIVHSize
Definition: ntv2registerexpert.cpp:55
kRegCh1ControlExtended
@ kRegCh1ControlExtended
Definition: ntv2publicinterface.h:303
regAncExtControl
@ regAncExtControl
Definition: ntv2publicinterface.h:5349
kRegShiftCCMode
@ kRegShiftCCMode
Definition: ntv2publicinterface.h:2535
kRegRP188InOut1Bits0_31_2
@ kRegRP188InOut1Bits0_31_2
Definition: ntv2publicinterface.h:343
kRegAudioMixerMainOutputLevelsPair1
@ kRegAudioMixerMainOutputLevelsPair1
Definition: ntv2publicinterface.h:835
RegisterExpert::RegNameToString
string RegNameToString(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1835
kRegSDIIn4VPIDA
@ kRegSDIIn4VPIDA
Definition: ntv2publicinterface.h:454
kVRegTxc_2EncodeUllMode2
@ kVRegTxc_2EncodeUllMode2
Definition: ntv2virtualregisters.h:441
kRegMaskFrameOrientation
@ kRegMaskFrameOrientation
Definition: ntv2publicinterface.h:1311
kRegCh6PCIAccessFrame
@ kRegCh6PCIAccessFrame
Definition: ntv2publicinterface.h:561
kRegHDMIV2VideoStatus
@ kRegHDMIV2VideoStatus
Definition: ntv2publicinterface.h:533
NTV2_XptDualLinkOut6Input
@ NTV2_XptDualLinkOut6Input
Definition: ntv2enums.h:2832
kVRegHDMIInputStatus4
@ kVRegHDMIInputStatus4
Definition: ntv2virtualregisters.h:670
kVRegXilinxProgramming
@ kVRegXilinxProgramming
Definition: ntv2virtualregisters.h:249
kRegShiftAudioMixerInputLeftLevel
@ kRegShiftAudioMixerInputLeftLevel
Definition: ntv2publicinterface.h:3331
kRegClass_Output
#define kRegClass_Output
Definition: ntv2registerexpert.h:62
NTV2FrameGeometry
NTV2FrameGeometry
Identifies a particular video frame geometry.
Definition: ntv2enums.h:344
NTV2_XptDualLinkOut2Input
@ NTV2_XptDualLinkOut2Input
Definition: ntv2enums.h:2828
kRegRP188InOut2Bits32_63_2
@ kRegRP188InOut2Bits32_63_2
Definition: ntv2publicinterface.h:346
kRegEnhancedCSC1CoeffA2
@ kRegEnhancedCSC1CoeffA2
Definition: ntv2publicinterface.h:877
kRegAud6Control
@ kRegAud6Control
Definition: ntv2publicinterface.h:624
kVRegTimeStampLastOutput6VerticalHi
@ kVRegTimeStampLastOutput6VerticalHi
Definition: ntv2virtualregisters.h:293
kVRegForceApplicationCode
@ kVRegForceApplicationCode
Definition: ntv2virtualregisters.h:188
kVRegTimeStampLastInput4VerticalLo
@ kVRegTimeStampLastInput4VerticalLo
Definition: ntv2virtualregisters.h:270
kRegLEDReserved3
@ kRegLEDReserved3
Definition: ntv2publicinterface.h:1088
kRegCSCoefficients5_6
@ kRegCSCoefficients5_6
Definition: ntv2publicinterface.h:279
kVRegHDMIOutHDRWhitePoint4
@ kVRegHDMIOutHDRWhitePoint4
Definition: ntv2virtualregisters.h:676
kVRegTxc_2EncodeMbps2
@ kVRegTxc_2EncodeMbps2
Definition: ntv2virtualregisters.h:444
kVRegSDIInput1Stereo3DMode
@ kVRegSDIInput1Stereo3DMode
Definition: ntv2virtualregisters.h:131
kRegAudioMixerMainOutputLevelsPair7
@ kRegAudioMixerMainOutputLevelsPair7
Definition: ntv2publicinterface.h:841
kRegMaskRP188ModeCh3
@ kRegMaskRP188ModeCh3
Definition: ntv2publicinterface.h:1276
kVRegTimeCodeIn3Delay
@ kVRegTimeCodeIn3Delay
Definition: ntv2virtualregisters.h:98
kVRegRxc_2DecodeSelectionMode2
@ kVRegRxc_2DecodeSelectionMode2
Definition: ntv2virtualregisters.h:423
kRegCS6Coefficients7_8
@ kRegCS6Coefficients7_8
Definition: ntv2publicinterface.h:649
kRegCh8PCIAccessFrame
@ kRegCh8PCIAccessFrame
Definition: ntv2publicinterface.h:571
kVRegTxcSfp1LocalPort3
@ kVRegTxcSfp1LocalPort3
Definition: ntv2virtualregisters.h:398
kRegBOBGPIOutData
@ kRegBOBGPIOutData
Definition: ntv2publicinterface.h:1079
NTV2_XptDualLinkIn4DSInput
@ NTV2_XptDualLinkIn4DSInput
Definition: ntv2enums.h:2818
true
#define true
Definition: ntv2devicefeatures.h:26
kVRegHdrWhiteYCh1
@ kVRegHdrWhiteYCh1
Definition: ntv2virtualregisters.h:546
NTV2_XptFrameBuffer6DS2Input
@ NTV2_XptFrameBuffer6DS2Input
Definition: ntv2enums.h:2762
kRegXptSelectGroup15
@ kRegXptSelectGroup15
Definition: ntv2publicinterface.h:446
NTV2_XptHDMIOutQ4Input
@ NTV2_XptHDMIOutQ4Input
Definition: ntv2enums.h:2855
kVRegTestPatternFormat
@ kVRegTestPatternFormat
Definition: ntv2virtualregisters.h:232
kVRegTxc_2EncodePcrPid2
@ kVRegTxc_2EncodePcrPid2
Definition: ntv2virtualregisters.h:449
kK2RegMaskFrameSize
@ kK2RegMaskFrameSize
Definition: ntv2publicinterface.h:1319
kVRegTxcSfp2RemoteIp3
@ kVRegTxcSfp2RemoteIp3
Definition: ntv2virtualregisters.h:402
RegisterExpert::IsRegInClass
bool IsRegInClass(const uint32_t inRegNum, const string &inClassName) const
Definition: ntv2registerexpert.cpp:1865
NTV2_XptOEInput
@ NTV2_XptOEInput
Definition: ntv2enums.h:2878
kRegCh1Control
@ kRegCh1Control
Definition: ntv2publicinterface.h:121
kRegMaskBOBGPIIn1InterruptControl
@ kRegMaskBOBGPIIn1InterruptControl
Definition: ntv2publicinterface.h:2306
kRegMRQ2Control
@ kRegMRQ2Control
Definition: ntv2publicinterface.h:1051
NTV2_Xpt425Mux4BInput
@ NTV2_Xpt425Mux4BInput
Definition: ntv2enums.h:2867
RegisterExpert
Definition: ntv2registerexpert.cpp:122
kVRegDisplayReferenceSelect
@ kVRegDisplayReferenceSelect
Definition: ntv2virtualregisters.h:114
kRegMaskAudioMixerOutputChannelsMute
@ kRegMaskAudioMixerOutputChannelsMute
Definition: ntv2publicinterface.h:2227
kRegShiftHDMIHDRMinMasteringLuminance
@ kRegShiftHDMIHDRMinMasteringLuminance
Definition: ntv2publicinterface.h:3275
kRegBOBAudioControl
@ kRegBOBAudioControl
Definition: ntv2publicinterface.h:1080
kVRegRxc_2DecodeProgramNumber2
@ kVRegRxc_2DecodeProgramNumber2
Definition: ntv2virtualregisters.h:424
kRegMaskHDMIHDRMaxFrameAverageLightLevel
@ kRegMaskHDMIHDRMaxFrameAverageLightLevel
Definition: ntv2publicinterface.h:2215
NTV2Audio4ChannelSelect
NTV2Audio4ChannelSelect
Identifies a contiguous, adjacent group of four audio channels.
Definition: ntv2enums.h:3259
kRegMixer2Coefficient
@ kRegMixer2Coefficient
Definition: ntv2publicinterface.h:389
kVRegTxcSfp2LocalPort4
@ kVRegTxcSfp2LocalPort4
Definition: ntv2virtualregisters.h:409
kRegClass_Audio
#define kRegClass_Audio
Definition: ntv2registerexpert.h:42
kVRegTimeStampLastInput7VerticalLo
@ kVRegTimeStampLastInput7VerticalLo
Definition: ntv2virtualregisters.h:276
kLHIRegShiftHDMIOutFPS
@ kLHIRegShiftHDMIOutFPS
Definition: ntv2publicinterface.h:2687
kRegCh7OutputFrame
@ kRegCh7OutputFrame
Definition: ntv2publicinterface.h:564
kRegMaskLEDRedControl
@ kRegMaskLEDRedControl
Definition: ntv2publicinterface.h:2322
kVRegAudioMixerSourceAux1Enable
@ kVRegAudioMixerSourceAux1Enable
Definition: ntv2virtualregisters.h:472
kVRegDmaHardwareRateH2C2
@ kVRegDmaHardwareRateH2C2
Definition: ntv2virtualregisters.h:600
kVRegHDMIOutHDRControl1
@ kVRegHDMIOutHDRControl1
Definition: ntv2virtualregisters.h:643
kRegMaskMonitorSource
@ kRegMaskMonitorSource
Definition: ntv2publicinterface.h:1971
kVRegHdrGreenXCh1
@ kVRegHdrGreenXCh1
Definition: ntv2virtualregisters.h:539
kVRegTxc_2EncodeAudioChannels2
@ kVRegTxc_2EncodeAudioChannels2
Definition: ntv2virtualregisters.h:445
kRegCS8Coefficients3_4
@ kRegCS8Coefficients3_4
Definition: ntv2publicinterface.h:659
kRegMaskAud4PlayCapMode
@ kRegMaskAud4PlayCapMode
Definition: ntv2publicinterface.h:1259
kRegMaskHDMIOutV2VideoStd
@ kRegMaskHDMIOutV2VideoStd
Definition: ntv2publicinterface.h:1594
kRegCh2ControlExtended
@ kRegCh2ControlExtended
Definition: ntv2publicinterface.h:304
kVRegFollowInputFormat
@ kVRegFollowInputFormat
Definition: ntv2virtualregisters.h:334
RegisterExpert::GetRegisterClasses
NTV2StringSet GetRegisterClasses(const uint32_t inRegNum, const bool inRemovePrefix) const
Definition: ntv2registerexpert.cpp:1887
kVRegTimeStampLastInput6VerticalHi
@ kVRegTimeStampLastInput6VerticalHi
Definition: ntv2virtualregisters.h:275
kRegCh4OutputFrame
@ kRegCh4OutputFrame
Definition: ntv2publicinterface.h:402
kVRegTxc_2EncodeChromaSubSamp1
@ kVRegTxc_2EncodeChromaSubSamp1
Definition: ntv2virtualregisters.h:431
kVRegHDMIInDrmInfo2
@ kVRegHDMIInDrmInfo2
Definition: ntv2virtualregisters.h:618
NTV2DeviceCanDoVersalSysMon
bool NTV2DeviceCanDoVersalSysMon(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:5894
kRegPWMFanStatus
@ kRegPWMFanStatus
Definition: ntv2publicinterface.h:1071
kVRegDmaTransferRateC2H2
@ kVRegDmaTransferRateC2H2
Definition: ntv2virtualregisters.h:597
kVRegRxc_2DecodeProgramPID2
@ kVRegRxc_2DecodeProgramPID2
Definition: ntv2virtualregisters.h:425
NTV2_XptFrameBuffer5Input
@ NTV2_XptFrameBuffer5Input
Definition: ntv2enums.h:2759
NTV2_XptHDMIOutQ2Input
@ NTV2_XptHDMIOutQ2Input
Definition: ntv2enums.h:2853
kVRegRxcEnable1
@ kVRegRxcEnable1
Definition: ntv2virtualregisters.h:365
kVRegHdrInMaxCLLCh1
@ kVRegHdrInMaxCLLCh1
Definition: ntv2virtualregisters.h:572
kRegLEDSDI2Control
@ kRegLEDSDI2Control
Definition: ntv2publicinterface.h:1090
kVRegHDMIInDrmRedPrimary2
@ kVRegHDMIInDrmRedPrimary2
Definition: ntv2virtualregisters.h:621
kRegVidIntControl
@ kRegVidIntControl
Definition: ntv2publicinterface.h:141
NTV2DeviceGetMaxRegisterNumber
ULWord NTV2DeviceGetMaxRegisterNumber(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:9653
kVRegNTV2VPIDTransferCharacteristics4
@ kVRegNTV2VPIDTransferCharacteristics4
Definition: ntv2virtualregisters.h:512
kRegLTC4EmbeddedBits0_31
@ kRegLTC4EmbeddedBits0_31
Definition: ntv2publicinterface.h:467
kVRegHDMIOutHDRGreenPrimary1
@ kVRegHDMIOutHDRGreenPrimary1
Definition: ntv2virtualregisters.h:637
kVRegDmaTransferRateH2C3
@ kVRegDmaTransferRateH2C3
Definition: ntv2virtualregisters.h:603
kVRegOutputTimecodeOffset
@ kVRegOutputTimecodeOffset
Definition: ntv2virtualregisters.h:181
kVRegRxcSfp2SourcePort2
@ kVRegRxcSfp2SourcePort2
Definition: ntv2virtualregisters.h:391
kRegDMA1LocalAddr
@ kRegDMA1LocalAddr
Definition: ntv2publicinterface.h:154
kVRegServicesInitialized
@ kVRegServicesInitialized
Definition: ntv2virtualregisters.h:317
NTV2_Xpt425Mux4AInput
@ NTV2_Xpt425Mux4AInput
Definition: ntv2enums.h:2866
kRegEnhancedCSC1CoeffB1
@ kRegEnhancedCSC1CoeffB1
Definition: ntv2publicinterface.h:879
SetNotset
#define SetNotset(__x__)
Definition: ntv2registerexpert.h:27
kRegHDMIV2HBlankingMeasurements
@ kRegHDMIV2HBlankingMeasurements
Definition: ntv2publicinterface.h:535
regAuxExtFID
@ regAuxExtFID
Definition: ntv2publicinterface.h:5465
kRegMaskBOBGPIOut4Data
@ kRegMaskBOBGPIOut4Data
Definition: ntv2publicinterface.h:2314
kVRegMacKernelModeDebugLevel
@ kVRegMacKernelModeDebugLevel
Definition: ntv2virtualregisters.h:242
kVRegAgentCheck
@ kVRegAgentCheck
Definition: ntv2virtualregisters.h:338
kRegMaskSmpte372Enable8
@ kRegMaskSmpte372Enable8
Definition: ntv2publicinterface.h:1267
kRegXptSelectGroup11
@ kRegXptSelectGroup11
Definition: ntv2publicinterface.h:332
kRegRP188InOut5Bits0_31
@ kRegRP188InOut5Bits0_31
Definition: ntv2publicinterface.h:495
kVRegDmaHardwareRateH2C4
@ kVRegDmaHardwareRateH2C4
Definition: ntv2virtualregisters.h:608
kRegClass_Aux
#define kRegClass_Aux
Definition: ntv2registerexpert.h:43
kRegAud2OutputLastAddr
@ kRegAud2OutputLastAddr
Definition: ntv2publicinterface.h:383
kVRegRxcSsrc1
@ kVRegRxcSsrc1
Definition: ntv2virtualregisters.h:378
kRegRP188InOut8Bits32_63_2
@ kRegRP188InOut8Bits32_63_2
Definition: ntv2publicinterface.h:358
kVRegInputSelectUser
@ kVRegInputSelectUser
Definition: ntv2virtualregisters.h:49
NTV2OutputXptID
enum NTV2OutputCrosspointID NTV2OutputXptID
kRegCS4Coefficients1_2
@ kRegCS4Coefficients1_2
Definition: ntv2publicinterface.h:439
regAuxExtPacketMask2
@ regAuxExtPacketMask2
Definition: ntv2publicinterface.h:5469
kRegMaskVidProcSyncFail
@ kRegMaskVidProcSyncFail
Definition: ntv2publicinterface.h:1351
kVRegDSKForegroundFade
@ kVRegDSKForegroundFade
Definition: ntv2virtualregisters.h:122
NTV2DeviceGetNumVideoOutputs
UWord NTV2DeviceGetNumVideoOutputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:13013
kRegFirmwareUserID
@ kRegFirmwareUserID
Definition: ntv2publicinterface.h:336
kRegShiftHDMIHDRMaxFrameAverageLightLevel
@ kRegShiftHDMIHDRMaxFrameAverageLightLevel
Definition: ntv2publicinterface.h:3277
kRegSDITransmitControl
@ kRegSDITransmitControl
Definition: ntv2publicinterface.h:397
kVRegDynFirmwareUpdateCounts
@ kVRegDynFirmwareUpdateCounts
Definition: ntv2virtualregisters.h:628
kRegAud2SourceSelect
@ kRegAud2SourceSelect
Definition: ntv2publicinterface.h:382
regAncInsFieldIDLines
@ regAncInsFieldIDLines
Definition: ntv2publicinterface.h:5393
kVRegBaseFirmwareDeviceID
@ kVRegBaseFirmwareDeviceID
Definition: ntv2virtualregisters.h:625
NTV2_XptSDIOut7InputDS2
@ NTV2_XptSDIOut7InputDS2
Definition: ntv2enums.h:2808
NTV2DeviceCanDoCustomAnc
bool NTV2DeviceCanDoCustomAnc(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2273
RegisterExpert::~RegisterExpert
~RegisterExpert()
Definition: ntv2registerexpert.cpp:170
kVRegAudioMixerOutputGain
@ kVRegAudioMixerOutputGain
Definition: ntv2virtualregisters.h:586
kRegCh1InputFrame
@ kRegCh1InputFrame
Definition: ntv2publicinterface.h:124
kRegDMA2HostAddrHigh
@ kRegDMA2HostAddrHigh
Definition: ntv2publicinterface.h:227
kVRegNTV2VPIDRGBRange7
@ kVRegNTV2VPIDRGBRange7
Definition: ntv2virtualregisters.h:582
kVRegZeroDeviceAncPostCapture
@ kVRegZeroDeviceAncPostCapture
Definition: ntv2virtualregisters.h:468
kVRegUartRxFifoSize
@ kVRegUartRxFifoSize
Definition: ntv2virtualregisters.h:307
kVRegTimeCodeIn4Delay
@ kVRegTimeCodeIn4Delay
Definition: ntv2virtualregisters.h:99
NTV2_XptWaterMarker2Input
@ NTV2_XptWaterMarker2Input
Definition: ntv2enums.h:2876
kVRegTxcSfp1LocalPort4
@ kVRegTxcSfp1LocalPort4
Definition: ntv2virtualregisters.h:406
kRegCanDoStatus
@ kRegCanDoStatus
Definition: ntv2publicinterface.h:188
NTV2DriverVersionDecode_Build
#define NTV2DriverVersionDecode_Build(__vers__)
Definition: ntv2publicinterface.h:5557
regAncInsFieldBytesHigh
@ regAncInsFieldBytesHigh
Definition: ntv2publicinterface.h:5399
DEF_REG
#define DEF_REG(_num_, _dec_, _rw_, _c1_, _c2_, _c3_)
Definition: ntv2registerexpert.cpp:43
kRegLTCOutBits32_63
@ kRegLTCOutBits32_63
Definition: ntv2publicinterface.h:242
kVRegTimelapseIntervalUnits
@ kVRegTimelapseIntervalUnits
Definition: ntv2virtualregisters.h:177
kVRegNTV2VPIDTransferCharacteristics5
@ kVRegNTV2VPIDTransferCharacteristics5
Definition: ntv2virtualregisters.h:516
kRegSDIOut8VPIDA
@ kRegSDIOut8VPIDA
Definition: ntv2publicinterface.h:609
kVRegTimeCodeCh8Delay
@ kVRegTimeCodeCh8Delay
Definition: ntv2virtualregisters.h:106
kVRegEnableQueuedDMAs
@ kVRegEnableQueuedDMAs
Definition: ntv2virtualregisters.h:254
kVRegQTCodecModeDebug
@ kVRegQTCodecModeDebug
Definition: ntv2virtualregisters.h:164
kRegClass_DMA
#define kRegClass_DMA
Definition: ntv2registerexpert.h:53
kRegSDIOut5VPIDB
@ kRegSDIOut5VPIDB
Definition: ntv2publicinterface.h:493
kRegEnhancedCSC1CoeffC0
@ kRegEnhancedCSC1CoeffC0
Definition: ntv2publicinterface.h:881
kRegMaskBOBADAV801Reset
@ kRegMaskBOBADAV801Reset
Definition: ntv2publicinterface.h:2316
kVRegHdrWhiteXCh1
@ kVRegHdrWhiteXCh1
Definition: ntv2virtualregisters.h:545
kRegRP188InOut7DBB
@ kRegRP188InOut7DBB
Definition: ntv2publicinterface.h:603
kVRegPulldownPattern
@ kVRegPulldownPattern
Definition: ntv2virtualregisters.h:53
kRegClass_AES
#define kRegClass_AES
Definition: ntv2registerexpert.h:39
regAncInsActiveStart
@ regAncInsActiveStart
Definition: ntv2publicinterface.h:5390
kRegAudioMixerMainInputLevelsPair3
@ kRegAudioMixerMainInputLevelsPair3
Definition: ntv2publicinterface.h:828
kVRegGatewayEth1
@ kVRegGatewayEth1
Definition: ntv2virtualregisters.h:363
kVRegHdrInWhiteYCh1
@ kVRegHdrInWhiteYCh1
Definition: ntv2virtualregisters.h:569
kVRegTxc_2EncodeVideoFormat2
@ kVRegTxc_2EncodeVideoFormat2
Definition: ntv2virtualregisters.h:440
kVRegTimelapseCaptureUnits
@ kVRegTimelapseCaptureUnits
Definition: ntv2virtualregisters.h:175
kRegCh5Control
@ kRegCh5Control
Definition: ntv2publicinterface.h:553
kVRegTimeStampMode
@ kVRegTimeStampMode
Definition: ntv2virtualregisters.h:78
kRegMaskBOBADAV801UpdateStatus
@ kRegMaskBOBADAV801UpdateStatus
Definition: ntv2publicinterface.h:2298
kRegCh1ColorCorrectionControl
@ kRegCh1ColorCorrectionControl
Definition: ntv2publicinterface.h:189
kVRegHdrInMasterLumMinCh1
@ kVRegHdrInMasterLumMinCh1
Definition: ntv2virtualregisters.h:571
kRegShiftElectroOpticalTransferFunction
@ kRegShiftElectroOpticalTransferFunction
Definition: ntv2publicinterface.h:3282
NTV2OutputCrosspointIDToString
std::string NTV2OutputCrosspointIDToString(const NTV2OutputCrosspointID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:5954
kVRegRxcPlayoutDelay2
@ kVRegRxcPlayoutDelay2
Definition: ntv2virtualregisters.h:395
kRegDMA2LocalAddr
@ kRegDMA2LocalAddr
Definition: ntv2publicinterface.h:158
RegisterExpert::GetInstance
static RegisterExpertPtr GetInstance(const bool inCreateIfNecessary=true)
Definition: ntv2registerexpert.cpp:4714
kRegEnhancedCSC1CoeffC1
@ kRegEnhancedCSC1CoeffC1
Definition: ntv2publicinterface.h:882
kVRegBA4MemorySize
@ kVRegBA4MemorySize
Definition: ntv2virtualregisters.h:259
kRegRP188InOut3Bits32_63
@ kRegRP188InOut3Bits32_63
Definition: ntv2publicinterface.h:411
kRegCh6InputFrame
@ kRegCh6InputFrame
Definition: ntv2publicinterface.h:560
kRegCh1PCIAccessFrame
@ kRegCh1PCIAccessFrame
Definition: ntv2publicinterface.h:122
CNTV2RegisterExpert::GetInputCrosspointID
static NTV2InputCrosspointID GetInputCrosspointID(const uint32_t inXptRegNum, const uint32_t inMaskIndex)
Definition: ntv2registerexpert.cpp:4825
regNTV4FS_RasterVTotalLines
@ regNTV4FS_RasterVTotalLines
Definition: ntv2registerexpert.cpp:71
kRegCS7Coefficients1_2
@ kRegCS7Coefficients1_2
Definition: ntv2publicinterface.h:652
kVRegReleaseReferenceCount
@ kVRegReleaseReferenceCount
Definition: ntv2virtualregisters.h:68
NTV2ReferenceSourceToString
std::string NTV2ReferenceSourceToString(const NTV2ReferenceSource inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7409
kVRegHdrInMasterLumMaxCh1
@ kVRegHdrInMasterLumMaxCh1
Definition: ntv2virtualregisters.h:570
kRegSDIOut2VPIDA
@ kRegSDIOut2VPIDA
Definition: ntv2publicinterface.h:377
kRegMaskRP188ModeCh8
@ kRegMaskRP188ModeCh8
Definition: ntv2publicinterface.h:1281
regAncExtField2StartAddress
@ regAncExtField2StartAddress
Definition: ntv2publicinterface.h:5352
RegisterExpert::RegValueToString
string RegValueToString(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
Definition: ntv2registerexpert.cpp:1852
kRegFlatMatte2Value
@ kRegFlatMatte2Value
Definition: ntv2publicinterface.h:390
kRegSDIOut7VPIDA
@ kRegSDIOut7VPIDA
Definition: ntv2publicinterface.h:599
kRegMaskSDIRelayPosition12
@ kRegMaskSDIRelayPosition12
Definition: ntv2publicinterface.h:2100
kRegLTC2AnalogBits0_31
@ kRegLTC2AnalogBits0_31
Definition: ntv2publicinterface.h:395
kRegShiftHDMIHDRRedPrimaryX
@ kRegShiftHDMIHDRRedPrimaryX
Definition: ntv2publicinterface.h:3270
kVRegDriverVersion
@ kVRegDriverVersion
Packed driver version – use NTV2DriverVersionEncode, NTV2DriverVersionDecode* macros to encode/decode...
Definition: ntv2virtualregisters.h:29
AJALabelValuePairs
std::vector< AJALabelValuePair > AJALabelValuePairs
An ordered sequence of label/value pairs.
Definition: info.h:71
regAuxExtTotalStatus
@ regAuxExtTotalStatus
Definition: ntv2publicinterface.h:5460
regAncInsControl
@ regAncInsControl
Definition: ntv2publicinterface.h:5386
kRegAudioMixerMainOutputLevelsPair2
@ kRegAudioMixerMainOutputLevelsPair2
Definition: ntv2publicinterface.h:836
BIT
#define BIT(_x_)
Definition: ajatypes.h:585
kVRegTimeStampLastInput3VerticalLo
@ kVRegTimeStampLastInput3VerticalLo
Definition: ntv2virtualregisters.h:268
xHEX0N
#define xHEX0N(__x__, __n__)
Definition: ntv2publicinterface.h:5768
kRegOutputTimingControl
@ kRegOutputTimingControl
Definition: ntv2publicinterface.h:134
NTV2AudioSystem
NTV2AudioSystem
Used to identify an Audio System on an NTV2 device. See Audio System Operation for more information.
Definition: ntv2enums.h:3880
kVRegRxcSfp1RxMatch1
@ kVRegRxcSfp1RxMatch1
Definition: ntv2virtualregisters.h:366
kRegCS5Coefficients5_6
@ kRegCS5Coefficients5_6
Definition: ntv2publicinterface.h:508
NTV2_AudioChannel1_2
@ NTV2_AudioChannel1_2
This selects audio channels 1 and 2 (Group 1 channels 1 and 2)
Definition: ntv2enums.h:3121
kRegDMAIntControl
@ kRegDMAIntControl
Definition: ntv2publicinterface.h:170
kRegEnhancedCSC1CoeffB0
@ kRegEnhancedCSC1CoeffB0
Definition: ntv2publicinterface.h:878
kVRegSDIInput1ColorSpaceMode
@ kVRegSDIInput1ColorSpaceMode
Definition: ntv2virtualregisters.h:145
kVRegDSKGraphicFileIndex
@ kVRegDSKGraphicFileIndex
Definition: ntv2virtualregisters.h:159
NTV2_XptMixer1BGKeyInput
@ NTV2_XptMixer1BGKeyInput
Definition: ntv2enums.h:2835
kVRegHDMIOutColorSpaceModeCtrl
@ kVRegHDMIOutColorSpaceModeCtrl
Definition: ntv2virtualregisters.h:140
NTV2_XptCSC5VidInput
@ NTV2_XptCSC5VidInput
Definition: ntv2enums.h:2775
kRegShiftHDMIHDRBluePrimaryX
@ kRegShiftHDMIHDRBluePrimaryX
Definition: ntv2publicinterface.h:3268
kRegSDIIn4VPIDB
@ kRegSDIIn4VPIDB
Definition: ntv2publicinterface.h:455
kVRegRxcSfp2RxMatch2
@ kVRegRxcSfp2RxMatch2
Definition: ntv2virtualregisters.h:388
kVRegLUT3Type
@ kVRegLUT3Type
Definition: ntv2virtualregisters.h:225
kRegXptSelectGroup18
@ kRegXptSelectGroup18
Definition: ntv2publicinterface.h:512
kRegAudioMixerMainGain
@ kRegAudioMixerMainGain
Definition: ntv2publicinterface.h:813
kVRegHDMIOutHDRControl4
@ kVRegHDMIOutHDRControl4
Definition: ntv2virtualregisters.h:679
kRegMaskRegClocking
@ kRegMaskRegClocking
Definition: ntv2publicinterface.h:1243
kRegXptSelectGroup23
@ kRegXptSelectGroup23
Definition: ntv2publicinterface.h:576
kVRegTxcSfp2RemoteIp4
@ kVRegTxcSfp2RemoteIp4
Definition: ntv2virtualregisters.h:410
NTV2_XptCSC2KeyInput
@ NTV2_XptCSC2KeyInput
Definition: ntv2enums.h:2770
kVRegRxc_2DecodeProgramPID1
@ kVRegRxc_2DecodeProgramPID1
Definition: ntv2virtualregisters.h:420
kRegLTCStatusControl
@ kRegLTCStatusControl
Definition: ntv2publicinterface.h:374
kRegCh8InputFrame
@ kRegCh8InputFrame
Definition: ntv2publicinterface.h:570
kVRegCustomAncInputSelect
@ kVRegCustomAncInputSelect
Definition: ntv2virtualregisters.h:342
kVRegDebugIPConfigTimeMS
@ kVRegDebugIPConfigTimeMS
Definition: ntv2virtualregisters.h:111
kVRegHdrMasterLumMinCh1
@ kVRegHdrMasterLumMinCh1
Definition: ntv2virtualregisters.h:548
kVRegDTVersionAja
@ kVRegDTVersionAja
Definition: ntv2virtualregisters.h:74
kVRegVideoFormatCh5
@ kVRegVideoFormatCh5
Definition: ntv2virtualregisters.h:351
kVRegRestoreHardwareProcampRegisters
@ kVRegRestoreHardwareProcampRegisters
Definition: ntv2virtualregisters.h:66
NTV2_XptFrameBuffer2DS2Input
@ NTV2_XptFrameBuffer2DS2Input
Definition: ntv2enums.h:2754
kVRegAudioInputSelect
@ kVRegAudioInputSelect
Definition: ntv2virtualregisters.h:247
NTV2FrameRateToString
std::string NTV2FrameRateToString(const NTV2FrameRate inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7335
kRegMaskVidProcFGControl
@ kRegMaskVidProcFGControl
Definition: ntv2publicinterface.h:1347
kRegMaskQuadMode2
@ kRegMaskQuadMode2
Definition: ntv2publicinterface.h:1264
ntv2registerexpert.h
Declares the CNTV2RegisterExpert class.
kVRegTimeCodeIn7Delay
@ kVRegTimeCodeIn7Delay
Definition: ntv2virtualregisters.h:105
kRegHDMIV2HBlankingMeasurements1
@ kRegHDMIV2HBlankingMeasurements1
Definition: ntv2publicinterface.h:536
ajarefptr.h
Defines the AJARefPtr template class.
kRegMaskAudioMixerInputRightLevel
@ kRegMaskAudioMixerInputRightLevel
Definition: ntv2publicinterface.h:2270
NTV2_XptCSC2VidInput
@ NTV2_XptCSC2VidInput
Definition: ntv2enums.h:2769
kRegCS7Coefficients3_4
@ kRegCS7Coefficients3_4
Definition: ntv2publicinterface.h:653
kRegShiftMonitorSource
@ kRegShiftMonitorSource
Definition: ntv2publicinterface.h:3036
kRegShiftHDMIOutAudioSource
@ kRegShiftHDMIOutAudioSource
Definition: ntv2publicinterface.h:3037
NTV2_XptAnalogOutInput
@ NTV2_XptAnalogOutInput
Definition: ntv2enums.h:2868
kRegMaskVidProcSplitStd
@ kRegMaskVidProcSplitStd
Definition: ntv2publicinterface.h:1352
kRegShiftAudioMixerAux1InputEnable
@ kRegShiftAudioMixerAux1InputEnable
Definition: ntv2publicinterface.h:3307
regNTV4FS_LAST
@ regNTV4FS_LAST
Definition: ntv2registerexpert.cpp:78
kVRegProcAmpStandardDefCrOffset
@ kVRegProcAmpStandardDefCrOffset
Definition: ntv2virtualregisters.h:203
kRegRP188InOut4Bits32_63_2
@ kRegRP188InOut4Bits32_63_2
Definition: ntv2publicinterface.h:350
kVRegDigitalOutput5Select
@ kVRegDigitalOutput5Select
Definition: ntv2virtualregisters.h:237
kRegMaskRP188ModeCh1
@ kRegMaskRP188ModeCh1
Definition: ntv2publicinterface.h:1248
kVReg8kOutputTransportSelection
@ kVReg8kOutputTransportSelection
Definition: ntv2virtualregisters.h:192
kVRegVideoFormatCh7
@ kVRegVideoFormatCh7
Definition: ntv2virtualregisters.h:353
kVRegHdrGreenYCh1
@ kVRegHdrGreenYCh1
Definition: ntv2virtualregisters.h:540
ActInact
#define ActInact(__x__)
Definition: ntv2registerexpert.h:31
kRegShiftCC3OutputBankSelect
@ kRegShiftCC3OutputBankSelect
Definition: ntv2publicinterface.h:2540
kRegMaskInputStatusFPS
@ kRegMaskInputStatusFPS
Definition: ntv2publicinterface.h:1630
kRegMaskRP188ModeCh4
@ kRegMaskRP188ModeCh4
Definition: ntv2publicinterface.h:1277
kVRegTimeStampLastOutput7VerticalHi
@ kVRegTimeStampLastOutput7VerticalHi
Definition: ntv2virtualregisters.h:295
kRegMaskInputStatusStd
@ kRegMaskInputStatusStd
Definition: ntv2publicinterface.h:1628
NTV2_XptLUT6Input
@ NTV2_XptLUT6Input
Definition: ntv2enums.h:2788
kVRegHDMIOutStatus4
@ kVRegHDMIOutStatus4
Definition: ntv2virtualregisters.h:672
kRegAud2Control
@ kRegAud2Control
Definition: ntv2publicinterface.h:381
kVRegMailBoxRelease
@ kVRegMailBoxRelease
Definition: ntv2virtualregisters.h:414
kVRegDefaultVideoFormat
@ kVRegDefaultVideoFormat
Definition: ntv2virtualregisters.h:236
kVRegDigitalOutput3Select
@ kVRegDigitalOutput3Select
Definition: ntv2virtualregisters.h:227
kVRegIPAddrEth0
@ kVRegIPAddrEth0
Definition: ntv2virtualregisters.h:357
kVRegTxc_2EncodeChromaSubSamp2
@ kVRegTxc_2EncodeChromaSubSamp2
Definition: ntv2virtualregisters.h:443
kVRegRxc_2DecodeAudioNumber2
@ kVRegRxc_2DecodeAudioNumber2
Definition: ntv2virtualregisters.h:426
kRegAud3Delay
@ kRegAud3Delay
Definition: ntv2publicinterface.h:449
NTV2_XptSDIOut1Input
@ NTV2_XptSDIOut1Input
Definition: ntv2enums.h:2795
kRegMixer3Coefficient
@ kRegMixer3Coefficient
Definition: ntv2publicinterface.h:677
kVRegSDIInConfig
@ kVRegSDIInConfig
Definition: ntv2virtualregisters.h:190
kRegLTC5EmbeddedBits32_63
@ kRegLTC5EmbeddedBits32_63
Definition: ntv2publicinterface.h:502
kRegRP188InOut8Bits0_31
@ kRegRP188InOut8Bits0_31
Definition: ntv2publicinterface.h:611
NTV2_XptCSC1KeyInput
@ NTV2_XptCSC1KeyInput
Definition: ntv2enums.h:2768
kVRegTxc_2EncodeMbps1
@ kVRegTxc_2EncodeMbps1
Definition: ntv2virtualregisters.h:432
NTV2_Xpt425Mux1BInput
@ NTV2_Xpt425Mux1BInput
Definition: ntv2enums.h:2861
kVRegHdrInWhiteXCh1
@ kVRegHdrInWhiteXCh1
Definition: ntv2virtualregisters.h:568
kVRegSDIOutput1ColorSpaceMode
@ kVRegSDIOutput1ColorSpaceMode
Definition: ntv2virtualregisters.h:170
kVRegHDMIOutHDRLightLevel2
@ kVRegHDMIOutHDRLightLevel2
Definition: ntv2virtualregisters.h:654
kRegAud6Delay
@ kRegAud6Delay
Definition: ntv2publicinterface.h:687
kRegHDMIHDRLightLevel
@ kRegHDMIHDRLightLevel
Definition: ntv2publicinterface.h:488
CNTV2RegisterExpert::GetDisplayValue
static std::string GetDisplayValue(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID=DEVICE_ID_NOTFOUND)
Definition: ntv2registerexpert.cpp:4769
kVRegHdrColorimetryCh1
@ kVRegHdrColorimetryCh1
Definition: ntv2virtualregisters.h:536
kRegAudioMixerMainInputLevelsPair4
@ kRegAudioMixerMainInputLevelsPair4
Definition: ntv2publicinterface.h:829
kVRegRxc_2DecodeSelectionMode1
@ kVRegRxc_2DecodeSelectionMode1
Definition: ntv2virtualregisters.h:418
kRegSDIOut8Control
@ kRegSDIOut8Control
Definition: ntv2publicinterface.h:666
kVRegSwizzle4kInput
@ kVRegSwizzle4kInput
Definition: ntv2virtualregisters.h:484
kVRegApplicationCode
@ kVRegApplicationCode
Definition: ntv2virtualregisters.h:185
kRegCh2ColorCorrectionControl
@ kRegCh2ColorCorrectionControl
Definition: ntv2publicinterface.h:190
kRegBitfileTime
@ kRegBitfileTime
Definition: ntv2publicinterface.h:212
kVRegNTV2VPIDRGBRange8
@ kVRegNTV2VPIDRGBRange8
Definition: ntv2virtualregisters.h:583
kRegSDIIn3VPIDA
@ kRegSDIIn3VPIDA
Definition: ntv2publicinterface.h:452
debug.h
Declares the AJADebug class.
kRegMaskBOBGPIOut3Data
@ kRegMaskBOBGPIOut3Data
Definition: ntv2publicinterface.h:2313
kVRegRxcSfp1SourceIp2
@ kVRegRxcSfp1SourceIp2
Definition: ntv2virtualregisters.h:383
NTV2_XptSDIOut6InputDS2
@ NTV2_XptSDIOut6InputDS2
Definition: ntv2enums.h:2806
kRegMaskAudioMixerAux2InputEnable
@ kRegMaskAudioMixerAux2InputEnable
Definition: ntv2publicinterface.h:2246
kRegMaskPWMFanSpeed
@ kRegMaskPWMFanSpeed
Definition: ntv2publicinterface.h:2291
RegisterExpert::GetInputCrosspointID
NTV2InputCrosspointID GetInputCrosspointID(const uint32_t inXptRegNum, const uint32_t inMaskIndex) const
Definition: ntv2registerexpert.cpp:2140
kK2RegShiftUpConvertMode
@ kK2RegShiftUpConvertMode
Definition: ntv2publicinterface.h:2772
kRegCS5Coefficients1_2
@ kRegCS5Coefficients1_2
Definition: ntv2publicinterface.h:506
AJAAtomic::Decrement
static int32_t Decrement(int32_t volatile *pTarget)
Definition: atomic.cpp:95
kVRegProcAmpEndHighDefRange
@ kVRegProcAmpEndHighDefRange
Definition: ntv2virtualregisters.h:214
NTV2_XptSDIOut3Input
@ NTV2_XptSDIOut3Input
Definition: ntv2enums.h:2799
kVRegRxcSfp1SourcePort2
@ kVRegRxcSfp1SourcePort2
Definition: ntv2virtualregisters.h:385
NTV2_XptDualLinkIn1DSInput
@ NTV2_XptDualLinkIn1DSInput
Definition: ntv2enums.h:2812
kRegRP188InOut6DBB
@ kRegRP188InOut6DBB
Definition: ntv2publicinterface.h:593
kVRegUserLuminance
@ kVRegUserLuminance
Definition: ntv2virtualregisters.h:534
kRegMaskFrameBufferMode
@ kRegMaskFrameBufferMode
Definition: ntv2publicinterface.h:1313
kRegMaskAud5PlayCapMode
@ kRegMaskAud5PlayCapMode
Definition: ntv2publicinterface.h:1260
kVRegRGBRangeMode
@ kVRegRGBRangeMode
Definition: ntv2virtualregisters.h:253
kRegPCMControl8765
@ kRegPCMControl8765
Definition: ntv2publicinterface.h:692
kVRegRxcSsrc2
@ kVRegRxcSsrc2
Definition: ntv2virtualregisters.h:394
NTV2_Xpt425Mux2AInput
@ NTV2_Xpt425Mux2AInput
Definition: ntv2enums.h:2862
sSpace
static const string sSpace(" ")
kVRegInput1UserBufferLevel
@ kVRegInput1UserBufferLevel
Definition: ntv2virtualregisters.h:219
kRegDMA2HostAddr
@ kRegDMA2HostAddr
Definition: ntv2publicinterface.h:157
kVRegTxc_2EncodeVideoPid2
@ kVRegTxc_2EncodeVideoPid2
Definition: ntv2virtualregisters.h:448
kRegCh3InputFrame
@ kRegCh3InputFrame
Definition: ntv2publicinterface.h:400
kVRegNumberVideoMappingRegisters
@ kVRegNumberVideoMappingRegisters
Definition: ntv2virtualregisters.h:85
kVRegAudioRecordPinDelay
@ kVRegAudioRecordPinDelay
Definition: ntv2virtualregisters.h:32
kRegCS7Coefficients9_10
@ kRegCS7Coefficients9_10
Definition: ntv2publicinterface.h:656
kVRegHDMIOutHDRBluePrimary1
@ kVRegHDMIOutHDRBluePrimary1
Definition: ntv2virtualregisters.h:638
kRegMaskBOBGPIOut1Data
@ kRegMaskBOBGPIOut1Data
Definition: ntv2publicinterface.h:2311
kRegAud1Detect
@ kRegAud1Detect
Definition: ntv2publicinterface.h:144
NTV2AudioSystemToString
std::string NTV2AudioSystemToString(const NTV2AudioSystem inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:5742
kRegMaskQuarterSizeMode
@ kRegMaskQuarterSizeMode
Definition: ntv2publicinterface.h:1312
kVRegTimeStampLastInput8VerticalHi
@ kVRegTimeStampLastInput8VerticalHi
Definition: ntv2virtualregisters.h:279
kRegMaskBOBGPIIn3Data
@ kRegMaskBOBGPIIn3Data
Definition: ntv2publicinterface.h:2303
NTV2_XptDualLinkOut1Input
@ NTV2_XptDualLinkOut1Input
Definition: ntv2enums.h:2827
kRegCSCoefficients9_10
@ kRegCSCoefficients9_10
Definition: ntv2publicinterface.h:281
kRegLTCInBits32_63
@ kRegLTCInBits32_63
Definition: ntv2publicinterface.h:244
kK2RegMaskConverterOutStandard
@ kK2RegMaskConverterOutStandard
Definition: ntv2publicinterface.h:1692
kRegAud7SourceSelect
@ kRegAud7SourceSelect
Definition: ntv2publicinterface.h:630
regAncExtFieldVBLStartLine
@ regAncExtFieldVBLStartLine
Definition: ntv2publicinterface.h:5358
kRegGlobalControl
@ kRegGlobalControl
Definition: ntv2publicinterface.h:120
kRegRP188InOut8DBB
@ kRegRP188InOut8DBB
Definition: ntv2publicinterface.h:613
kVRegDTAudioCapturePinConnected
@ kVRegDTAudioCapturePinConnected
Definition: ntv2virtualregisters.h:76
NTV2_XptCSC6VidInput
@ NTV2_XptCSC6VidInput
Definition: ntv2enums.h:2777
kVRegProcAmpHighDefCrOffset
@ kVRegProcAmpHighDefCrOffset
Definition: ntv2virtualregisters.h:213
NTV2_XptDualLinkOut8Input
@ NTV2_XptDualLinkOut8Input
Definition: ntv2enums.h:2834
kRegMaskVidProcFGMatteEnable
@ kRegMaskVidProcFGMatteEnable
Definition: ntv2publicinterface.h:1345
kVRegRxcSfp1SourcePort1
@ kVRegRxcSfp1SourcePort1
Definition: ntv2virtualregisters.h:369
regAuxExtField1Status
@ regAuxExtField1Status
Definition: ntv2publicinterface.h:5461