AJA NTV2 SDK  17.5.0.1242
NTV2 SDK 17.5.0.1242
ntv2registerexpert.cpp
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1 /* SPDX-License-Identifier: MIT */
7 #include "ntv2registerexpert.h"
8 #include "ntv2devicefeatures.hh"
9 #include "ntv2utils.h"
10 #include "ntv2debug.h"
11 #include "ntv2endian.h"
12 #include "ntv2vpid.h"
13 #include "ntv2bitfile.h"
14 #include "ntv2signalrouter.h"
15 #include "ajabase/common/common.h"
16 #include "ajabase/system/lock.h"
17 #include "ajabase/common/ajarefptr.h"
18 #include "ajabase/system/debug.h"
19 #include <algorithm>
20 #include <sstream>
21 #include <iterator>
22 #include <iomanip>
23 #include <map>
24 #include <math.h>
25 #include <ctype.h> // for isprint()
26 #if !defined(AJA_WINDOWS)
27 #include <unistd.h>
28 #endif
29 
30 
31 using namespace std;
32 
33 #define LOGGING_MAPPINGS (AJADebug::IsActive(AJA_DebugUnit_Enumeration))
34 #define HEX16(__x__) "0x" << hex << setw(16) << setfill('0') << uint64_t(__x__) << dec
35 #define INSTP(_p_) HEX16(uint64_t(_p_))
36 #define REiFAIL(__x__) AJA_sERROR (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
37 #define REiWARN(__x__) AJA_sWARNING(AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
38 #define REiNOTE(__x__) AJA_sNOTICE (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
39 #define REiINFO(__x__) AJA_sINFO (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
40 #define REiDBG(__x__) AJA_sDEBUG (AJA_DebugUnit_Enumeration, INSTP(this) << "::" << AJAFUNC << ": " << __x__)
41 
42 #define DEF_REGNAME(_num_) DefineRegName(_num_, #_num_)
43 #define DEF_REG(_num_, _dec_, _rw_, _c1_, _c2_, _c3_) DefineRegister((_num_), #_num_, _dec_, _rw_, _c1_, _c2_, _c3_)
44 
45 
46 static const string gChlClasses[] = { kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3, kRegClass_Channel4,
47  kRegClass_Channel5, kRegClass_Channel6, kRegClass_Channel7, kRegClass_Channel8 };
48 static const string sSpace(" ");
49 static const string sNull;
50 
51 typedef enum
52 {
53  regNTV4FS_FIRST,
54  regNTV4FS_LineLengthPitch = regNTV4FS_FIRST, // Reg 0 - Raster bytes/line[31:16] & pitch[15:0]
55  regNTV4FS_ROIVHSize, // Reg 1 - ROI size: vert[27:16] horz[11:0]
56  regNTV4FS_ROIF1StartAddr, // Reg 2 - ROI F1 start address [31:0]
57  regNTV4FS_ROIF2StartAddr, // Reg 3 - ROI F2 end address [31:0]
58  regNTV4FS_ROIF1VHOffsets, // Reg 4 - ROI F1 byte offsets: vert[26:16] horz[11:0]
59  regNTV4FS_ROIF2VHOffsets, // Reg 5 - ROI F2 byte offsets: vert[26:16] horz[11:0]
60  regNTV4FS_DisplayHorzPixelsPerLine, // Reg 6 - Horiz display: total[27:16] active[11:0]
61  regNTV4FS_DisplayFID, // Reg 7 - FID bit transition lines: FID lo[26:16] hi[10:0]
62  regNTV4FS_F1ActiveLines, // Reg 8 - Disp F1 active lines: end[26:16] start[10:0]
63  regNTV4FS_F2ActiveLines, // Reg 9 - Disp F2 active lines: end[26:16] start[10:0]
64  regNTV4FS_RasterControl, // Reg 10 - Control: sync[21:20] pixclk[18:16] pixfmt[12:8] p[6] rgb8cvt[5] dither[4] fill[3] DRT[2] disable[1] capture[0]
65  regNTV4FS_RasterPixelSkip, // Reg 11 - Raster pixel skip (or unpacker H offset?)
66  regNTV4FS_RasterVideoFill_YCb_GB, // Reg 12 - Raster video fill YorG[31:16] CbOrB[15:0]
67  regNTV4FS_RasterVideoFill_Cr_AR, // Reg 13 - Raster video fill A[31:16] CrOrR[15:0]
68  regNTV4FS_RasterROIFillAlpha, // Reg 14 - ROI Fill Alpha[15:0]
69  regNTV4FS_Status, // Reg 15 - Status lineCount[31:16] oddField[0]
70  regNTV4FS_RasterOutputTimingPreset, // Reg 16 - Output timing preset[23:0]
71  regNTV4FS_RasterVTotalLines, // Reg 17 - Total lines
72  regNTV4FS_RasterSmpteFramePulse, // Reg 18 - SMPTE frame pulse
73  regNTV4FS_RasterOddLineStartAddress, // Reg 19 - UHD odd line start addr | Green playback component offset (int12_t)
74  regNTV4FS_RasterOffsetBlue, // Reg 20 - Blue playback component offset[12:0] (int12_t)
75  regNTV4FS_RasterOffsetRed, // Reg 21 - Red playback component offset[12:0] (int12_t)
76  regNTV4FS_RasterOffsetAlpha, // Reg 22 - Alpha playback component offset[12:0] (int12_t)
77  regNTV4FS_InputSourceSelect = 63, // Reg 63 - Input source select[7:0]
78  regNTV4FS_LAST = regNTV4FS_InputSourceSelect,
79  regNTV4FS_REGISTER_COUNT
80 } NTV4FrameStoreRegs;
81 
82 static const std::string sNTV4FrameStoreRegNames[] = { "LineLengthPitch",
83  "ROIVHSize",
84  "ROIF1StartAddr",
85  "ROIF2StartAddr",
86  "ROIF1VHOffsets",
87  "ROIF2VHOffsets",
88  "DisplayHorzPixelsPerLine",
89  "DisplayFID",
90  "F1ActiveLines",
91  "F2ActiveLines",
92  "RasterControl",
93  "RasterPixelSkip",
94  "RasterVideoFill_YCb_GB",
95  "RasterVideoFill_Cr_AR",
96  "RasterROIFillAlpha",
97  "Status",
98  "RasterOutputTimingPreset",
99  "RasterVTotalLines",
100  "RasterSmpteFramePulse",
101  "RasterOddLineStartAddress",
102  "RasterOffsetBlue",
103  "RasterOffsetRed",
104  "RasterOffsetAlpha"};
105 static const ULWord kNTV4FrameStoreFirstRegNum (0x0000D000 / sizeof(ULWord)); // First FS reg num 13,312
106 static const ULWord kNumNTV4FrameStoreRegisters(regNTV4FS_REGISTER_COUNT); // 64 registers
107 
108 
109 class RegisterExpert;
110 typedef AJARefPtr<RegisterExpert> RegisterExpertPtr;
111 static uint32_t gInstanceTally(0);
112 static uint32_t gLivingInstances(0);
113 
114 
122 class RegisterExpert
123 {
124 public:
125  static RegisterExpertPtr GetInstance(const bool inCreateIfNecessary = true);
126  static bool DisposeInstance(void);
127 
128 private:
129  RegisterExpert()
130  {
131  AJAAutoLock lock(&mGuardMutex);
132  AJAAtomic::Increment(&gInstanceTally);
133  AJAAtomic::Increment(&gLivingInstances);
134  // Name "Classic" registers using NTV2RegisterNameString...
135  for (ULWord regNum (0); regNum < kRegNumRegisters; regNum++)
136  DefineRegName (regNum, ::NTV2RegisterNameString(regNum));
137  // Now the rest...
138  SetupBasicRegs(); // Basic registers
139  SetupVPIDRegs(); // VPIDs
140  SetupAncInsExt(); // Anc Ins/Ext
141  SetupAuxInsExt(); // Aux Ins/Ext
142  SetupXptSelect(); // Xpt Select
143  SetupDMARegs(); // DMA
144  SetupTimecodeRegs(); // Timecode
145  SetupAudioRegs(); // Audio
146  SetupMRRegs(); // MultiViewer/MultiRaster
147  SetupMixerKeyerRegs(); // Mixer/Keyer
148  SetupHDMIRegs(); // HDMI
149  SetupSDIErrorRegs(); // SDIError
150  SetupCSCRegs(); // CSCs
151  SetupLUTRegs(); // LUTs
152  SetupBOBRegs(); // Break Out Board
153  SetupLEDRegs(); // Bracket LEDs
154  SetupCMWRegs(); // Clock Monitor Out
155  SetupNTV4FrameStoreRegs(); // NTV4 FrameStores
156  SetupVRegs(); // Virtuals
157  REiNOTE(DEC(gLivingInstances) << " extant, " << DEC(gInstanceTally) << " total");
158  if (LOGGING_MAPPINGS)
159  {
160  REiDBG("RegsToStrsMap=" << mRegNumToStringMap.size()
161  << " RegsToDecodersMap=" << mRegNumToDecoderMap.size()
162  << " ClassToRegsMMap=" << mRegClassToRegNumMMap.size()
163  << " StrToRegsMMap=" << mStringToRegNumMMap.size()
164  << " InpXptsToXptRegInfoMap=" << mInputXpt2XptRegNumMaskIndexMap.size()
165  << " XptRegInfoToInpXptsMap=" << mXptRegNumMaskIndex2InputXptMap.size()
166  << " RegClasses=" << mAllRegClasses.size());
167  }
168  } // constructor
169 public:
170  ~RegisterExpert()
171  {
172  AJAAtomic::Decrement(&gLivingInstances);
173  REiNOTE(DEC(gLivingInstances) << " extant, " << DEC(gInstanceTally) << " total");
174  } // destructor
175 
176 private:
177  // This class implements a functor that returns a string that contains a human-readable decoding
178  // of a register value, given its number and the ID of the device it came from.
179  struct Decoder
180  {
181  // The default reg decoder functor returns an empty string.
182  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
183  {
184  (void) inRegNum;
185  (void) inRegValue;
186  (void) inDeviceID;
187  return string();
188  }
189  } mDefaultRegDecoder;
190 
191  void DefineRegName(const uint32_t regNumber, const string & regName)
192  {
193  if (!regName.empty())
194  {
195  AJAAutoLock lock(&mGuardMutex);
196  if (mRegNumToStringMap.find(regNumber) == mRegNumToStringMap.end())
197  {
198  mRegNumToStringMap.insert (RegNumToStringPair(regNumber, regName));
199  string lowerCaseRegName(regName);
200  mStringToRegNumMMap.insert (StringToRegNumPair(aja::lower(lowerCaseRegName), regNumber));
201  }
202  }
203  }
204  inline void DefineRegDecoder(const uint32_t inRegNum, const Decoder & dec)
205  {
206  AJAAutoLock lock(&mGuardMutex);
207  mRegNumToDecoderMap.insert (RegNumToDecoderPair(inRegNum, &dec));
208  }
209  inline void DefineRegClass (const uint32_t inRegNum, const string & className)
210  {
211  if (!className.empty())
212  {
213  AJAAutoLock lock(&mGuardMutex);
214  mRegClassToRegNumMMap.insert(StringToRegNumPair(className, inRegNum));
215  }
216  }
217  void DefineRegReadWrite(const uint32_t inRegNum, const int rdWrt)
218  {
219  AJAAutoLock lock(&mGuardMutex);
220  if (rdWrt == READONLY)
221  {
222  NTV2_ASSERT (!IsRegisterWriteOnly(inRegNum));
223  DefineRegClass (inRegNum, kRegClass_ReadOnly);
224  }
225  if (rdWrt == WRITEONLY)
226  {
227  NTV2_ASSERT (!IsRegisterReadOnly(inRegNum));
228  DefineRegClass (inRegNum, kRegClass_WriteOnly);
229  }
230  }
231  void DefineRegister(const uint32_t inRegNum, const string & regName, const Decoder & dec, const int rdWrt, const string & className1, const string & className2, const string & className3)
232  {
233  DefineRegName (inRegNum, regName);
234  DefineRegDecoder (inRegNum, dec);
235  DefineRegReadWrite (inRegNum, rdWrt);
236  DefineRegClass (inRegNum, className1);
237  DefineRegClass (inRegNum, className2);
238  DefineRegClass (inRegNum, className3);
239  }
240  void DefineXptReg(const uint32_t inRegNum, const NTV2InputXptID xpt0, const NTV2InputXptID xpt1, const NTV2InputXptID xpt2, const NTV2InputXptID xpt3)
241  {
242  DefineRegister (inRegNum, sNull, mDecodeXptGroupReg, READWRITE, kRegClass_Routing, kRegClass_NULL, kRegClass_NULL);
243  const NTV2InputCrosspointID indexes [4] = {xpt0, xpt1, xpt2, xpt3};
244  for (int ndx(0); ndx < 4; ndx++)
245  {
246  if (indexes[ndx] == NTV2_INPUT_CROSSPOINT_INVALID)
247  continue;
248  const XptRegNumAndMaskIndex regNumAndNdx(inRegNum, ndx);
249  if (mXptRegNumMaskIndex2InputXptMap.find(regNumAndNdx) == mXptRegNumMaskIndex2InputXptMap.end())
250  mXptRegNumMaskIndex2InputXptMap [regNumAndNdx] = indexes[ndx];
251  if (mInputXpt2XptRegNumMaskIndexMap.find(indexes[ndx]) == mInputXpt2XptRegNumMaskIndexMap.end())
252  mInputXpt2XptRegNumMaskIndexMap[indexes[ndx]] = regNumAndNdx;
253  }
254  }
255 
256  void SetupBasicRegs(void)
257  {
258  AJAAutoLock lock(&mGuardMutex);
259  DefineRegister (kRegGlobalControl, "", mDecodeGlobalControlReg, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
260  DefineRegister (kRegGlobalControl2, "", mDecodeGlobalControl2, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
261  DefineRegister (kRegGlobalControl3, "", mDecodeGlobalControl3, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
262  DefineRegister (kRegGlobalControlCh2, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
263  DefineRegister (kRegGlobalControlCh3, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
264  DefineRegister (kRegGlobalControlCh4, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
265  DefineRegister (kRegGlobalControlCh5, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
266  DefineRegister (kRegGlobalControlCh6, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
267  DefineRegister (kRegGlobalControlCh7, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
268  DefineRegister (kRegGlobalControlCh8, "", mDecodeGlobalControlChanRegs,READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
269  DefineRegister (kRegCh1Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
270  DefineRegister (kRegCh2Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
271  DefineRegister (kRegCh3Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
272  DefineRegister (kRegCh4Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
273  DefineRegister (kRegCh5Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
274  DefineRegister (kRegCh6Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
275  DefineRegister (kRegCh7Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
276  DefineRegister (kRegCh8Control, "", mDecodeChannelControl, READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
277  #if 1 // PCIAccessFrame regs are obsolete
278  DefineRegister (kRegCh1PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
279  DefineRegister (kRegCh2PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
280  DefineRegister (kRegCh3PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel3, kRegClass_NULL);
281  DefineRegister (kRegCh4PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel4, kRegClass_NULL);
282  DefineRegister (kRegCh5PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel5, kRegClass_NULL);
283  DefineRegister (kRegCh6PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel6, kRegClass_NULL);
284  DefineRegister (kRegCh7PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel7, kRegClass_NULL);
285  DefineRegister (kRegCh8PCIAccessFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel8, kRegClass_NULL);
286  #endif // PCIAccessFrame regs are obsolete
287  DefineRegister (kRegCh1InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel1, kRegClass_NULL);
288  DefineRegister (kRegCh2InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel2, kRegClass_NULL);
289  DefineRegister (kRegCh3InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel3, kRegClass_NULL);
290  DefineRegister (kRegCh4InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel4, kRegClass_NULL);
291  DefineRegister (kRegCh5InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel5, kRegClass_NULL);
292  DefineRegister (kRegCh6InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel6, kRegClass_NULL);
293  DefineRegister (kRegCh7InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel7, kRegClass_NULL);
294  DefineRegister (kRegCh8InputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Input, kRegClass_Channel8, kRegClass_NULL);
295  DefineRegister (kRegCh1OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
296  DefineRegister (kRegCh2OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
297  DefineRegister (kRegCh3OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
298  DefineRegister (kRegCh4OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
299  DefineRegister (kRegCh5OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
300  DefineRegister (kRegCh6OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
301  DefineRegister (kRegCh7OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
302  DefineRegister (kRegCh8OutputFrame, "", mDefaultRegDecoder, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
303  DefineRegister (kRegSDIOut1Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
304  DefineRegister (kRegSDIOut2Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
305  DefineRegister (kRegSDIOut3Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
306  DefineRegister (kRegSDIOut4Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
307  DefineRegister (kRegSDIOut5Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
308  DefineRegister (kRegSDIOut6Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
309  DefineRegister (kRegSDIOut7Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
310  DefineRegister (kRegSDIOut8Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
311  DefineRegister (kRegSDIOut6Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
312  DefineRegister (kRegSDIOut7Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
313  DefineRegister (kRegSDIOut8Control, "", mDecodeSDIOutputControl, READWRITE, kRegClass_Output, kRegClass_Channel8, kRegClass_NULL);
314 
315  DefineRegister (kRegOutputTimingControl, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel1, kRegClass_NULL);
316  DefineRegister (kRegOutputTimingControlch2, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel2, kRegClass_NULL);
317  DefineRegister (kRegOutputTimingControlch3, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel3, kRegClass_NULL);
318  DefineRegister (kRegOutputTimingControlch4, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel4, kRegClass_NULL);
319  DefineRegister (kRegOutputTimingControlch5, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel5, kRegClass_NULL);
320  DefineRegister (kRegOutputTimingControlch6, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel6, kRegClass_NULL);
321  DefineRegister (kRegOutputTimingControlch7, "", mDecodeSDIOutTimingCtrl,READWRITE, kRegClass_Output, kRegClass_Channel7, kRegClass_NULL);
322 
323  DefineRegister (kRegCh1ControlExtended, "", mDecodeChannelControlExt, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_NULL);
324  DefineRegister (kRegCh2ControlExtended, "", mDecodeChannelControlExt, READWRITE, kRegClass_NULL, kRegClass_Channel2, kRegClass_NULL);
325  DefineRegister (kRegBoardID, "", mDecodeBoardID, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
326  DefineRegister (kRegFirmwareUserID, "", mDecodeFirmwareUserID, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
327 
328  DefineRegister (kRegCanDoStatus, "", mDecodeCanDoStatus, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
329  DefineRegister (kRegBitfileDate, "", mDecodeBitfileDateTime, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
330  DefineRegister (kRegBitfileTime, "", mDecodeBitfileDateTime, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
331  DefineRegister (kRegCPLDVersion, "", mDecodeCPLDVersion, READONLY, kRegClass_Info, kRegClass_NULL, kRegClass_NULL);
332 
333  DefineRegister (kRegVidIntControl, "", mDecodeVidIntControl, READWRITE, kRegClass_Interrupt, kRegClass_Channel1, kRegClass_Channel2);
334  DefineRegClass (kRegVidIntControl, kRegClass_Channel3);
335  DefineRegClass (kRegVidIntControl, kRegClass_Channel4);
336  DefineRegister (kRegStatus, "", mDecodeStatusReg, READWRITE, kRegClass_Interrupt, kRegClass_Channel1, kRegClass_Channel2);
337  DefineRegClass (kRegStatus, kRegClass_Timecode);
338  DefineRegister (kRegVidIntControl2, "", mDecodeVidIntControl2, READWRITE, kRegClass_Interrupt, kRegClass_Channel5, kRegClass_Channel5);
339  DefineRegClass (kRegVidIntControl2, kRegClass_Channel7);
340  DefineRegClass (kRegVidIntControl2, kRegClass_Channel8);
341  DefineRegister (kRegStatus2, "", mDecodeStatus2Reg, READWRITE, kRegClass_Interrupt, kRegClass_Channel3, kRegClass_Channel4);
342  DefineRegClass (kRegStatus2, kRegClass_Channel5);
343  DefineRegClass (kRegStatus2, kRegClass_Channel6);
344  DefineRegClass (kRegStatus2, kRegClass_Channel7);
345  DefineRegClass (kRegStatus2, kRegClass_Channel8);
346  DefineRegister (kRegInputStatus, "", mDecodeInputStatusReg, READONLY, kRegClass_Input, kRegClass_Channel1, kRegClass_Channel2);
347  DefineRegClass (kRegInputStatus, kRegClass_Audio);
348  DefineRegister (kRegSDIInput3GStatus, "", mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel1, kRegClass_Channel2);
349  DefineRegister (kRegSDIInput3GStatus2, "", mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel3, kRegClass_Channel4);
350  DefineRegister (kRegSDI5678Input3GStatus,"",mDecodeSDIInputStatusReg, READWRITE, kRegClass_Input, kRegClass_Channel5, kRegClass_Channel6);
351  DefineRegClass (kRegSDI5678Input3GStatus, kRegClass_Channel7);
352  DefineRegClass (kRegSDI5678Input3GStatus, kRegClass_Channel8);
353  DefineRegister (kRegInputStatus2, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel3, kRegClass_Channel4); // 288
354  DefineRegister (kRegInput56Status, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel5, kRegClass_Channel6); // 458
355  DefineRegister (kRegInput78Status, "", mDecodeSDIInputStatus2Reg, READONLY, kRegClass_Input, kRegClass_Channel7, kRegClass_Channel8); // 459
356 
357  DefineRegister (kRegFS1ReferenceSelect, "", mDecodeFS1RefSelectReg, READWRITE, kRegClass_Input, kRegClass_Timecode, kRegClass_NULL);
358  DefineRegister (kRegSysmonVccIntDieTemp,"", mDecodeSysmonVccIntDieTemp, READONLY, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
359  DefineRegister (kRegSDITransmitControl, "", mDecodeSDITransmitCtrl, READWRITE, kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3);
360  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel4);
361  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel5);
362  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel6);
363  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel7);
364  DefineRegClass (kRegSDITransmitControl, kRegClass_Channel8);
365 
366  DefineRegister (kRegConversionControl, "", mConvControlRegDecoder, READWRITE, kRegClass_NULL, kRegClass_Channel1, kRegClass_Channel2);
367  DefineRegister (kRegSDIWatchdogControlStatus, "", mDecodeRelayCtrlStat, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
368  DefineRegister (kRegSDIWatchdogTimeout, "", mDecodeWatchdogTimeout, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
369  DefineRegister (kRegSDIWatchdogKick1, "", mDecodeWatchdogKick, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
370  DefineRegister (kRegSDIWatchdogKick2, "", mDecodeWatchdogKick, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
371  DefineRegister (kRegIDSwitch, "kRegIDSwitch", mDecodeIDSwitchStatus, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
372  DefineRegister (kRegPWMFanControl, "kRegPWMFanControl", mDecodePWMFanControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
373  DefineRegister (kRegPWMFanStatus, "kRegPWMFanStatus", mDecodePWMFanMonitor, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
374  }
375  void SetupBOBRegs(void)
376  {
377  AJAAutoLock lock(&mGuardMutex);
378  DefineRegister (kRegBOBStatus, "kRegBOBStatus", mDecodeBOBStatus, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
379  DefineRegister (kRegBOBGPIInData, "kRegBOBGPIInData", mDecodeBOBGPIIn, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
380  DefineRegister (kRegBOBGPIInterruptControl, "kRegBOBGPIInterruptControl", mDecodeBOBGPIInInterruptControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
381  DefineRegister (kRegBOBGPIOutData, "kRegBOBGPIOutData", mDecodeBOBGPIOut, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
382  DefineRegister (kRegBOBAudioControl, "kRegBOBAudioControl", mDecodeBOBAudioControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
383  }
384  void SetupLEDRegs(void)
385  {
386  AJAAutoLock lock(&mGuardMutex);
387  DefineRegister (kRegLEDReserved0, "kRegLEDReserved0", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
388  DefineRegister (kRegLEDClockDivide, "kRegLEDClockDivide", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
389  DefineRegister (kRegLEDReserved2, "kRegLEDReserved2", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
390  DefineRegister (kRegLEDReserved3, "kRegLEDReserved3", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
391  DefineRegister (kRegLEDSDI1Control, "kRegLEDSDI1Control", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
392  DefineRegister (kRegLEDSDI2Control, "kRegLEDSDI2Control", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
393  DefineRegister (kRegLEDHDMIInControl, "kRegLEDHDMIInControl", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
394  DefineRegister (kRegLEDHDMIOutControl, "kRegLEDHDMIOutControl", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
395  }
396  void SetupCMWRegs(void)
397  {
398  AJAAutoLock lock(&mGuardMutex);
399  DefineRegister (kRegCMWControl, "kRegCMWControl", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
400  DefineRegister (kRegCMW1485Out, "kRegCMW1485Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
401  DefineRegister (kRegCMW14835Out, "kRegCMW14835Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
402  DefineRegister (kRegCMW27Out, "kRegCMW27Out", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
403  DefineRegister (kRegCMW12288Out, "kRegCMW12288Out", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
404  DefineRegister (kRegCMWHDMIOut, "kRegCMWHDMIOut", mDecodeLEDControl, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
405  }
406  void SetupVPIDRegs(void)
407  {
408  AJAAutoLock lock(&mGuardMutex);
409  DefineRegister (kRegSDIIn1VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel1);
410  DefineRegister (kRegSDIIn1VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel1);
411  DefineRegister (kRegSDIOut1VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
412  DefineRegister (kRegSDIOut1VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
413  DefineRegister (kRegSDIOut2VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
414  DefineRegister (kRegSDIOut2VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel1);
415  DefineRegister (kRegSDIIn2VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel2);
416  DefineRegister (kRegSDIIn2VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel2);
417  DefineRegister (kRegSDIOut3VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel3);
418  DefineRegister (kRegSDIOut3VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel3);
419  DefineRegister (kRegSDIOut4VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel4);
420  DefineRegister (kRegSDIOut4VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel4);
421  DefineRegister (kRegSDIIn3VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel3);
422  DefineRegister (kRegSDIIn3VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel3);
423  DefineRegister (kRegSDIIn4VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel4);
424  DefineRegister (kRegSDIIn4VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel4);
425  DefineRegister (kRegSDIOut5VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel5);
426  DefineRegister (kRegSDIOut5VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel5);
427  DefineRegister (kRegSDIIn5VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel5);
428  DefineRegister (kRegSDIIn5VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel5);
429  DefineRegister (kRegSDIIn6VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel6);
430  DefineRegister (kRegSDIIn6VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel6);
431  DefineRegister (kRegSDIOut6VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel6);
432  DefineRegister (kRegSDIOut6VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel6);
433  DefineRegister (kRegSDIIn7VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel7);
434  DefineRegister (kRegSDIIn7VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel7);
435  DefineRegister (kRegSDIOut7VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel7);
436  DefineRegister (kRegSDIOut7VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel7);
437  DefineRegister (kRegSDIIn8VPIDA, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel8);
438  DefineRegister (kRegSDIIn8VPIDB, "", mVPIDInpRegDecoder, READONLY, kRegClass_VPID, kRegClass_Input, kRegClass_Channel8);
439  DefineRegister (kRegSDIOut8VPIDA, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel8);
440  DefineRegister (kRegSDIOut8VPIDB, "", mVPIDOutRegDecoder, READWRITE, kRegClass_VPID, kRegClass_Output, kRegClass_Channel8);
441  }
442  void SetupTimecodeRegs(void)
443  {
444  AJAAutoLock lock(&mGuardMutex);
445  DefineRegister (kRegRP188InOut1DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
446  DefineRegister (kRegRP188InOut1Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
447  DefineRegister (kRegRP188InOut1Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
448  DefineRegister (kRegRP188InOut2DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
449  DefineRegister (kRegRP188InOut2Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
450  DefineRegister (kRegRP188InOut2Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
451  DefineRegister (kRegLTCOutBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Output);
452  DefineRegister (kRegLTCOutBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Output);
453  DefineRegister (kRegLTCInBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Input);
454  DefineRegister (kRegLTCInBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_Input);
455  DefineRegister (kRegRP188InOut1Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
456  DefineRegister (kRegRP188InOut1Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel1, kRegClass_NULL);
457  DefineRegister (kRegRP188InOut2Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
458  DefineRegister (kRegRP188InOut2Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
459  DefineRegister (kRegRP188InOut3Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
460  DefineRegister (kRegRP188InOut3Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
461  DefineRegister (kRegRP188InOut4Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
462  DefineRegister (kRegRP188InOut4Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
463  DefineRegister (kRegRP188InOut5Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
464  DefineRegister (kRegRP188InOut5Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
465  DefineRegister (kRegRP188InOut6Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
466  DefineRegister (kRegRP188InOut6Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
467  DefineRegister (kRegRP188InOut7Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
468  DefineRegister (kRegRP188InOut7Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
469  DefineRegister (kRegRP188InOut8Bits0_31_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
470  DefineRegister (kRegRP188InOut8Bits32_63_2, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
471  DefineRegister (kRegLTCStatusControl, "", mLTCStatusControlDecoder, READWRITE, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
472  DefineRegister (kRegLTC2EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
473  DefineRegister (kRegLTC2EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel2, kRegClass_NULL);
474  DefineRegister (kRegLTC2AnalogBits0_31, "", mDefaultRegDecoder, READONLY, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
475  DefineRegister (kRegLTC2AnalogBits32_63, "", mDefaultRegDecoder, READONLY, kRegClass_Timecode, kRegClass_NULL, kRegClass_NULL);
476  DefineRegister (kRegRP188InOut3DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
477  DefineRegister (kRegRP188InOut3Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
478  DefineRegister (kRegRP188InOut3Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
479  DefineRegister (kRegRP188InOut4DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
480  DefineRegister (kRegRP188InOut4Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
481  DefineRegister (kRegRP188InOut4Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
482  DefineRegister (kRegLTC3EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
483  DefineRegister (kRegLTC3EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel3, kRegClass_NULL);
484  DefineRegister (kRegLTC4EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
485  DefineRegister (kRegLTC4EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel4, kRegClass_NULL);
486  DefineRegister (kRegRP188InOut5Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
487  DefineRegister (kRegRP188InOut5Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
488  DefineRegister (kRegRP188InOut5DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
489  DefineRegister (kRegLTC5EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
490  DefineRegister (kRegLTC5EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel5, kRegClass_NULL);
491  DefineRegister (kRegRP188InOut6Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
492  DefineRegister (kRegRP188InOut6Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
493  DefineRegister (kRegRP188InOut6DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
494  DefineRegister (kRegLTC6EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
495  DefineRegister (kRegLTC6EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel6, kRegClass_NULL);
496  DefineRegister (kRegRP188InOut7Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
497  DefineRegister (kRegRP188InOut7Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
498  DefineRegister (kRegRP188InOut7DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
499  DefineRegister (kRegLTC7EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
500  DefineRegister (kRegLTC7EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel7, kRegClass_NULL);
501  DefineRegister (kRegRP188InOut8Bits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
502  DefineRegister (kRegRP188InOut8Bits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
503  DefineRegister (kRegRP188InOut8DBB, "", mRP188InOutDBBRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
504  DefineRegister (kRegLTC8EmbeddedBits0_31, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
505  DefineRegister (kRegLTC8EmbeddedBits32_63, "", mDefaultRegDecoder, READWRITE, kRegClass_Timecode, kRegClass_Channel8, kRegClass_NULL);
506  } // SetupTimecodeRegs
507 
508  void SetupAudioRegs(void)
509  {
510  AJAAutoLock lock(&mGuardMutex);
511  DefineRegister (kRegAud1Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
512  DefineRegister (kRegAud2Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
513  DefineRegister (kRegAud3Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
514  DefineRegister (kRegAud4Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
515  DefineRegister (kRegAud5Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
516  DefineRegister (kRegAud6Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
517  DefineRegister (kRegAud7Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
518  DefineRegister (kRegAud8Control, "", mDecodeAudControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
519  DefineRegister (kRegAud1Detect, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel1, kRegClass_Channel2);
520  DefineRegister (kRegAudDetect2, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel3, kRegClass_Channel4);
521  DefineRegister (kRegAudioDetect5678, "", mDecodeAudDetectReg, READONLY, kRegClass_Audio, kRegClass_Channel8, kRegClass_Channel7);
522  DefineRegClass (kRegAudioDetect5678, kRegClass_Channel6);
523  DefineRegClass (kRegAudioDetect5678, kRegClass_Channel5);
524  DefineRegister (kRegAud1SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
525  DefineRegister (kRegAud2SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
526  DefineRegister (kRegAud3SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
527  DefineRegister (kRegAud4SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
528  DefineRegister (kRegAud5SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
529  DefineRegister (kRegAud6SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
530  DefineRegister (kRegAud7SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
531  DefineRegister (kRegAud8SourceSelect, "", mDecodeAudSourceSelectReg, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
532  DefineRegister (kRegAud1Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_NULL);
533  DefineRegister (kRegAud2Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_NULL);
534  DefineRegister (kRegAud3Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_NULL);
535  DefineRegister (kRegAud4Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_NULL);
536  DefineRegister (kRegAud5Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_NULL);
537  DefineRegister (kRegAud6Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_NULL);
538  DefineRegister (kRegAud7Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_NULL);
539  DefineRegister (kRegAud8Delay, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_NULL);
540  DefineRegister (kRegAud1OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Output);
541  DefineRegister (kRegAud2OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_Output);
542  DefineRegister (kRegAud3OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_Output);
543  DefineRegister (kRegAud4OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_Output);
544  DefineRegister (kRegAud5OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Output);
545  DefineRegister (kRegAud6OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_Output);
546  DefineRegister (kRegAud7OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_Output);
547  DefineRegister (kRegAud8OutputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_Output);
548  DefineRegister (kRegAud1InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Input);
549  DefineRegister (kRegAud2InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel2, kRegClass_Input);
550  DefineRegister (kRegAud3InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel3, kRegClass_Input);
551  DefineRegister (kRegAud4InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel4, kRegClass_Input);
552  DefineRegister (kRegAud5InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Input);
553  DefineRegister (kRegAud6InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel6, kRegClass_Input);
554  DefineRegister (kRegAud7InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel7, kRegClass_Input);
555  DefineRegister (kRegAud8InputLastAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Channel8, kRegClass_Input);
556  DefineRegister (kRegPCMControl4321, "", mDecodePCMControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel1, kRegClass_Channel2);
557  DefineRegClass (kRegPCMControl4321, kRegClass_Channel3);
558  DefineRegClass (kRegPCMControl4321, kRegClass_Channel4);
559  DefineRegister (kRegPCMControl8765, "", mDecodePCMControlReg, READWRITE, kRegClass_Audio, kRegClass_Channel5, kRegClass_Channel6);
560  DefineRegClass (kRegPCMControl8765, kRegClass_Channel7);
561  DefineRegClass (kRegPCMControl8765, kRegClass_Channel8);
562  DefineRegister (kRegAud1Counter, "", mDefaultRegDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
563  DefineRegister (kRegAudioOutputSourceMap,"",mDecodeAudOutputSrcMap, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_AES);
564  DefineRegClass (kRegAudioOutputSourceMap, kRegClass_HDMI);
565 
566  DefineRegister (kRegAudioMixerInputSelects, "kRegAudioMixerInputSelects", mAudMxrInputSelDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
567  DefineRegister (kRegAudioMixerMainGain, "kRegAudioMixerMainGain", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
568  DefineRegister (kRegAudioMixerAux1GainCh1, "kRegAudioMixerAux1GainCh1", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
569  DefineRegister (kRegAudioMixerAux2GainCh1, "kRegAudioMixerAux2GainCh1", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
570  DefineRegister (kRegAudioMixerChannelSelect, "kRegAudioMixerChannelSelect", mAudMxrChanSelDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
571  DefineRegister (kRegAudioMixerMutes, "kRegAudioMixerMutes", mAudMxrMutesDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
572  DefineRegister (kRegAudioMixerAux1GainCh2, "kRegAudioMixerAux1GainCh2", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
573  DefineRegister (kRegAudioMixerAux2GainCh2, "kRegAudioMixerAux2GainCh2", mAudMxrGainDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
574  DefineRegister (kRegAudioMixerAux1InputLevels, "kRegAudioMixerAux1InputLevels", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
575  DefineRegister (kRegAudioMixerAux2InputLevels, "kRegAudioMixerAux2InputLevels", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
576  DefineRegister (kRegAudioMixerMainInputLevelsPair0, "kRegAudioMixerMainInputLevelsPair0", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
577  DefineRegister (kRegAudioMixerMainInputLevelsPair1, "kRegAudioMixerMainInputLevelsPair1", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
578  DefineRegister (kRegAudioMixerMainInputLevelsPair2, "kRegAudioMixerMainInputLevelsPair2", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
579  DefineRegister (kRegAudioMixerMainInputLevelsPair3, "kRegAudioMixerMainInputLevelsPair3", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
580  DefineRegister (kRegAudioMixerMainInputLevelsPair4, "kRegAudioMixerMainInputLevelsPair4", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
581  DefineRegister (kRegAudioMixerMainInputLevelsPair5, "kRegAudioMixerMainInputLevelsPair5", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
582  DefineRegister (kRegAudioMixerMainInputLevelsPair6, "kRegAudioMixerMainInputLevelsPair6", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
583  DefineRegister (kRegAudioMixerMainInputLevelsPair7, "kRegAudioMixerMainInputLevelsPair7", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
584  DefineRegister (kRegAudioMixerMainOutputLevelsPair0, "kRegAudioMixerMainOutputLevelsPair0", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
585  DefineRegister (kRegAudioMixerMainOutputLevelsPair1, "kRegAudioMixerMainOutputLevelsPair1", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
586  DefineRegister (kRegAudioMixerMainOutputLevelsPair2, "kRegAudioMixerMainOutputLevelsPair2", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
587  DefineRegister (kRegAudioMixerMainOutputLevelsPair3, "kRegAudioMixerMainOutputLevelsPair3", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
588  DefineRegister (kRegAudioMixerMainOutputLevelsPair4, "kRegAudioMixerMainOutputLevelsPair4", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
589  DefineRegister (kRegAudioMixerMainOutputLevelsPair5, "kRegAudioMixerMainOutputLevelsPair5", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
590  DefineRegister (kRegAudioMixerMainOutputLevelsPair6, "kRegAudioMixerMainOutputLevelsPair6", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
591  DefineRegister (kRegAudioMixerMainOutputLevelsPair7, "kRegAudioMixerMainOutputLevelsPair7", mAudMxrLevelDecoder, READONLY, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
592  }
593 
594  void SetupMRRegs(void)
595  {
596  AJAAutoLock lock(&mGuardMutex);
597  DefineRegister (kRegMRQ1Control, "kRegMRQ1Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
598  DefineRegister (kRegMRQ2Control, "kRegMRQ2Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
599  DefineRegister (kRegMRQ3Control, "kRegMRQ3Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
600  DefineRegister (kRegMRQ4Control, "kRegMRQ4Control", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
601  DefineRegister (kRegMROutControl, "kRegMROutControl", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
602  DefineRegister (kRegMRSupport, "kRegMRSupport", mDefaultRegDecoder, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
603  }
604 
605  void SetupDMARegs(void)
606  {
607  AJAAutoLock lock(&mGuardMutex);
608  DefineRegister (kRegDMA1HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
609  DefineRegister (kRegDMA1HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
610  DefineRegister (kRegDMA1LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
611  DefineRegister (kRegDMA1XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
612  DefineRegister (kRegDMA1NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
613  DefineRegister (kRegDMA1NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
614  DefineRegister (kRegDMA2HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
615  DefineRegister (kRegDMA2HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
616  DefineRegister (kRegDMA2LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
617  DefineRegister (kRegDMA2XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
618  DefineRegister (kRegDMA2NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
619  DefineRegister (kRegDMA2NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
620  DefineRegister (kRegDMA3HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
621  DefineRegister (kRegDMA3HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
622  DefineRegister (kRegDMA3LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
623  DefineRegister (kRegDMA3XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
624  DefineRegister (kRegDMA3NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
625  DefineRegister (kRegDMA3NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
626  DefineRegister (kRegDMA4HostAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
627  DefineRegister (kRegDMA4HostAddrHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
628  DefineRegister (kRegDMA4LocalAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
629  DefineRegister (kRegDMA4XferCount, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
630  DefineRegister (kRegDMA4NextDesc, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
631  DefineRegister (kRegDMA4NextDescHigh, "", mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
632  DefineRegister (kRegDMAControl, "", mDMAControlRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
633  DefineRegister (kRegDMAIntControl, "", mDMAIntControlRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
634  }
635 
636  void SetupXptSelect(void)
637  {
638  AJAAutoLock lock(&mGuardMutex);
639  // RegNum 0-7 8-15 16-23 24-31
640  DefineXptReg (kRegXptSelectGroup1, NTV2_XptLUT1Input, NTV2_XptCSC1VidInput, NTV2_XptConversionModInput, NTV2_XptCompressionModInput);
641  DefineXptReg (kRegXptSelectGroup2, NTV2_XptFrameBuffer1Input, NTV2_XptFrameSync1Input, NTV2_XptFrameSync2Input, NTV2_XptDualLinkOut1Input);
642  DefineXptReg (kRegXptSelectGroup3, NTV2_XptAnalogOutInput, NTV2_XptSDIOut1Input, NTV2_XptSDIOut2Input, NTV2_XptCSC1KeyInput);
643  DefineXptReg (kRegXptSelectGroup4, NTV2_XptMixer1FGVidInput, NTV2_XptMixer1FGKeyInput, NTV2_XptMixer1BGVidInput, NTV2_XptMixer1BGKeyInput);
644  DefineXptReg (kRegXptSelectGroup5, NTV2_XptFrameBuffer2Input, NTV2_XptLUT2Input, NTV2_XptCSC2VidInput, NTV2_XptCSC2KeyInput);
645  DefineXptReg (kRegXptSelectGroup6, NTV2_XptWaterMarker1Input, NTV2_XptIICT1Input, NTV2_XptHDMIOutInput, NTV2_XptOEInput);
646  { // An additional input Xpt for kRegXptSelectGroup6 in mask index 2...
647  const XptRegNumAndMaskIndex regNumAndNdx (kRegXptSelectGroup6, 2);
648  if (mXptRegNumMaskIndex2InputXptMap.find (regNumAndNdx) == mXptRegNumMaskIndex2InputXptMap.end())
649  mXptRegNumMaskIndex2InputXptMap [regNumAndNdx] = NTV2_XptHDMIOutQ1Input;
650  if (mInputXpt2XptRegNumMaskIndexMap.find (NTV2_XptHDMIOutQ1Input) == mInputXpt2XptRegNumMaskIndexMap.end())
651  mInputXpt2XptRegNumMaskIndexMap[NTV2_XptHDMIOutQ1Input] = regNumAndNdx;
652  }
653  DefineXptReg (kRegXptSelectGroup7, NTV2_XptWaterMarker2Input, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptDualLinkOut2Input, NTV2_INPUT_CROSSPOINT_INVALID);
654  DefineXptReg (kRegXptSelectGroup8, NTV2_XptSDIOut3Input, NTV2_XptSDIOut4Input, NTV2_XptSDIOut5Input, NTV2_INPUT_CROSSPOINT_INVALID);
655  DefineXptReg (kRegXptSelectGroup9, NTV2_XptMixer2FGVidInput, NTV2_XptMixer2FGKeyInput, NTV2_XptMixer2BGVidInput, NTV2_XptMixer2BGKeyInput);
656  DefineXptReg (kRegXptSelectGroup10, NTV2_XptSDIOut1InputDS2, NTV2_XptSDIOut2InputDS2, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
657  DefineXptReg (kRegXptSelectGroup11, NTV2_XptDualLinkIn1Input, NTV2_XptDualLinkIn1DSInput, NTV2_XptDualLinkIn2Input, NTV2_XptDualLinkIn2DSInput);
658  DefineXptReg (kRegXptSelectGroup12, NTV2_XptLUT3Input, NTV2_XptLUT4Input, NTV2_XptLUT5Input, NTV2_Xpt3DLUT1Input);
659  DefineXptReg (kRegXptSelectGroup13, NTV2_XptFrameBuffer3Input, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptFrameBuffer4Input, NTV2_INPUT_CROSSPOINT_INVALID);
660  DefineXptReg (kRegXptSelectGroup14, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptSDIOut3InputDS2, NTV2_XptSDIOut5InputDS2, NTV2_XptSDIOut4InputDS2);
661  DefineXptReg (kRegXptSelectGroup15, NTV2_XptDualLinkIn3Input, NTV2_XptDualLinkIn3DSInput, NTV2_XptDualLinkIn4Input, NTV2_XptDualLinkIn4DSInput);
662  DefineXptReg (kRegXptSelectGroup16, NTV2_XptDualLinkOut3Input, NTV2_XptDualLinkOut4Input, NTV2_XptDualLinkOut5Input, NTV2_INPUT_CROSSPOINT_INVALID);
663  DefineXptReg (kRegXptSelectGroup17, NTV2_XptCSC3VidInput, NTV2_XptCSC3KeyInput, NTV2_XptCSC4VidInput, NTV2_XptCSC4KeyInput);
664  DefineXptReg (kRegXptSelectGroup18, NTV2_XptCSC5VidInput, NTV2_XptCSC5KeyInput, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
665  DefineXptReg (kRegXptSelectGroup19, NTV2_Xpt4KDCQ1Input, NTV2_Xpt4KDCQ2Input, NTV2_Xpt4KDCQ3Input, NTV2_Xpt4KDCQ4Input);
666  DefineXptReg (kRegXptSelectGroup20, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_XptHDMIOutQ2Input, NTV2_XptHDMIOutQ3Input, NTV2_XptHDMIOutQ4Input);
667  DefineXptReg (kRegXptSelectGroup21, NTV2_XptFrameBuffer5Input, NTV2_XptFrameBuffer6Input, NTV2_XptFrameBuffer7Input, NTV2_XptFrameBuffer8Input);
668  DefineXptReg (kRegXptSelectGroup22, NTV2_XptSDIOut6Input, NTV2_XptSDIOut6InputDS2, NTV2_XptSDIOut7Input, NTV2_XptSDIOut7InputDS2);
669  DefineXptReg (kRegXptSelectGroup23, NTV2_XptCSC7VidInput, NTV2_XptCSC7KeyInput, NTV2_XptCSC8VidInput, NTV2_XptCSC8KeyInput);
670  DefineXptReg (kRegXptSelectGroup24, NTV2_XptLUT6Input, NTV2_XptLUT7Input, NTV2_XptLUT8Input, NTV2_INPUT_CROSSPOINT_INVALID);
671  DefineXptReg (kRegXptSelectGroup25, NTV2_XptDualLinkIn5Input, NTV2_XptDualLinkIn5DSInput, NTV2_XptDualLinkIn6Input, NTV2_XptDualLinkIn6DSInput);
672  DefineXptReg (kRegXptSelectGroup26, NTV2_XptDualLinkIn7Input, NTV2_XptDualLinkIn7DSInput, NTV2_XptDualLinkIn8Input, NTV2_XptDualLinkIn8DSInput);
673  DefineXptReg (kRegXptSelectGroup27, NTV2_XptDualLinkOut6Input, NTV2_XptDualLinkOut7Input, NTV2_XptDualLinkOut8Input, NTV2_INPUT_CROSSPOINT_INVALID);
674  DefineXptReg (kRegXptSelectGroup28, NTV2_XptMixer3FGVidInput, NTV2_XptMixer3FGKeyInput, NTV2_XptMixer3BGVidInput, NTV2_XptMixer3BGKeyInput);
675  DefineXptReg (kRegXptSelectGroup29, NTV2_XptMixer4FGVidInput, NTV2_XptMixer4FGKeyInput, NTV2_XptMixer4BGVidInput, NTV2_XptMixer4BGKeyInput);
676  DefineXptReg (kRegXptSelectGroup30, NTV2_XptSDIOut8Input, NTV2_XptSDIOut8InputDS2, NTV2_XptCSC6VidInput, NTV2_XptCSC6KeyInput);
677  DefineXptReg (kRegXptSelectGroup32, NTV2_Xpt425Mux1AInput, NTV2_Xpt425Mux1BInput, NTV2_Xpt425Mux2AInput, NTV2_Xpt425Mux2BInput);
678  DefineXptReg (kRegXptSelectGroup33, NTV2_Xpt425Mux3AInput, NTV2_Xpt425Mux3BInput, NTV2_Xpt425Mux4AInput, NTV2_Xpt425Mux4BInput);
679  DefineXptReg (kRegXptSelectGroup34, NTV2_XptFrameBuffer1DS2Input, NTV2_XptFrameBuffer2DS2Input, NTV2_XptFrameBuffer3DS2Input, NTV2_XptFrameBuffer4DS2Input);
680  DefineXptReg (kRegXptSelectGroup35, NTV2_XptFrameBuffer5DS2Input, NTV2_XptFrameBuffer6DS2Input, NTV2_XptFrameBuffer7DS2Input, NTV2_XptFrameBuffer8DS2Input);
681  DefineXptReg (kRegXptSelectGroup36, NTV2_XptMultiLinkOut1Input, NTV2_XptMultiLinkOut1InputDS2, NTV2_INPUT_CROSSPOINT_INVALID, NTV2_INPUT_CROSSPOINT_INVALID);
682 
683 
684  // Expose the CanConnect ROM registers:
685  for (ULWord regNum(kRegFirstValidXptROMRegister); regNum < ULWord(kRegInvalidValidXptROMRegister); regNum++)
686  { ostringstream regName; // used to synthesize reg name
687  const ULWord rawInputXpt ((regNum - ULWord(kRegFirstValidXptROMRegister)) / 4UL + ULWord(NTV2_FIRST_INPUT_CROSSPOINT));
688  const ULWord ndx ((regNum - ULWord(kRegFirstValidXptROMRegister)) % 4UL);
689  const NTV2InputXptID inputXpt (NTV2InputXptID(rawInputXpt+0));
690  if (NTV2_IS_VALID_InputCrosspointID(inputXpt))
691  {
692  string inputXptEnumName (::NTV2InputCrosspointIDToString(inputXpt,false)); // e.g. "NTV2_XptFrameBuffer1Input"
693  if (inputXptEnumName.empty())
694  regName << "kRegXptValid" << DEC0N(rawInputXpt,3) << "N" << DEC(ndx);
695  else
696  regName << "kRegXptValid" << aja::replace(inputXptEnumName, "NTV2_Xpt", "") << DEC(ndx);
697  }
698  else
699  regName << "kRegXptValue" << HEX0N(regNum,4);
700  DefineRegister (regNum, regName.str(), mDecodeXptValidReg, READONLY, kRegClass_XptROM, kRegClass_NULL, kRegClass_NULL);
701  }
702  } // SetupXptSelect
703 
704  void SetupAncInsExt(void)
705  {
706  static const string AncExtRegNames [] = { "Control", "F1 Start Address", "F1 End Address",
707  "F2 Start Address", "F2 End Address", "Field Cutoff Lines",
708  "Memory Total", "F1 Memory Usage", "F2 Memory Usage",
709  "V Blank Lines", "Lines Per Frame", "Field ID Lines",
710  "Ignore DID 1-4", "Ignore DID 5-8", "Ignore DID 9-12",
711  "Ignore DID 13-16", "Ignore DID 17-20", "Analog Start Line",
712  "Analog F1 Y Filter", "Analog F2 Y Filter", "Analog F1 C Filter",
713  "Analog F2 C Filter", "", "",
714  "", "", "",
715  "Analog Act Line Len"};
716  static const string AncInsRegNames [] = { "Field Bytes", "Control", "F1 Start Address",
717  "F2 Start Address", "Pixel Delay", "Active Start",
718  "Pixels Per Line", "Lines Per Frame", "Field ID Lines",
719  "Payload ID Control", "Payload ID", "Chroma Blank Lines",
720  "F1 C Blanking Mask", "F2 C Blanking Mask", "Field Bytes High",
721  "Reserved 15", "RTP Payload ID", "RTP SSRC",
722  "IP Channel"};
723  static const uint32_t AncExtPerChlRegBase [] = { 0x1000, 0x1040, 0x1080, 0x10C0, 0x1100, 0x1140, 0x1180, 0x11C0 };
724  static const uint32_t AncInsPerChlRegBase [] = { 0x1200, 0x1240, 0x1280, 0x12C0, 0x1300, 0x1340, 0x1380, 0x13C0 };
725 
726  NTV2_ASSERT(sizeof(AncExtRegNames[0]) == sizeof(AncExtRegNames[1]));
727  NTV2_ASSERT(size_t(regAncExt_LAST) == sizeof(AncExtRegNames)/sizeof(AncExtRegNames[0]));
728  NTV2_ASSERT(size_t(regAncIns_LAST) == sizeof(AncInsRegNames)/sizeof(string));
729 
730  AJAAutoLock lock(&mGuardMutex);
731  for (ULWord offsetNdx (0); offsetNdx < 8; offsetNdx++)
732  {
733  for (ULWord reg(regAncExtControl); reg < regAncExt_LAST; reg++)
734  {
735  if (AncExtRegNames[reg].empty()) continue;
736  ostringstream oss; oss << "Extract " << (offsetNdx+1) << " " << AncExtRegNames[reg];
737  DefineRegName (AncExtPerChlRegBase[offsetNdx] + reg, oss.str());
738  }
739  for (ULWord reg(regAncInsFieldBytes); reg < regAncIns_LAST; reg++)
740  {
741  ostringstream oss; oss << "Insert " << (offsetNdx+1) << " " << AncInsRegNames[reg];
742  DefineRegName (AncInsPerChlRegBase[offsetNdx] + reg, oss.str());
743  }
744  }
745  for (ULWord ndx (0); ndx < 8; ndx++)
746  {
747  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtControl, "", mDecodeAncExtControlReg, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
748  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
749  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
750  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
751  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
752  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFieldCutoffLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
753  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtTotalStatus, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
754  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
755  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
756  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFieldVBLStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
757  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtTotalFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
758  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtFID, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
759  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_1_2_3_4, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
760  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_5_6_7_8, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
761  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_9_10_11_12, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
762  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_13_14_15_16, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
763  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtIgnorePacketReg_17_18_19_20, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
764  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtAnalogStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
765  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1AnalogYFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
766  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2AnalogYFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
767  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField1AnalogCFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
768  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtField2AnalogCFilter, "", mDecodeAncExtAnalogFilter, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
769  DefineRegister (AncExtPerChlRegBase[ndx] + regAncExtAnalogActiveLineLength, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Input, gChlClasses[ndx]);
770 
771  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytes, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
772  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsControl, "", mDecodeAncInsControlReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
773  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField1StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
774  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField2StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
775  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPixelDelay, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
776  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsActiveStart, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
777  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsLinePixels, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
778  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
779  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldIDLines, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
780  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadIDControl, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
781  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
782  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankCStartLine, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
783  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField1CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
784  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField2CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
785  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytesHigh, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
786  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
787  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpSSRC, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
788  DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsIpChannel, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
789  }
790  } // SetupAncInsExt
791 
792  void SetupAuxInsExt(void)
793  {
794  static const string AuxExtRegNames [] = { "Control", "F1 Start Address", "F1 End Address",
795  "F2 Start Address", "", "",
796  "Memory Total", "F1 Memory Usage", "F2 Memory Usage",
797  "V Blank Lines", "Lines Per Frame", "Field ID Lines",
798  "Ignore DID 1-4", "Ignore DID 5-8", "Ignore DID 9-12",
799  "Ignore DID 13-16", "Buffer Fill"};
800  // static const string AncInsRegNames [] = { "Field Bytes", "Control", "F1 Start Address",
801  // "F2 Start Address", "Pixel Delay", "Active Start",
802  // "Pixels Per Line", "Lines Per Frame", "Field ID Lines",
803  // "Payload ID Control", "Payload ID", "Chroma Blank Lines",
804  // "F1 C Blanking Mask", "F2 C Blanking Mask", "Field Bytes High",
805  // "Reserved 15", "RTP Payload ID", "RTP SSRC",
806  // "IP Channel"};
807  static const uint32_t AuxExtPerChlRegBase [] = { 7616, 7680, 7744, 7808 };
808  static const uint32_t AuxInsPerChlRegBase [] = { 4608, 4672, 4736, 4800 };
809  NTV2_UNUSED(AuxInsPerChlRegBase);
810 
811  NTV2_ASSERT(sizeof(AuxExtRegNames[0]) == sizeof(AuxExtRegNames[1]));
812  NTV2_ASSERT(size_t(regAuxExt_LAST) == sizeof(AuxExtRegNames)/sizeof(AuxExtRegNames[0]));
813  //NTV2_ASSERT(size_t(regAncIns_LAST) == sizeof(AncInsRegNames)/sizeof(string));
814 
815  AJAAutoLock lock(&mGuardMutex);
816  for (ULWord offsetNdx (0); offsetNdx < 4; offsetNdx++)
817  {
818  for (ULWord reg(regAuxExtControl); reg < regAuxExt_LAST; reg++)
819  {
820  if (AuxExtRegNames[reg].empty()) continue;
821  ostringstream oss; oss << "Extract " << (offsetNdx+1) << " " << AuxExtRegNames[reg];
822  DefineRegName (AuxExtPerChlRegBase[offsetNdx] + reg, oss.str());
823  }
824  // for (ULWord reg(regAncInsFieldBytes); reg < regAncIns_LAST; reg++)
825  // {
826  // ostringstream oss; oss << "Insert " << (offsetNdx+1) << " " << AncInsRegNames[reg];
827  // DefineRegName (AncInsPerChlRegBase[offsetNdx] + reg, oss.str());
828  // }
829  }
830  for (ULWord ndx (0); ndx < 4; ndx++)
831  {
832  // Some of the decoders are shared with Anc
833  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtControl, "", mDecodeAuxExtControlReg, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
834  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
835  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1EndAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
836  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField2StartAddress, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
837  // DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExt4, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
838  // DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExt5, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
839  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtTotalStatus, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
840  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField1Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
841  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtField2Status, "", mDecodeAncExtStatus, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
842  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFieldVBLStartLine, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
843  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtTotalFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
844  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFID, "", mDecodeAncExtFieldLines, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
845  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask0, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
846  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask1, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
847  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask2, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
848  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtPacketMask3, "", mDecodeAncExtIgnoreDIDs, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
849  DefineRegister (AuxExtPerChlRegBase[ndx] + regAuxExtFillData, "", mDefaultRegDecoder, READWRITE, kRegClass_Aux, kRegClass_Input, gChlClasses[ndx]);
850 
851 
852  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytes, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
853  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsControl, "", mDecodeAncInsControlReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
854  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField1StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
855  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsField2StartAddr, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
856  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPixelDelay, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
857  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsActiveStart, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
858  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsLinePixels, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
859  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFrameLines, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
860  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldIDLines, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
861  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadIDControl, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
862  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
863  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankCStartLine, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
864  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField1CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
865  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsBlankField2CLines, "", mDecodeAncInsChromaBlankReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
866  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsFieldBytesHigh, "", mDecodeAncInsValuePairReg, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
867  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpPayloadID, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
868  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsRtpSSRC, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
869  // DefineRegister (AncInsPerChlRegBase[ndx] + regAncInsIpChannel, "", mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_Output, gChlClasses[ndx]);
870  }
871  } // SetupAuxInsExt
872 
873  void SetupHDMIRegs(void)
874  {
875  AJAAutoLock lock(&mGuardMutex);
876  DefineRegister (kRegHDMIOutControl, "", mDecodeHDMIOutputControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
877  DefineRegister (kRegHDMIInputStatus, "", mDecodeHDMIInputStatus, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
878  DefineRegister (kRegHDMIInputControl, "", mDecodeHDMIInputControl, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
879  DefineRegister (kRegHDMIHDRGreenPrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
880  DefineRegister (kRegHDMIHDRBluePrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
881  DefineRegister (kRegHDMIHDRRedPrimary, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
882  DefineRegister (kRegHDMIHDRWhitePoint, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
883  DefineRegister (kRegHDMIHDRMasteringLuminence, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
884  DefineRegister (kRegHDMIHDRLightLevel, "", mDecodeHDMIOutHDRPrimary, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
885  DefineRegister (kRegHDMIHDRControl, "", mDecodeHDMIOutHDRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_HDR);
886  DefineRegister (kRegMRQ1Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
887  DefineRegister (kRegMRQ2Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
888  DefineRegister (kRegMRQ3Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
889  DefineRegister (kRegMRQ4Control, "", mDecodeHDMIOutMRControl, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
890  DefineRegister (kRegHDMIV2I2C1Control, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
891  DefineRegister (kRegHDMIV2I2C1Data, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
892  DefineRegister (kRegHDMIV2VideoSetup, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
893  DefineRegister (kRegHDMIV2HSyncDurationAndBackPorch, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
894  DefineRegister (kRegHDMIV2HActive, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
895  DefineRegister (kRegHDMIV2VSyncDurationAndBackPorchField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
896  DefineRegister (kRegHDMIV2VSyncDurationAndBackPorchField2, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
897  DefineRegister (kRegHDMIV2VActiveField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
898  DefineRegister (kRegHDMIV2VActiveField2, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
899  DefineRegister (kRegHDMIV2VideoStatus, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
900  DefineRegister (kRegHDMIV2HorizontalMeasurements, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
901  DefineRegister (kRegHDMIV2HBlankingMeasurements, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
902  DefineRegister (kRegHDMIV2HBlankingMeasurements1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
903  DefineRegister (kRegHDMIV2VerticalMeasurementsField0, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
904  DefineRegister (kRegHDMIV2VerticalMeasurementsField1, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
905  DefineRegister (kRegHDMIV2i2c2Control, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
906  DefineRegister (kRegHDMIV2i2c2Data, "", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
907 
908  DefineRegister (0x1d00, "reg_hdmiin4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
909  DefineRegister (0x1d01, "reg_hdmiin4_videodetect0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
910  DefineRegister (0x1d02, "reg_hdmiin4_videodetect1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
911  DefineRegister (0x1d03, "reg_hdmiin4_videodetect2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
912  DefineRegister (0x1d04, "reg_hdmiin4_videodetect3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
913  DefineRegister (0x1d05, "reg_hdmiin4_videodetect4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
914  DefineRegister (0x1d06, "reg_hdmiin4_videodetect5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
915  DefineRegister (0x1d07, "reg_hdmiin4_videodetect6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
916  DefineRegister (0x1d08, "reg_hdmiin4_videodetect7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
917  DefineRegister (0x1d09, "reg_hdmiin4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
918  DefineRegister (0x1d0a, "reg_hdmiin4_receiverstatus", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
919  DefineRegister (0x1d0b, "reg_hdmiin4_auxpacketignore0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
920  DefineRegister (0x1d0c, "reg_hdmiin4_auxpacketignore1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
921  DefineRegister (0x1d0d, "reg_hdmiin4_auxpacketignore2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
922  DefineRegister (0x1d0e, "reg_hdmiin4_auxpacketignore3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
923  DefineRegister (0x1d0f, "reg_hdmiin4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
924  DefineRegister (0x1d10, "reg_hdmiin4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
925  DefineRegister (0x1d11, "reg_hdmiin4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
926  DefineRegister (0x1d12, "reg_hdmiin4_rxclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
927  DefineRegister (0x1d13, "reg_hdmiin4_rxoversampling", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
928  DefineRegister (0x1d14, "reg_hdmiin4_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
929  DefineRegister (0x1d15, "reg_hdmiin4_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
930  DefineRegister (0x1d16, "reg_hdmiin4_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
931  DefineRegister (0x1d1e, "reg_hdmiin4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
932  DefineRegister (0x1d1f, "reg_hdmiin4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel1);
933 
934  DefineRegister (0x2500, "reg_hdmiin4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
935  DefineRegister (0x2501, "reg_hdmiin4_videodetect0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
936  DefineRegister (0x2502, "reg_hdmiin4_videodetect1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
937  DefineRegister (0x2503, "reg_hdmiin4_videodetect2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
938  DefineRegister (0x2504, "reg_hdmiin4_videodetect3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
939  DefineRegister (0x2505, "reg_hdmiin4_videodetect4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
940  DefineRegister (0x2506, "reg_hdmiin4_videodetect5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
941  DefineRegister (0x2507, "reg_hdmiin4_videodetect6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
942  DefineRegister (0x2508, "reg_hdmiin4_videodetect7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
943  DefineRegister (0x2509, "reg_hdmiin4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
944  DefineRegister (0x250a, "reg_hdmiin4_receiverstatus", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
945  DefineRegister (0x250b, "reg_hdmiin4_auxpacketignore0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
946  DefineRegister (0x250c, "reg_hdmiin4_auxpacketignore1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
947  DefineRegister (0x250d, "reg_hdmiin4_auxpacketignore2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
948  DefineRegister (0x250e, "reg_hdmiin4_auxpacketignore3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
949  DefineRegister (0x250f, "reg_hdmiin4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
950  DefineRegister (0x2510, "reg_hdmiin4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
951  DefineRegister (0x2511, "reg_hdmiin4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
952  DefineRegister (0x2512, "reg_hdmiin4_rxclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
953  DefineRegister (0x2513, "reg_hdmiin4_rxoversampling", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
954  DefineRegister (0x2514, "reg_hdmiin4_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
955  DefineRegister (0x2515, "reg_hdmiin4_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
956  DefineRegister (0x2516, "reg_hdmiin4_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
957  DefineRegister (0x251e, "reg_hdmiin4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
958  DefineRegister (0x251f, "reg_hdmiin4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel2);
959 
960  DefineRegister (0x2c00, "reg_hdmiin_i2c_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
961  DefineRegister (0x2c01, "reg_hdmiin_i2c_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
962  DefineRegister (0x2c02, "reg_hdmiin_video_setup", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
963  DefineRegister (0x2c03, "reg_hdmiin_hsync_duration", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
964  DefineRegister (0x2c04, "reg_hdmiin_h_active", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
965  DefineRegister (0x2c05, "reg_hdmiin_vsync_duration_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
966  DefineRegister (0x2c06, "reg_hdmiin_vsync_duration_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
967  DefineRegister (0x2c07, "reg_hdmiin_v_active_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
968  DefineRegister (0x2c08, "reg_hdmiin_v_active_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
969  DefineRegister (0x2c09, "reg_hdmiin_video_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
970  DefineRegister (0x2c0a, "reg_hdmiin_horizontal_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
971  DefineRegister (0x2c0b, "reg_hdmiin_hblank_data0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
972  DefineRegister (0x2c0c, "reg_hdmiin_hblank_data1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
973  DefineRegister (0x2c0d, "reg_hdmiin_vertical_data_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
974  DefineRegister (0x2c0e, "reg_hdmiin_vertical_data_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
975  DefineRegister (0x2c0f, "reg_hdmiin_color_depth", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
976  DefineRegister (0x2c12, "reg_hdmiin_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
977  DefineRegister (0x2c13, "reg_hdmiin_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
978  DefineRegister (0x2c14, "reg_hdmiin_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel3);
979 
980  DefineRegister (0x3000, "reg_hdmiin_i2c_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
981  DefineRegister (0x3001, "reg_hdmiin_i2c_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
982  DefineRegister (0x3002, "reg_hdmiin_video_setup", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
983  DefineRegister (0x3003, "reg_hdmiin_hsync_duration", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
984  DefineRegister (0x3004, "reg_hdmiin_h_active", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
985  DefineRegister (0x3005, "reg_hdmiin_vsync_duration_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
986  DefineRegister (0x3006, "reg_hdmiin_vsync_duration_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
987  DefineRegister (0x3007, "reg_hdmiin_v_active_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
988  DefineRegister (0x3008, "reg_hdmiin_v_active_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
989  DefineRegister (0x3009, "reg_hdmiin_video_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
990  DefineRegister (0x300a, "reg_hdmiin_horizontal_data", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
991  DefineRegister (0x300b, "reg_hdmiin_hblank_data0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
992  DefineRegister (0x300c, "reg_hdmiin_hblank_data1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
993  DefineRegister (0x300d, "reg_hdmiin_vertical_data_fld1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
994  DefineRegister (0x300e, "reg_hdmiin_vertical_data_fld2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
995  DefineRegister (0x300f, "reg_hdmiin_color_depth", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
996  DefineRegister (0x3012, "reg_hdmiin_output_config", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
997  DefineRegister (0x3013, "reg_hdmiin_input_status", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
998  DefineRegister (0x3014, "reg_hdmiin_control", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_Channel4);
999 
1000  DefineRegister (0x1d40, "reg_hdmiout4_videocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1001  DefineRegister (0x1d41, "reg_hdmiout4_videosetup0", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1002  DefineRegister (0x1d42, "reg_hdmiout4_videosetup1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1003  DefineRegister (0x1d43, "reg_hdmiout4_videosetup2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1004  DefineRegister (0x1d44, "reg_hdmiout4_videosetup3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1005  DefineRegister (0x1d45, "reg_hdmiout4_videosetup4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1006  DefineRegister (0x1d46, "reg_hdmiout4_videosetup5", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1007  DefineRegister (0x1d47, "reg_hdmiout4_videosetup6", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1008  DefineRegister (0x1d48, "reg_hdmiout4_videosetup7", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1009  DefineRegister (0x1d49, "reg_hdmiout4_auxcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1010  DefineRegister (0x1d4b, "reg_hdmiout4_audiocontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1011  DefineRegister (0x1d4f, "reg_hdmiout4_redrivercontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1012  DefineRegister (0x1d50, "reg_hdmiout4_refclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1013  DefineRegister (0x1d51, "reg_hdmiout4_tmdsclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1014  DefineRegister (0x1d52, "reg_hdmiout4_txclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1015  DefineRegister (0x1d53, "reg_hdmiout4_fpllclockfrequency", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1016  DefineRegister (0x1d54, "reg_hdmiout4_audio_cts1", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1017  DefineRegister (0x1d55, "reg_hdmiout4_audio_cts2", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1018  DefineRegister (0x1d56, "reg_hdmiout4_audio_cts3", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1019  DefineRegister (0x1d57, "reg_hdmiout4_audio_cts4", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1020  DefineRegister (0x1d58, "reg_hdmiout4_audio_n", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1021  DefineRegister (0x1d5e, "reg_hdmiout4_croplocation", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1022  DefineRegister (0x1d5f, "reg_hdmiout4_pixelcontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1023  DefineRegister (0x1d60, "reg_hdmiout4_i2ccontrol", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1024  DefineRegister (0x1d61, "reg_hdmiout4_i2cedid", mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_Channel1);
1025  }
1026 
1027  void SetupSDIErrorRegs(void)
1028  {
1029  static const ULWord baseNum[] = {kRegRXSDI1Status, kRegRXSDI2Status, kRegRXSDI3Status, kRegRXSDI4Status, kRegRXSDI5Status, kRegRXSDI6Status, kRegRXSDI7Status, kRegRXSDI8Status};
1030  static const string suffixes [] = {"Status", "CRCErrorCount", "FrameCountLow", "FrameCountHigh", "FrameRefCountLow", "FrameRefCountHigh"};
1031  static const int perms [] = {READWRITE, READWRITE, READWRITE, READWRITE, READONLY, READONLY};
1032 
1033  AJAAutoLock lock(&mGuardMutex);
1034  for (ULWord chan (0); chan < 8; chan++)
1035  for (UWord ndx(0); ndx < 6; ndx++)
1036  {
1037  ostringstream ossName; ossName << "kRegRXSDI" << DEC(chan+1) << suffixes[ndx];
1038  const string & regName (ossName.str());
1039  const uint32_t regNum (baseNum[chan] + ndx);
1040  const int perm (perms[ndx]);
1041  if (ndx == 0)
1042  DefineRegister (regNum, regName, mSDIErrorStatusRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1043  else if (ndx == 1)
1044  DefineRegister (regNum, regName, mSDIErrorCountRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1045  else
1046  DefineRegister (regNum, regName, mDefaultRegDecoder, perm, kRegClass_SDIError, gChlClasses[chan], kRegClass_Input);
1047  }
1048  DefineRegister (kRegRXSDIFreeRunningClockLow, "kRegRXSDIFreeRunningClockLow", mDefaultRegDecoder, READONLY, kRegClass_SDIError, kRegClass_NULL, kRegClass_NULL);
1049  DefineRegister (kRegRXSDIFreeRunningClockHigh, "kRegRXSDIFreeRunningClockHigh", mDefaultRegDecoder, READONLY, kRegClass_SDIError, kRegClass_NULL, kRegClass_NULL);
1050  } // SetupSDIErrorRegs
1051 
1052  void SetupLUTRegs (void)
1053  {
1054  AJAAutoLock lock(&mGuardMutex);
1055  }
1056 
1057  void SetupCSCRegs(void)
1058  {
1059  static const string sChan[8] = {kRegClass_Channel1, kRegClass_Channel2, kRegClass_Channel3, kRegClass_Channel4, kRegClass_Channel5, kRegClass_Channel6, kRegClass_Channel7, kRegClass_Channel8};
1060 
1061  AJAAutoLock lock(&mGuardMutex);
1062  for (unsigned num(0); num < 8; num++)
1063  {
1064  ostringstream ossRegName; ossRegName << "kRegEnhancedCSC" << (num+1);
1065  const string & chanClass (sChan[num]); const string rootName (ossRegName.str());
1066  const string modeName (rootName + "Mode"); const string inOff01Name (rootName + "InOffset0_1"); const string inOff2Name (rootName + "InOffset2");
1067  const string coeffA0Name (rootName + "CoeffA0"); const string coeffA1Name (rootName + "CoeffA1"); const string coeffA2Name (rootName + "CoeffA2");
1068  const string coeffB0Name (rootName + "CoeffB0"); const string coeffB1Name (rootName + "CoeffB1"); const string coeffB2Name (rootName + "CoeffB2");
1069  const string coeffC0Name (rootName + "CoeffC0"); const string coeffC1Name (rootName + "CoeffC1"); const string coeffC2Name (rootName + "CoeffC2");
1070  const string outOffABName(rootName + "OutOffsetA_B"); const string outOffCName (rootName + "OutOffsetC");
1071  const string keyModeName (rootName + "KeyMode"); const string keyClipOffName (rootName + "KeyClipOffset"); const string keyGainName (rootName + "KeyGain");
1072  DefineRegister (64*num + kRegEnhancedCSC1Mode, modeName, mEnhCSCModeDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1073  DefineRegister (64*num + kRegEnhancedCSC1InOffset0_1, inOff01Name, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1074  DefineRegister (64*num + kRegEnhancedCSC1InOffset2, inOff2Name, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1075  DefineRegister (64*num + kRegEnhancedCSC1CoeffA0, coeffA0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1076  DefineRegister (64*num + kRegEnhancedCSC1CoeffA1, coeffA1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1077  DefineRegister (64*num + kRegEnhancedCSC1CoeffA2, coeffA2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1078  DefineRegister (64*num + kRegEnhancedCSC1CoeffB0, coeffB0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1079  DefineRegister (64*num + kRegEnhancedCSC1CoeffB1, coeffB1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1080  DefineRegister (64*num + kRegEnhancedCSC1CoeffB2, coeffB2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1081  DefineRegister (64*num + kRegEnhancedCSC1CoeffC0, coeffC0Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1082  DefineRegister (64*num + kRegEnhancedCSC1CoeffC1, coeffC1Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1083  DefineRegister (64*num + kRegEnhancedCSC1CoeffC2, coeffC2Name, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1084  DefineRegister (64*num + kRegEnhancedCSC1OutOffsetA_B, outOffABName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1085  DefineRegister (64*num + kRegEnhancedCSC1OutOffsetC, outOffCName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1086  DefineRegister (64*num + kRegEnhancedCSC1KeyMode, keyModeName, mEnhCSCKeyModeDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1087  DefineRegister (64*num + kRegEnhancedCSC1KeyClipOffset, keyClipOffName, mEnhCSCOffsetDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1088  DefineRegister (64*num + kRegEnhancedCSC1KeyGain, keyGainName, mEnhCSCCoeffDecoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1089  }
1090  static const NTV2RegisterNumber sECSCRegs[8][5] = { { kRegCSCoefficients1_2, kRegCSCoefficients3_4, kRegCSCoefficients5_6, kRegCSCoefficients7_8, kRegCSCoefficients9_10 },
1091  { kRegCS2Coefficients1_2, kRegCS2Coefficients3_4, kRegCS2Coefficients5_6, kRegCS2Coefficients7_8, kRegCS2Coefficients9_10 },
1092  { kRegCS3Coefficients1_2, kRegCS3Coefficients3_4, kRegCS3Coefficients5_6, kRegCS3Coefficients7_8, kRegCS3Coefficients9_10 },
1093  { kRegCS4Coefficients1_2, kRegCS4Coefficients3_4, kRegCS4Coefficients5_6, kRegCS4Coefficients7_8, kRegCS4Coefficients9_10 },
1094  { kRegCS5Coefficients1_2, kRegCS5Coefficients3_4, kRegCS5Coefficients5_6, kRegCS5Coefficients7_8, kRegCS5Coefficients9_10 },
1095  { kRegCS6Coefficients1_2, kRegCS6Coefficients3_4, kRegCS6Coefficients5_6, kRegCS6Coefficients7_8, kRegCS6Coefficients9_10 },
1096  { kRegCS7Coefficients1_2, kRegCS7Coefficients3_4, kRegCS7Coefficients5_6, kRegCS7Coefficients7_8, kRegCS7Coefficients9_10 },
1097  { kRegCS8Coefficients1_2, kRegCS8Coefficients3_4, kRegCS8Coefficients5_6, kRegCS8Coefficients7_8, kRegCS8Coefficients9_10 } };
1098  for (unsigned chan(0); chan < 8; chan++)
1099  {
1100  const string & chanClass (sChan[chan]);
1101  DefineRegister (sECSCRegs[chan][0], "", mCSCoeff1234Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1102  DefineRegister (sECSCRegs[chan][1], "", mCSCoeff1234Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1103  DefineRegister (sECSCRegs[chan][2], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1104  DefineRegister (sECSCRegs[chan][3], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1105  DefineRegister (sECSCRegs[chan][4], "", mCSCoeff567890Decoder, READWRITE, kRegClass_CSC, chanClass, kRegClass_NULL);
1106  }
1107 
1108  // LUT/ColorCorrection Registers...
1109  DefineRegister (kRegCh1ColorCorrectionControl, "", mLUTV1ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1110  DefineRegister (kRegCh2ColorCorrectionControl, "", mLUTV1ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1111  DefineRegister (kRegLUTV2Control, "", mLUTV2ControlRegDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1112  // LUT tables...
1113 #if 1 // V2 tables need the appropriate Enable & Bank bits set in kRegLUTV2Control, otherwise they'll always readback zero!
1114  // So it's kinda pointless to read/decode them unless we do the "bank-select" dance immediately before reading them...
1115  const ULWord REDreg(kColorCorrectionLUTOffset_Red/4), GRNreg(kColorCorrectionLUTOffset_Green/4), BLUreg(kColorCorrectionLUTOffset_Blue/4);
1116  for (ULWord ndx(0); ndx < 512; ndx++)
1117  {
1118  ostringstream regNameR, regNameG, regNameB;
1119  regNameR << "kRegLUTRed" << DEC0N(ndx,3); regNameG << "kRegLUTGreen" << DEC0N(ndx,3); regNameB << "kRegLUTBlue" << DEC0N(ndx,3);
1120  DefineRegister (REDreg + ndx, regNameR.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1121  DefineRegister (GRNreg + ndx, regNameG.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1122  DefineRegister (BLUreg + ndx, regNameB.str(), mLUTDecoder, READWRITE, kRegClass_LUT, kRegClass_NULL, kRegClass_NULL);
1123  }
1124 #endif
1125  } // SetupCSCRegs
1126 
1127  void SetupMixerKeyerRegs(void)
1128  {
1129  AJAAutoLock lock(&mGuardMutex);
1130  // VidProc/Mixer/Keyer
1131  DefineRegister (kRegVidProc1Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1132  DefineRegister (kRegVidProc2Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1133  DefineRegister (kRegVidProc3Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1134  DefineRegister (kRegVidProc4Control, "", mVidProcControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1135  DefineRegister (kRegSplitControl, "", mSplitControlRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_NULL);
1136  DefineRegister (kRegFlatMatteValue, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1137  DefineRegister (kRegFlatMatte2Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1138  DefineRegister (kRegFlatMatte3Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1139  DefineRegister (kRegFlatMatte4Value, "", mFlatMatteValueRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1140  DefineRegister (kRegMixer1Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel1, kRegClass_Channel2);
1141  DefineRegister (kRegMixer2Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel3, kRegClass_Channel4);
1142  DefineRegister (kRegMixer3Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel5, kRegClass_Channel6);
1143  DefineRegister (kRegMixer4Coefficient, "", mDefaultRegDecoder, READWRITE, kRegClass_Mixer, kRegClass_Channel7, kRegClass_Channel8);
1144  }
1145 
1146  void SetupNTV4FrameStoreRegs(void)
1147  {
1148  for (ULWord fsNdx(0); fsNdx < 4; fsNdx++)
1149  {
1150  for (ULWord regNdx(0); regNdx < ULWord(regNTV4FS_LAST); regNdx++)
1151  {
1152  ostringstream regName; regName << "kRegNTV4FS" << DEC(fsNdx+1) << "_";
1153  const ULWord registerNumber (kNTV4FrameStoreFirstRegNum + fsNdx * kNumNTV4FrameStoreRegisters + regNdx);
1154  switch (NTV4FrameStoreRegs(regNdx))
1155  {
1156  case regNTV4FS_LineLengthPitch:
1157  case regNTV4FS_ROIVHSize:
1158  case regNTV4FS_ROIF1StartAddr:
1159  case regNTV4FS_ROIF2StartAddr:
1160  case regNTV4FS_ROIF1VHOffsets:
1161  case regNTV4FS_ROIF2VHOffsets:
1162  case regNTV4FS_DisplayHorzPixelsPerLine:
1163  case regNTV4FS_DisplayFID:
1164  case regNTV4FS_F1ActiveLines:
1165  case regNTV4FS_F2ActiveLines:
1166  case regNTV4FS_RasterControl:
1167  case regNTV4FS_RasterPixelSkip:
1168  case regNTV4FS_RasterVideoFill_YCb_GB:
1169  case regNTV4FS_RasterVideoFill_Cr_AR:
1170  case regNTV4FS_RasterROIFillAlpha:
1171  case regNTV4FS_Status:
1172  case regNTV4FS_RasterOutputTimingPreset:
1173  case regNTV4FS_RasterVTotalLines:
1174  case regNTV4FS_RasterSmpteFramePulse:
1175  case regNTV4FS_RasterOddLineStartAddress:
1176  case regNTV4FS_RasterOffsetBlue:
1177  case regNTV4FS_RasterOffsetRed:
1178  case regNTV4FS_RasterOffsetAlpha:
1179  regName << sNTV4FrameStoreRegNames[regNdx];
1180  DefineRegister(registerNumber, regName.str(), mDecodeNTV4FSReg, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1181  break;
1182  case regNTV4FS_InputSourceSelect:
1183  regName << "InputSourceSelect";
1184  DefineRegister(registerNumber, regName.str(), mDecodeNTV4FSReg, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1185  break;
1186  default:
1187  regName << DEC(regNdx);
1188  DefineRegister(registerNumber, regName.str(), mDefaultRegDecoder, READWRITE, kRegClass_NTV4FrameStore, gChlClasses[fsNdx], kRegClass_NULL);
1189  break;
1190  }
1191  } // for each FrameStore register
1192  } // for each FrameStore widget
1193  }
1194 
1195  void SetupVRegs(void)
1196  {
1197  AJAAutoLock lock(&mGuardMutex);
1198  DEF_REG (kVRegDriverVersion, mDriverVersionDecoder, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1199  DEF_REGNAME (kVRegRelativeVideoPlaybackDelay);
1200  DEF_REGNAME (kVRegAudioRecordPinDelay);
1201  DEF_REGNAME (kVRegGlobalAudioPlaybackMode);
1202  DEF_REGNAME (kVRegFlashProgramKey);
1203  DEF_REGNAME (kVRegStrictTiming);
1204  DEF_REG (kVRegDriverType, mDecodeDriverType, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1205  DEF_REGNAME (kVRegInputSelect);
1206  DEF_REGNAME (kVRegSecondaryFormatSelect);
1207  DEF_REGNAME (kVRegDigitalOutput1Select);
1208  DEF_REGNAME (kVRegDigitalOutput2Select);
1209  DEF_REGNAME (kVRegAnalogOutputSelect);
1210  DEF_REGNAME (kVRegAnalogOutputType);
1211  DEF_REGNAME (kVRegAnalogOutBlackLevel);
1212  DEF_REGNAME (kVRegInputSelectUser);
1213  DEF_REGNAME (kVRegVideoOutPauseMode);
1214  DEF_REGNAME (kVRegPulldownPattern);
1215  DEF_REGNAME (kVRegColorSpaceMode);
1216  DEF_REGNAME (kVRegGammaMode);
1217  DEF_REGNAME (kVRegLUTType);
1218  DEF_REGNAME (kVRegRGB10Range);
1219  DEF_REGNAME (kVRegRGB10Endian);
1220  DEF_REGNAME (kVRegFanControl);
1221  DEF_REGNAME (kVRegBitFileDownload);
1222  DEF_REGNAME (kVRegSaveRegistersToRegistry);
1223  DEF_REGNAME (kVRegRecallRegistersFromRegistry);
1224  DEF_REGNAME (kVRegClearAllSubscriptions);
1225  DEF_REGNAME (kVRegRestoreHardwareProcampRegisters);
1226  DEF_REGNAME (kVRegAcquireReferenceCount);
1227  DEF_REGNAME (kVRegReleaseReferenceCount);
1228  DEF_REGNAME (kVRegDTAudioMux0);
1229  DEF_REGNAME (kVRegDTAudioMux1);
1230  DEF_REGNAME (kVRegDTAudioMux2);
1231  DEF_REGNAME (kVRegDTFirmware);
1232  DEF_REGNAME (kVRegDTVersionAja);
1233  DEF_REGNAME (kVRegDTVersionDurian);
1234  DEF_REGNAME (kVRegDTAudioCapturePinConnected);
1235  DEF_REGNAME (kVRegTimeStampMode);
1236  DEF_REGNAME (kVRegTimeStampLastOutputVerticalLo);
1237  DEF_REGNAME (kVRegTimeStampLastOutputVerticalHi);
1238  DEF_REGNAME (kVRegTimeStampLastInput1VerticalLo);
1239  DEF_REGNAME (kVRegTimeStampLastInput1VerticalHi);
1240  DEF_REGNAME (kVRegTimeStampLastInput2VerticalLo);
1241  DEF_REGNAME (kVRegTimeStampLastInput2VerticalHi);
1242  DEF_REGNAME (kVRegNumberVideoMappingRegisters);
1243  DEF_REGNAME (kVRegNumberAudioMappingRegisters);
1244  DEF_REGNAME (kVRegAudioSyncTolerance);
1245  DEF_REGNAME (kVRegDmaSerialize);
1246  DEF_REGNAME (kVRegSyncChannel);
1247  DEF_REGNAME (kVRegSyncChannels);
1248  DEF_REGNAME (kVRegSoftwareUartFifo);
1249  DEF_REGNAME (kVRegTimeCodeCh1Delay);
1250  DEF_REGNAME (kVRegTimeCodeCh2Delay);
1251  DEF_REGNAME (kVRegTimeCodeIn1Delay);
1252  DEF_REGNAME (kVRegTimeCodeIn2Delay);
1253  DEF_REGNAME (kVRegTimeCodeCh3Delay);
1254  DEF_REGNAME (kVRegTimeCodeCh4Delay);
1255  DEF_REGNAME (kVRegTimeCodeIn3Delay);
1256  DEF_REGNAME (kVRegTimeCodeIn4Delay);
1257  DEF_REGNAME (kVRegTimeCodeCh5Delay);
1258  DEF_REGNAME (kVRegTimeCodeIn5Delay);
1259  DEF_REGNAME (kVRegTimeCodeCh6Delay);
1260  DEF_REGNAME (kVRegTimeCodeIn6Delay);
1261  DEF_REGNAME (kVRegTimeCodeCh7Delay);
1262  DEF_REGNAME (kVRegTimeCodeIn7Delay);
1263  DEF_REGNAME (kVRegTimeCodeCh8Delay);
1264  DEF_REGNAME (kVRegTimeCodeIn8Delay);
1265  DEF_REGNAME (kVRegDebug1);
1266  DEF_REGNAME (kVRegDebugLastFormat);
1267  DEF_REGNAME (kVRegDebugIPConfigTimeMS);
1268  DEF_REGNAME (kVRegDisplayReferenceSelect);
1269  DEF_REGNAME (kVRegVANCMode);
1270  DEF_REGNAME (kVRegDualStreamTransportType);
1271  DEF_REGNAME (kVRegDSKMode);
1272  DEF_REGNAME (kVRegIsoConvertEnable);
1273  DEF_REGNAME (kVRegDSKAudioMode);
1274  DEF_REGNAME (kVRegDSKForegroundMode);
1275  DEF_REGNAME (kVRegDSKForegroundFade);
1276  DEF_REGNAME (kVRegCaptureReferenceSelect);
1277  DEF_REGNAME (kVRegUnfilterAnc);
1278  DEF_REGNAME (kVRegSDIOutput1RGBRange);
1279  DEF_REGNAME (kVRegSDIInput1FormatSelect);
1280  DEF_REGNAME (kVRegSDIInput2FormatSelect);
1281  DEF_REGNAME (kVRegSDIInput1RGBRange);
1282  DEF_REGNAME (kVRegSDIInput2RGBRange);
1283  DEF_REGNAME (kVRegSDIInput1Stereo3DMode);
1284  DEF_REGNAME (kVRegSDIInput2Stereo3DMode);
1285  DEF_REGNAME (kVRegFrameBuffer1RGBRange);
1286  DEF_REGNAME (kVRegFrameBuffer1Stereo3DMode);
1287  DEF_REGNAME (kVRegHDMIInRgbRange);
1288  DEF_REGNAME (kVRegHDMIOutRgbRange);
1289  DEF_REGNAME (kVRegAnalogInBlackLevel);
1290  DEF_REGNAME (kVRegAnalogInputType);
1291  DEF_REGNAME (kVRegHDMIOutColorSpaceModeCtrl);
1292  DEF_REGNAME (kVRegHDMIOutProtocolMode);
1293  DEF_REGNAME (kVRegHDMIOutStereoSelect);
1294  DEF_REGNAME (kVRegHDMIOutStereoCodecSelect);
1295  DEF_REGNAME (kVRegHdmiOutSubSample);
1296  DEF_REGNAME (kVRegSDIInput1ColorSpaceMode);
1297  DEF_REGNAME (kVRegSDIInput2ColorSpaceMode);
1298  DEF_REGNAME (kVRegSDIOutput2RGBRange);
1299  DEF_REGNAME (kVRegSDIOutput1Stereo3DMode);
1300  DEF_REGNAME (kVRegSDIOutput2Stereo3DMode);
1301  DEF_REGNAME (kVRegFrameBuffer2RGBRange);
1302  DEF_REGNAME (kVRegFrameBuffer2Stereo3DMode);
1303  DEF_REGNAME (kVRegAudioGainDisable);
1304  DEF_REGNAME (kVRegLTCOnRefInSelect);
1305  DEF_REGNAME (kVRegActiveVideoOutFilter);
1306  DEF_REGNAME (kVRegAudioInputMapSelect);
1307  DEF_REGNAME (kVRegAudioInputDelay);
1308  DEF_REGNAME (kVRegDSKGraphicFileIndex);
1309  DEF_REGNAME (kVRegTimecodeBurnInMode);
1310  DEF_REGNAME (kVRegUseQTTimecode);
1311  DEF_REGNAME (kVRegAvailable164);
1312  DEF_REGNAME (kVRegRP188SourceSelect);
1313  DEF_REGNAME (kVRegQTCodecModeDebug);
1314  DEF_REGNAME (kVRegHDMIOutColorSpaceModeStatus);
1315  DEF_REGNAME (kVRegDeviceOnline);
1316  DEF_REGNAME (kVRegIsDefaultDevice);
1317  DEF_REGNAME (kVRegDesktopFrameBufferStatus);
1318  DEF_REGNAME (kVRegSDIOutput1ColorSpaceMode);
1319  DEF_REGNAME (kVRegSDIOutput2ColorSpaceMode);
1320  DEF_REGNAME (kVRegAudioOutputDelay);
1321  DEF_REGNAME (kVRegTimelapseEnable);
1322  DEF_REGNAME (kVRegTimelapseCaptureValue);
1323  DEF_REGNAME (kVRegTimelapseCaptureUnits);
1324  DEF_REGNAME (kVRegTimelapseIntervalValue);
1325  DEF_REGNAME (kVRegTimelapseIntervalUnits);
1326  DEF_REGNAME (kVRegSDIOutConfig);
1327  DEF_REGNAME (kVRegAnalogInStandard);
1328  DEF_REGNAME (kVRegOutputTimecodeOffset);
1329  DEF_REGNAME (kVRegOutputTimecodeType);
1330  DEF_REGNAME (kVRegQuicktimeUsingBoard);
1331  DEF_REGNAME (kVRegApplicationPID);
1332  DEF_REG (kVRegApplicationCode, mDecodeFourCC, READWRITE, kRegClass_Virtual, kRegClass_NULL, kRegClass_NULL);
1333  DEF_REGNAME (kVRegReleaseApplication);
1334  DEF_REGNAME (kVRegForceApplicationPID);
1335  DEF_REGNAME (kVRegForceApplicationCode);
1336  DEF_REGNAME (kVRegIpConfigStreamRefresh);
1337  DEF_REGNAME (kVRegSDIInConfig);
1338  DEF_REGNAME (kVRegInputChangedCount);
1339  DEF_REGNAME (kVReg8kOutputTransportSelection);
1340  DEF_REGNAME (kVRegAnalogIoSelect);
1341  DEF_REGNAME (kVRegProcAmpSDRegsInitialized);
1342  DEF_REGNAME (kVRegProcAmpStandardDefBrightness);
1343  DEF_REGNAME (kVRegProcAmpStandardDefContrast);
1344  DEF_REGNAME (kVRegProcAmpStandardDefSaturation);
1345  DEF_REGNAME (kVRegProcAmpStandardDefHue);
1346  DEF_REGNAME (kVRegProcAmpStandardDefCbOffset);
1347  DEF_REGNAME (kVRegProcAmpStandardDefCrOffset);
1348  DEF_REGNAME (kVRegProcAmpEndStandardDefRange);
1349  DEF_REGNAME (kVRegProcAmpHDRegsInitialized);
1350  DEF_REGNAME (kVRegProcAmpHighDefBrightness);
1351  DEF_REGNAME (kVRegProcAmpHighDefContrast);
1352  DEF_REGNAME (kVRegProcAmpHighDefSaturationCb);
1353  DEF_REGNAME (kVRegProcAmpHighDefSaturationCr);
1354  DEF_REGNAME (kVRegProcAmpHighDefHue);
1355  DEF_REGNAME (kVRegProcAmpHighDefCbOffset);
1356  DEF_REGNAME (kVRegProcAmpHighDefCrOffset);
1357  DEF_REGNAME (kVRegProcAmpEndHighDefRange);
1358  DEF_REGNAME (kVRegChannel1UserBufferLevel);
1359  DEF_REGNAME (kVRegChannel2UserBufferLevel);
1360  DEF_REGNAME (kVRegInput1UserBufferLevel);
1361  DEF_REGNAME (kVRegInput2UserBufferLevel);
1362  DEF_REGNAME (kVRegProgressivePicture);
1363  DEF_REGNAME (kVRegLUT2Type);
1364  DEF_REGNAME (kVRegLUT3Type);
1365  DEF_REGNAME (kVRegLUT4Type);
1366  DEF_REGNAME (kVRegDigitalOutput3Select);
1367  DEF_REGNAME (kVRegDigitalOutput4Select);
1368  DEF_REGNAME (kVRegHDMIOutputSelect);
1369  DEF_REGNAME (kVRegRGBRangeConverterLUTType);
1370  DEF_REGNAME (kVRegTestPatternChoice);
1371  DEF_REGNAME (kVRegTestPatternFormat);
1372  DEF_REGNAME (kVRegEveryFrameTaskFilter);
1373  DEF_REGNAME (kVRegDefaultInput);
1374  DEF_REGNAME (kVRegDefaultVideoOutMode);
1375  DEF_REGNAME (kVRegDefaultVideoFormat);
1376  DEF_REGNAME (kVRegDigitalOutput5Select);
1377  DEF_REGNAME (kVRegLUT5Type);
1378  DEF_REGNAME (kVRegMacUserModeDebugLevel);
1379  DEF_REGNAME (kVRegMacKernelModeDebugLevel);
1380  DEF_REGNAME (kVRegMacUserModePingLevel);
1381  DEF_REGNAME (kVRegMacKernelModePingLevel);
1382  DEF_REGNAME (kVRegLatencyTimerValue);
1383  DEF_REGNAME (kVRegAudioInputSelect);
1384  DEF_REGNAME (kVRegSerialSuspended);
1385  DEF_REGNAME (kVRegXilinxProgramming);
1386  DEF_REGNAME (kVRegETTDiagLastSerialTimestamp);
1387  DEF_REGNAME (kVRegETTDiagLastSerialTimecode);
1388  DEF_REGNAME (kVRegStartupStatusFlags);
1389  DEF_REGNAME (kVRegRGBRangeMode);
1390  DEF_REGNAME (kVRegEnableQueuedDMAs);
1391  DEF_REGNAME (kVRegBA0MemorySize);
1392  DEF_REGNAME (kVRegBA1MemorySize);
1393  DEF_REGNAME (kVRegBA4MemorySize);
1394  DEF_REGNAME (kVRegNumDmaDriverBuffers);
1395  DEF_REGNAME (kVRegDMADriverBufferPhysicalAddress);
1396  DEF_REGNAME (kVRegBA2MemorySize);
1397  DEF_REGNAME (kVRegAcquireLinuxReferenceCount);
1398  DEF_REGNAME (kVRegReleaseLinuxReferenceCount);
1399  DEF_REGNAME (kVRegAdvancedIndexing);
1400  DEF_REGNAME (kVRegTimeStampLastInput3VerticalLo);
1401  DEF_REGNAME (kVRegTimeStampLastInput3VerticalHi);
1402  DEF_REGNAME (kVRegTimeStampLastInput4VerticalLo);
1403  DEF_REGNAME (kVRegTimeStampLastInput4VerticalHi);
1404  DEF_REGNAME (kVRegTimeStampLastInput5VerticalLo);
1405  DEF_REGNAME (kVRegTimeStampLastInput5VerticalHi);
1406  DEF_REGNAME (kVRegTimeStampLastInput6VerticalLo);
1407  DEF_REGNAME (kVRegTimeStampLastInput6VerticalHi);
1408  DEF_REGNAME (kVRegTimeStampLastInput7VerticalLo);
1409  DEF_REGNAME (kVRegTimeStampLastInput7VerticalHi);
1410  DEF_REGNAME (kVRegTimeStampLastInput8VerticalLo);
1411  DEF_REGNAME (kVRegTimeStampLastInput8VerticalHi);
1412  DEF_REGNAME (kVRegTimeStampLastOutput2VerticalLo);
1413  DEF_REGNAME (kVRegTimeStampLastOutput2VerticalHi);
1414  DEF_REGNAME (kVRegTimeStampLastOutput3VerticalLo);
1415  DEF_REGNAME (kVRegTimeStampLastOutput3VerticalHi);
1416  DEF_REGNAME (kVRegTimeStampLastOutput4VerticalLo);
1417  DEF_REGNAME (kVRegTimeStampLastOutput4VerticalHi);
1418  DEF_REGNAME (kVRegTimeStampLastOutput5VerticalLo);
1419  DEF_REGNAME (kVRegTimeStampLastOutput5VerticalHi);
1420  DEF_REGNAME (kVRegTimeStampLastOutput6VerticalLo);
1421  DEF_REGNAME (kVRegTimeStampLastOutput6VerticalHi);
1422  DEF_REGNAME (kVRegTimeStampLastOutput7VerticalLo);
1423  DEF_REGNAME (kVRegTimeStampLastOutput7VerticalHi);
1424  DEF_REGNAME (kVRegTimeStampLastOutput8VerticalLo);
1425  DEF_REGNAME (kVRegResetCycleCount);
1426  DEF_REGNAME (kVRegUseProgressive);
1427  DEF_REGNAME (kVRegFlashSize);
1428  DEF_REGNAME (kVRegFlashStatus);
1429  DEF_REGNAME (kVRegFlashState);
1430  DEF_REGNAME (kVRegPCIDeviceID);
1431  DEF_REGNAME (kVRegUartRxFifoSize);
1432  DEF_REGNAME (kVRegEFTNeedsUpdating);
1433  DEF_REGNAME (kVRegSuspendSystemAudio);
1434  DEF_REGNAME (kVRegAcquireReferenceCounter);
1435  DEF_REGNAME (kVRegTimeStampLastOutput8VerticalHi);
1436  DEF_REGNAME (kVRegFramesPerVertical);
1437  DEF_REGNAME (kVRegServicesInitialized);
1438  DEF_REGNAME (kVRegFrameBufferGangCount);
1439  DEF_REGNAME (kVRegChannelCrosspointFirst);
1440  DEF_REGNAME (kVRegChannelCrosspointLast);
1441  DEF_REGNAME (kVRegMonAncField1Offset);
1442  DEF_REGNAME (kVRegMonAncField2Offset);
1443  DEF_REGNAME (kVRegFollowInputFormat);
1444  DEF_REG (kVRegAncField1Offset, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1445  DEF_REG (kVRegAncField2Offset, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1446  DEF_REGNAME (kVRegAgentCheck);
1447  DEF_REGNAME (kVReg4kOutputTransportSelection);
1448  DEF_REG (kVRegCustomAncInputSelect, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1449  DEF_REGNAME (kVRegUseThermostat);
1450  DEF_REGNAME (kVRegThermalSamplingRate);
1451  DEF_REGNAME (kVRegFanSpeed);
1452  DEF_REGNAME (kVRegVideoFormatCh1);
1453  DEF_REGNAME (kVRegVideoFormatCh2);
1454  DEF_REGNAME (kVRegVideoFormatCh3);
1455  DEF_REGNAME (kVRegVideoFormatCh4);
1456  DEF_REGNAME (kVRegVideoFormatCh5);
1457  DEF_REGNAME (kVRegVideoFormatCh6);
1458  DEF_REGNAME (kVRegVideoFormatCh7);
1459  DEF_REGNAME (kVRegVideoFormatCh8);
1460 
1461  DEF_REG (kVRegIPAddrEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1462  DEF_REG (kVRegSubnetEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1463  DEF_REG (kVRegGatewayEth0, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1464  DEF_REG (kVRegIPAddrEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1465  DEF_REG (kVRegSubnetEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1466  DEF_REG (kVRegGatewayEth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1467  DEF_REG (kVRegRxcEnable1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1468  DEF_REG (kVRegRxcSfp1RxMatch1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1469  DEF_REG (kVRegRxcSfp1SourceIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1470  DEF_REG (kVRegRxcSfp1DestIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1471  DEF_REG (kVRegRxcSfp1SourcePort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1472  DEF_REG (kVRegRxcSfp1DestPort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1473  DEF_REG (kVRegRxcSfp1Vlan1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1474  DEF_REG (kVRegRxcSfp2RxMatch1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1475  DEF_REG (kVRegRxcSfp2SourceIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1476  DEF_REG (kVRegRxcSfp2DestIp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1477  DEF_REG (kVRegRxcSfp2SourcePort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1478  DEF_REG (kVRegRxcSfp2DestPort1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1479  DEF_REG (kVRegRxcSfp2Vlan1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1480  DEF_REG (kVRegRxcSsrc1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1481  DEF_REG (kVRegRxcPlayoutDelay1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1482  DEF_REG (kVRegRxcEnable2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1483  DEF_REG (kVRegRxcSfp1RxMatch2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1484  DEF_REG (kVRegRxcSfp1SourceIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1485  DEF_REG (kVRegRxcSfp1DestIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1486  DEF_REG (kVRegRxcSfp1SourcePort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1487  DEF_REG (kVRegRxcSfp1DestPort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1488  DEF_REG (kVRegRxcSfp1Vlan2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1489  DEF_REG (kVRegRxcSfp2RxMatch2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1490  DEF_REG (kVRegRxcSfp2SourceIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1491  DEF_REG (kVRegRxcSfp2DestIp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1492  DEF_REG (kVRegRxcSfp2SourcePort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1493  DEF_REG (kVRegRxcSfp2DestPort2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1494  DEF_REG (kVRegRxcSfp2Vlan2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1495  DEF_REG (kVRegRxcSsrc2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1496  DEF_REG (kVRegRxcPlayoutDelay2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1497  DEF_REG (kVRegTxcEnable3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1498  DEF_REG (kVRegTxcSfp1LocalPort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1499  DEF_REG (kVRegTxcSfp1RemoteIp3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1500  DEF_REG (kVRegTxcSfp1RemotePort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1501  DEF_REG (kVRegTxcSfp2LocalPort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1502  DEF_REG (kVRegTxcSfp2RemoteIp3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1503  DEF_REG (kVRegTxcSfp2RemotePort3, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1504  DEF_REG (kVRegTxcEnable4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1505  DEF_REG (kVRegTxcSfp1LocalPort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1506  DEF_REG (kVRegTxcSfp1RemoteIp4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1507  DEF_REG (kVRegTxcSfp1RemotePort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1508  DEF_REG (kVRegTxcSfp2LocalPort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1509  DEF_REG (kVRegTxcSfp2RemoteIp4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1510  DEF_REG (kVRegTxcSfp2RemotePort4, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1511  DEF_REG (kVRegMailBoxAcquire, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1512  DEF_REG (kVRegMailBoxRelease, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1513  DEF_REG (kVRegMailBoxAbort, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1514  DEF_REG (kVRegMailBoxTimeoutNS, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1515  DEF_REG (kVRegRxc_2DecodeSelectionMode1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1516  DEF_REG (kVRegRxc_2DecodeProgramNumber1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1517  DEF_REG (kVRegRxc_2DecodeProgramPID1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1518  DEF_REG (kVRegRxc_2DecodeAudioNumber1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1519  DEF_REG (kVRegRxc_2DecodeSelectionMode2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1520  DEF_REG (kVRegRxc_2DecodeProgramNumber2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1521  DEF_REG (kVRegRxc_2DecodeProgramPID2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1522  DEF_REG (kVRegRxc_2DecodeAudioNumber2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Input, kRegClass_NULL);
1523  DEF_REG (kVRegTxc_2EncodeVideoFormat1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1524  DEF_REG (kVRegTxc_2EncodeUllMode1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1525  DEF_REG (kVRegTxc_2EncodeBitDepth1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1526  DEF_REG (kVRegTxc_2EncodeChromaSubSamp1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1527  DEF_REG (kVRegTxc_2EncodeMbps1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1528  DEF_REG (kVRegTxc_2EncodeAudioChannels1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1529  DEF_REG (kVRegTxc_2EncodeStreamType1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1530  DEF_REG (kVRegTxc_2EncodeProgramPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1531  DEF_REG (kVRegTxc_2EncodeVideoPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1532  DEF_REG (kVRegTxc_2EncodePcrPid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1533  DEF_REG (kVRegTxc_2EncodeAudio1Pid1, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1534  DEF_REG (kVRegTxc_2EncodeVideoFormat2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1535  DEF_REG (kVRegTxc_2EncodeUllMode2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1536  DEF_REG (kVRegTxc_2EncodeBitDepth2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1537  DEF_REG (kVRegTxc_2EncodeChromaSubSamp2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1538  DEF_REG (kVRegTxc_2EncodeMbps2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1539  DEF_REG (kVRegTxc_2EncodeAudioChannels2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1540  DEF_REG (kVRegTxc_2EncodeStreamType2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1541  DEF_REG (kVRegTxc_2EncodeProgramPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1542  DEF_REG (kVRegTxc_2EncodeVideoPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1543  DEF_REG (kVRegTxc_2EncodePcrPid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1544  DEF_REG (kVRegTxc_2EncodeAudio1Pid2, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_Output, kRegClass_NULL);
1545  DEF_REG (kVReg2022_7Enable, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1546  DEF_REG (kVReg2022_7NetworkPathDiff, mDefaultRegDecoder, READWRITE, kRegClass_IP, kRegClass_NULL, kRegClass_NULL);
1547  DEF_REGNAME (kVRegKIPRxCfgError);
1548  DEF_REGNAME (kVRegKIPTxCfgError);
1549  DEF_REGNAME (kVRegKIPEncCfgError);
1550  DEF_REGNAME (kVRegKIPDecCfgError);
1551  DEF_REGNAME (kVRegKIPNetCfgError);
1552  DEF_REG (kVRegUseHDMI420Mode, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_NULL, kRegClass_NULL);
1553  DEF_REGNAME (kVRegUserDefinedDBB);
1554  DEF_REG (kVRegHDMIOutAudioChannels, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_HDMI, kRegClass_NULL);
1555  DEF_REG (kVRegZeroHostAncPostCapture, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1556  DEF_REG (kVRegZeroDeviceAncPostCapture, mDefaultRegDecoder, READWRITE, kRegClass_Anc, kRegClass_NULL, kRegClass_NULL);
1557  DEF_REG (kVRegAudioMonitorChannelSelect, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1558  DEF_REG (kVRegAudioMixerOverrideState, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1559  DEF_REG (kVRegAudioMixerSourceMainEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1560  DEF_REG (kVRegAudioMixerSourceAux1Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1561  DEF_REG (kVRegAudioMixerSourceAux2Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1562  DEF_REG (kVRegAudioMixerSourceMainGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1563  DEF_REG (kVRegAudioMixerSourceAux1Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1564  DEF_REG (kVRegAudioMixerSourceAux2Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1565  DEF_REG (kVRegAudioCapMixerSourceMainEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1566  DEF_REG (kVRegAudioCapMixerSourceAux1Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1567  DEF_REG (kVRegAudioCapMixerSourceAux2Enable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1568  DEF_REG (kVRegAudioCapMixerSourceMainGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1569  DEF_REG (kVRegAudioCapMixerSourceAux1Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1570  DEF_REG (kVRegAudioCapMixerSourceAux2Gain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1571  DEF_REGNAME (kVRegSwizzle4kInput);
1572  DEF_REGNAME (kVRegSwizzle4kOutput);
1573  DEF_REG (kVRegAnalogAudioIOConfiguration, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1574  DEF_REGNAME (kVRegHdmiHdrOutChanged);
1575  DEF_REGNAME (kVRegDisableAutoVPID);
1576  DEF_REGNAME (kVRegEnableBT2020);
1577  DEF_REGNAME (kVRegHdmiHdrOutMode);
1578  DEF_REGNAME (kVRegServicesForceInit);
1579  DEF_REGNAME (kVRegServicesModeFinal);
1580 
1581  DEF_REG (kVRegNTV2VPIDTransferCharacteristics1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1582  DEF_REG (kVRegNTV2VPIDColorimetry1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1583  DEF_REG (kVRegNTV2VPIDLuminance1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1584  DEF_REG (kVRegNTV2VPIDTransferCharacteristics, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1585  DEF_REG (kVRegNTV2VPIDColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1586  DEF_REG (kVRegNTV2VPIDLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel1);
1587 
1588  DEF_REG (kVRegNTV2VPIDTransferCharacteristics2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1589  DEF_REG (kVRegNTV2VPIDColorimetry2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1590  DEF_REG (kVRegNTV2VPIDLuminance2, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel2);
1591 
1592  DEF_REG (kVRegNTV2VPIDTransferCharacteristics3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1593  DEF_REG (kVRegNTV2VPIDColorimetry3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1594  DEF_REG (kVRegNTV2VPIDLuminance3, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel3);
1595 
1596  DEF_REG (kVRegNTV2VPIDTransferCharacteristics4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1597  DEF_REG (kVRegNTV2VPIDColorimetry4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1598  DEF_REG (kVRegNTV2VPIDLuminance4, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel4);
1599 
1600  DEF_REG (kVRegNTV2VPIDTransferCharacteristics5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1601  DEF_REG (kVRegNTV2VPIDColorimetry5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1602  DEF_REG (kVRegNTV2VPIDLuminance5, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel5);
1603 
1604  DEF_REG (kVRegNTV2VPIDTransferCharacteristics6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1605  DEF_REG (kVRegNTV2VPIDColorimetry6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1606  DEF_REG (kVRegNTV2VPIDLuminance6, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel6);
1607 
1608  DEF_REG (kVRegNTV2VPIDTransferCharacteristics7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1609  DEF_REG (kVRegNTV2VPIDColorimetry7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1610  DEF_REG (kVRegNTV2VPIDLuminance7, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel7);
1611 
1612  DEF_REG (kVRegNTV2VPIDTransferCharacteristics8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1613  DEF_REG (kVRegNTV2VPIDColorimetry8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1614  DEF_REG (kVRegNTV2VPIDLuminance8, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_VPID, kRegClass_Channel8);
1615 
1616  DEF_REG (kVRegUserColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1617  DEF_REG (kVRegUserTransfer, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1618  DEF_REG (kVRegUserLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1619 
1620  DEF_REG (kVRegHdrColorimetryCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1621  DEF_REG (kVRegHdrTransferCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1622  DEF_REG (kVRegHdrLuminanceCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1623  DEF_REG (kVRegHdrGreenXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1624  DEF_REG (kVRegHdrGreenYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1625  DEF_REG (kVRegHdrBlueXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1626  DEF_REG (kVRegHdrBlueYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1627  DEF_REG (kVRegHdrRedXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1628  DEF_REG (kVRegHdrRedYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1629  DEF_REG (kVRegHdrWhiteXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1630  DEF_REG (kVRegHdrWhiteYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1631  DEF_REG (kVRegHdrMasterLumMaxCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1632  DEF_REG (kVRegHdrMasterLumMinCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1633  DEF_REG (kVRegHdrMaxCLLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1634  DEF_REG (kVRegHdrMaxFALLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1635  DEF_REG (kVRegHDROverrideState, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_NULL, kRegClass_NULL);
1636  DEF_REG (kVRegPCIMaxReadRequestSize, mDefaultRegDecoder, READWRITE, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1637  DEF_REG (kVRegUserInColorimetry, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1638  DEF_REG (kVRegUserInTransfer, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1639  DEF_REG (kVRegUserInLuminance, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1640  DEF_REG (kVRegHdrInColorimetryCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1641  DEF_REG (kVRegHdrInTransferCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1642  DEF_REG (kVRegHdrInLuminanceCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1643  DEF_REG (kVRegHdrInGreenXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1644  DEF_REG (kVRegHdrInGreenYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1645  DEF_REG (kVRegHdrInBlueXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1646  DEF_REG (kVRegHdrInBlueYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1647  DEF_REG (kVRegHdrInRedXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1648  DEF_REG (kVRegHdrInRedYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1649  DEF_REG (kVRegHdrInWhiteXCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1650  DEF_REG (kVRegHdrInWhiteYCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1651  DEF_REG (kVRegHdrInMasterLumMaxCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1652  DEF_REG (kVRegHdrInMasterLumMinCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1653  DEF_REG (kVRegHdrInMaxCLLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1654  DEF_REG (kVRegHdrInMaxFALLCh1, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1655  DEF_REG (kVRegHDRInOverrideState, mDefaultRegDecoder, READWRITE, kRegClass_HDR, kRegClass_Input,kRegClass_NULL);
1656  DEF_REG (kVRegNTV2VPIDRGBRange1, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1657  DEF_REG (kVRegNTV2VPIDRGBRange2, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1658  DEF_REG (kVRegNTV2VPIDRGBRange3, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1659  DEF_REG (kVRegNTV2VPIDRGBRange4, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1660  DEF_REG (kVRegNTV2VPIDRGBRange5, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1661  DEF_REG (kVRegNTV2VPIDRGBRange6, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1662  DEF_REG (kVRegNTV2VPIDRGBRange7, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1663  DEF_REG (kVRegNTV2VPIDRGBRange8, mDefaultRegDecoder, READWRITE, kRegClass_VPID, kRegClass_NULL, kRegClass_NULL);
1664 
1665  DEF_REG (kVRegRotaryGainOverrideEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1666  DEF_REG (kVRegAudioMixerOutputGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1667  DEF_REG (kVRegAudioHeadphoneGain, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1668  DEF_REG (kVRegAudioMixerOutputEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1669  DEF_REG (kVRegAudioHeadphoneEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1670  DEF_REG (kVRegAudioEncoderOutputEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_Output, kRegClass_NULL);
1671  DEF_REG (kVRegAudioEncoderHeadphoneEnable, mDefaultRegDecoder, READWRITE, kRegClass_Audio, kRegClass_NULL, kRegClass_NULL);
1672 
1673  DEF_REG (kVRegDmaTransferRateC2H1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1674  DEF_REG (kVRegDmaHardwareRateC2H1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1675  DEF_REG (kVRegDmaTransferRateH2C1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1676  DEF_REG (kVRegDmaHardwareRateH2C1, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1677  DEF_REG (kVRegDmaTransferRateC2H2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1678  DEF_REG (kVRegDmaHardwareRateC2H2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1679  DEF_REG (kVRegDmaTransferRateH2C2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1680  DEF_REG (kVRegDmaHardwareRateH2C2, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1681  DEF_REG (kVRegDmaTransferRateC2H3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1682  DEF_REG (kVRegDmaHardwareRateC2H3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1683  DEF_REG (kVRegDmaTransferRateH2C3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1684  DEF_REG (kVRegDmaHardwareRateH2C3, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1685  DEF_REG (kVRegDmaTransferRateC2H4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1686  DEF_REG (kVRegDmaHardwareRateC2H4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1687  DEF_REG (kVRegDmaTransferRateH2C4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1688  DEF_REG (kVRegDmaHardwareRateH2C4, mDMAXferRateRegDecoder, READONLY, kRegClass_DMA, kRegClass_NULL, kRegClass_NULL);
1689 
1690  DEF_REG (kVRegHDMIInAviInfo1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1691  DEF_REG (kVRegHDMIInDrmInfo1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1692  DEF_REG (kVRegHDMIInDrmGreenPrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1693  DEF_REG (kVRegHDMIInDrmBluePrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1694  DEF_REG (kVRegHDMIInDrmRedPrimary1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1695  DEF_REG (kVRegHDMIInDrmWhitePoint1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1696  DEF_REG (kVRegHDMIInDrmMasteringLuminence1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1697  DEF_REG (kVRegHDMIInDrmLightLevel1, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1698 
1699  DEF_REG (kVRegHDMIInAviInfo2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_NULL);
1700  DEF_REG (kVRegHDMIInDrmInfo2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1701  DEF_REG (kVRegHDMIInDrmGreenPrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1702  DEF_REG (kVRegHDMIInDrmBluePrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1703  DEF_REG (kVRegHDMIInDrmRedPrimary2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1704  DEF_REG (kVRegHDMIInDrmWhitePoint2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1705  DEF_REG (kVRegHDMIInDrmMasteringLuminence2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1706  DEF_REG (kVRegHDMIInDrmLightLevel2, mDefaultRegDecoder, READWRITE, kRegClass_HDMI, kRegClass_Input, kRegClass_HDR);
1707 
1708  DEF_REG (kVRegBaseFirmwareDeviceID, mDecodeBoardID, READWRITE, kRegClass_NULL, kRegClass_NULL, kRegClass_NULL);
1709 
1710  DEF_REG (kVRegHDMIOutStatus1, mDecodeHDMIOutputStatus,READWRITE, kRegClass_HDMI, kRegClass_Output, kRegClass_NULL);
1711  DEF_REG (kVRegAudioOutputToneSelect, mDefaultRegDecoder, READWRITE, kRegClass_Audio,kRegClass_Output, kRegClass_NULL);
1712  DEF_REG (kVRegDynFirmwareUpdateCounts, mDecodeDynFWUpdateCounts,READWRITE,kRegClass_NULL,kRegClass_NULL,kRegClass_NULL);
1713 
1714  DEF_REGNAME (kVRegLastAJA);
1715  DEF_REGNAME (kVRegFirstOEM);
1716 
1717  for (ULWord ndx(1); ndx < 1024; ndx++) // <== Start at 1, kVRegDriverVersion already done
1718  {
1719  ostringstream oss; oss << "VIRTUALREG_START+" << ndx;
1720  const string regName (oss.str());
1721  const ULWord regNum (VIRTUALREG_START + ndx);
1722  if (mRegNumToStringMap.find(regNum) == mRegNumToStringMap.end())
1723  {
1724  mRegNumToStringMap.insert (RegNumToStringPair(regNum, regName));
1725  mStringToRegNumMMap.insert (StringToRegNumPair(ToLower(regName), regNum));
1726  }
1727  DefineRegDecoder (regNum, mDefaultRegDecoder);
1728  DefineRegReadWrite (regNum, READWRITE);
1729  DefineRegClass (regNum, kRegClass_Virtual);
1730  }
1731  DefineRegClass (kVRegAudioOutputToneSelect, kRegClass_Audio);
1732  DefineRegClass (kVRegMonAncField1Offset, kRegClass_Anc);
1733  DefineRegClass (kVRegMonAncField2Offset, kRegClass_Anc);
1734  DefineRegClass (kVRegAncField1Offset, kRegClass_Anc);
1735  DefineRegClass (kVRegAncField2Offset, kRegClass_Anc);
1736  } // SetupVRegs
1737 
1738 public:
1739  static ostream & PrintLabelValuePairs (ostream & oss, const AJALabelValuePairs & inLabelValuePairs)
1740  {
1741  for (AJALabelValuePairsConstIter it(inLabelValuePairs.begin()); it != inLabelValuePairs.end(); )
1742  {
1743  const string & label (it->first);
1744  const string & value (it->second);
1745  if (label.empty())
1746  ;
1747  else if (label.at(label.length()-1) != ' ' && label.at(label.length()-1) != ':') // C++11 "label.back()" would be better
1748  oss << label << ": " << value;
1749  else if (label.at(label.length()-1) == ':') // C++11 "label.back()" would be better
1750  oss << label << " " << value;
1751  else
1752  oss << label << value;
1753  if (++it != inLabelValuePairs.end())
1754  oss << endl;
1755  }
1756  return oss;
1757  }
1758 
1759  string RegNameToString (const uint32_t inRegNum) const
1760  {
1761  AJAAutoLock lock(&mGuardMutex);
1762  RegNumToStringMap::const_iterator iter (mRegNumToStringMap.find (inRegNum));
1763  if (iter != mRegNumToStringMap.end())
1764  return iter->second;
1765 
1766  ostringstream oss; oss << "Reg ";
1767  if (inRegNum <= kRegNumRegisters)
1768  oss << DEC(inRegNum);
1769  else if (inRegNum <= 0x0000FFFF)
1770  oss << xHEX0N(inRegNum,4);
1771  else
1772  oss << xHEX0N(inRegNum,8);
1773  return oss.str();
1774  }
1775 
1776  string RegValueToString (const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
1777  {
1778  AJAAutoLock lock(&mGuardMutex);
1779  RegNumToDecoderMap::const_iterator iter(mRegNumToDecoderMap.find(inRegNum));
1780  ostringstream oss;
1781  if (iter != mRegNumToDecoderMap.end() && iter->second)
1782  {
1783  const Decoder * pDecoder (iter->second);
1784  oss << (*pDecoder)(inRegNum, inRegValue, inDeviceID);
1785  }
1786  return oss.str();
1787  }
1788 
1789  bool IsRegInClass (const uint32_t inRegNum, const string & inClassName) const
1790  {
1791  AJAAutoLock lock(&mGuardMutex);
1792  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.find(inClassName)); it != mRegClassToRegNumMMap.end() && it->first == inClassName; ++it)
1793  if (it->second == inRegNum)
1794  return true;
1795  return false;
1796  }
1797 
1798  inline bool IsRegisterWriteOnly (const uint32_t inRegNum) const {return IsRegInClass (inRegNum, kRegClass_WriteOnly);}
1799  inline bool IsRegisterReadOnly (const uint32_t inRegNum) const {return IsRegInClass (inRegNum, kRegClass_ReadOnly);}
1800 
1801  NTV2StringSet GetAllRegisterClasses (void) const
1802  {
1803  AJAAutoLock lock(&mGuardMutex);
1804  if (mAllRegClasses.empty())
1805  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.begin()); it != mRegClassToRegNumMMap.end(); ++it)
1806  if (mAllRegClasses.find(it->first) == mAllRegClasses.end())
1807  mAllRegClasses.insert(it->first);
1808  return mAllRegClasses;
1809  }
1810 
1811  NTV2StringSet GetRegisterClasses (const uint32_t inRegNum, const bool inRemovePrefix) const
1812  {
1813  AJAAutoLock lock(&mGuardMutex);
1814  NTV2StringSet result;
1815  NTV2StringSet allClasses (GetAllRegisterClasses());
1816  for (NTV2StringSetConstIter it(allClasses.begin()); it != allClasses.end(); ++it)
1817  if (IsRegInClass (inRegNum, *it))
1818  {
1819  string str(*it);
1820  if (inRemovePrefix)
1821  str.erase(0, 10); // Remove "kRegClass_" prefix
1822  if (result.find(str) == result.end())
1823  result.insert(str);
1824  }
1825  return result;
1826  }
1827 
1828  NTV2RegNumSet GetRegistersForClass (const string & inClassName) const
1829  {
1830  AJAAutoLock lock(&mGuardMutex);
1831  NTV2RegNumSet result;
1832  for (RegClassToRegNumConstIter it(mRegClassToRegNumMMap.find(inClassName)); it != mRegClassToRegNumMMap.end() && it->first == inClassName; ++it)
1833  if (result.find(it->second) == result.end())
1834  result.insert(it->second);
1835  return result;
1836  }
1837 
1838  NTV2RegNumSet GetRegistersForDevice (const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude) const
1839  {
1840  NTV2RegNumSet result;
1841  const uint32_t maxRegNum (::NTV2DeviceGetMaxRegisterNumber(inDeviceID));
1842 
1843  for (uint32_t regNum (0); regNum <= maxRegNum; regNum++)
1844  result.insert(regNum);
1845 
1846  AJAAutoLock lock(&mGuardMutex);
1847 
1848  if (::NTV2DeviceCanDoCustomAnc(inDeviceID))
1849  {
1850  const NTV2RegNumSet ancRegs (GetRegistersForClass(kRegClass_Anc));
1851  const UWord numVideoInputs (::NTV2DeviceGetNumVideoInputs(inDeviceID));
1852  const UWord numVideoOutputs (::NTV2DeviceGetNumVideoOutputs(inDeviceID));
1853  const UWord numSpigots(numVideoInputs > numVideoOutputs ? numVideoInputs : numVideoOutputs);
1854  NTV2RegNumSet allChanRegs; // For just those channels it supports
1855  for (UWord num(0); num < numSpigots; num++)
1856  {
1857  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1858  allChanRegs.insert(chRegs.begin(), chRegs.end());
1859  }
1860  std::set_intersection (ancRegs.begin(), ancRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1861  }
1862 
1863  if (::NTV2DeviceCanDoCustomAux(inDeviceID))
1864  {
1865  const NTV2RegNumSet auxRegs (GetRegistersForClass(kRegClass_Aux));
1866  const UWord numVideoInputs (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID));
1867  const UWord numVideoOutputs (::NTV2DeviceGetNumHDMIVideoOutputs(inDeviceID));
1868  const UWord numSpigots(numVideoInputs > numVideoOutputs ? numVideoInputs : numVideoOutputs);
1869  NTV2RegNumSet allChanRegs; // For just those channels it supports
1870  for (UWord num(0); num < numSpigots; num++)
1871  {
1872  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1873  allChanRegs.insert(chRegs.begin(), chRegs.end());
1874  }
1875  std::set_intersection (auxRegs.begin(), auxRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1876  }
1877 
1878  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
1879  {
1880  const NTV2RegNumSet sdiErrRegs (GetRegistersForClass(kRegClass_SDIError));
1881  result.insert(sdiErrRegs.begin(), sdiErrRegs.end());
1882  }
1883 
1884  if (::NTV2DeviceCanDoAudioMixer(inDeviceID))
1885  {
1886  for (ULWord regNum(kRegAudioMixerInputSelects); regNum <= kRegAudioMixerAux2GainCh2; regNum++)
1887  result.insert(regNum);
1888  for (ULWord regNum(kRegAudioMixerAux1InputLevels); regNum <= kRegAudioMixerMainOutputLevelsPair7; regNum++)
1889  result.insert(regNum);
1890  }
1891 
1892  if (::NTV2DeviceHasXilinxDMA(inDeviceID))
1893  {
1894  }
1895 
1896  if (::NTV2DeviceCanDoEnhancedCSC(inDeviceID))
1897  {
1898  const NTV2RegNumSet ecscRegs (GetRegistersForClass(kRegClass_CSC));
1899  const UWord numCSCs (::NTV2DeviceGetNumCSCs(inDeviceID));
1900  NTV2RegNumSet allChanRegs; // For just those CSCs it supports
1901  for (UWord num(0); num < numCSCs; num++)
1902  {
1903  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1904  allChanRegs.insert(chRegs.begin(), chRegs.end());
1905  }
1906  std::set_intersection (ecscRegs.begin(), ecscRegs.end(), allChanRegs.begin(), allChanRegs.end(), std::inserter(result, result.begin()));
1907  }
1908 
1909  if (::NTV2DeviceGetNumLUTs(inDeviceID))
1910  {
1911  const NTV2RegNumSet LUTRegs (GetRegistersForClass(kRegClass_LUT));
1912  result.insert(LUTRegs.begin(), LUTRegs.end());
1913  }
1914 
1915  if (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID) > 1) // KonaHDMI
1916  {
1917  for (ULWord regNum = 0x1d00; regNum <= 0x1d1f; regNum++)
1918  result.insert(regNum);
1919  for (ULWord regNum = 0x2500; regNum <= 0x251f; regNum++)
1920  result.insert(regNum);
1921  for (ULWord regNum = 0x2c00; regNum <= 0x2c1f; regNum++)
1922  result.insert(regNum);
1923  for (ULWord regNum = 0x3000; regNum <= 0x301f; regNum++)
1924  result.insert(regNum);
1925  }
1926  else if (NTV2DeviceGetHDMIVersion(inDeviceID) > 3) // Io4KPlus, IoIP2022, IoIP2110, Kona5, KonaHDMI
1927  { // v4 HDMI: Io4K+, IoIP2022, IoIP2110, Kona5, KonaHDMI...
1928  for (ULWord regNum = 0x1d00; regNum <= 0x1d1f; regNum++)
1929  result.insert(regNum);
1930  for (ULWord regNum = 0x1d40; regNum <= 0x1d5f; regNum++)
1931  result.insert(regNum);
1932  for (ULWord regNum = 0x3C00; regNum <= 0x3C0A; regNum++)
1933  result.insert(regNum);
1934  }
1935 
1936  if (inDeviceID == DEVICE_ID_IOX3 || inDeviceID == DEVICE_ID_KONA5_8K_MV_TX)
1937  { // IoX3 and some Kona5 support MultiViewer/MultiRaster
1938  result.insert(ULWord(kRegMRQ1Control));
1939  result.insert(ULWord(kRegMRQ2Control));
1940  result.insert(ULWord(kRegMRQ3Control));
1941  result.insert(ULWord(kRegMRQ4Control));
1942  result.insert(ULWord(kRegMROutControl));
1943  result.insert(ULWord(kRegMRSupport));
1944  }
1945 
1946  if (NTV2DeviceHasNTV4FrameStores(inDeviceID))
1947  {
1948  const NTV2RegNumSet ntv4FSRegs (GetRegistersForClass(kRegClass_NTV4FrameStore));
1949  const UWord numFrameStores (::NTV2DeviceGetNumFrameStores(inDeviceID));
1950  NTV2RegNumSet chanRegs; // Just the supported NTV4 FrameStores
1951  for (UWord num(0); num < numFrameStores; num++)
1952  {
1953  const NTV2RegNumSet chRegs (GetRegistersForClass(gChlClasses[num]));
1954  chanRegs.insert(chRegs.begin(), chRegs.end());
1955  }
1956  std::set_intersection (ntv4FSRegs.begin(), ntv4FSRegs.end(), chanRegs.begin(), chanRegs.end(), std::inserter(result, result.begin()));
1957  }
1958 
1959  if (NTV2DeviceCanDoIDSwitch(inDeviceID))
1960  {
1961  result.insert(ULWord(kRegIDSwitch));
1962  }
1963 
1964  if (NTV2DeviceHasPWMFanControl(inDeviceID))
1965  {
1966  result.insert(ULWord(kRegPWMFanControl));
1967  result.insert(ULWord(kRegPWMFanStatus));
1968  }
1969 
1970  if (NTV2DeviceCanDoBreakoutBoard(inDeviceID))
1971  {
1972  result.insert(ULWord(kRegBOBStatus));
1973  result.insert(ULWord(kRegBOBGPIInData));
1974  result.insert(ULWord(kRegBOBGPIInterruptControl));
1975  result.insert(ULWord(kRegBOBGPIOutData));
1976  result.insert(ULWord(kRegBOBAudioControl));
1977  }
1978 
1979  if (NTV2DeviceHasBracketLED(inDeviceID))
1980  {
1981  result.insert(ULWord(kRegLEDReserved0));
1982  result.insert(ULWord(kRegLEDClockDivide));
1983  result.insert(ULWord(kRegLEDReserved2));
1984  result.insert(ULWord(kRegLEDReserved3));
1985  result.insert(ULWord(kRegLEDSDI1Control));
1986  result.insert(ULWord(kRegLEDSDI2Control));
1987  result.insert(ULWord(kRegLEDHDMIInControl));
1988  result.insert(ULWord(kRegLEDHDMIOutControl));
1989  }
1990 
1991  if (NTV2DeviceCanDoClockMonitor(inDeviceID))
1992  {
1993  result.insert(ULWord(kRegCMWControl));
1994  result.insert(ULWord(kRegCMW1485Out));
1995  result.insert(ULWord(kRegCMW14835Out));
1996  result.insert(ULWord(kRegCMW27Out));
1997  result.insert(ULWord(kRegCMW12288Out));
1998  result.insert(ULWord(kRegCMWHDMIOut));
1999  }
2000 
2001  if (inOtherRegsToInclude & kIncludeOtherRegs_VRegs)
2002  {
2003  const NTV2RegNumSet vRegs (GetRegistersForClass(kRegClass_Virtual));
2004  result.insert(vRegs.begin(), vRegs.end());
2005  }
2006 
2007  if (inOtherRegsToInclude & kIncludeOtherRegs_XptROM)
2008  {
2009  const NTV2RegNumSet xptMapRegs (GetRegistersForClass(kRegClass_XptROM));
2010  result.insert(xptMapRegs.begin(), xptMapRegs.end());
2011  }
2012  return result;
2013  }
2014 
2015 
2016  NTV2RegNumSet GetRegistersWithName (const string & inName, const int inMatchStyle = EXACTMATCH) const
2017  {
2018  NTV2RegNumSet result;
2019  string nameStr(inName);
2020  const size_t nameStrLen(aja::lower(nameStr).length());
2021  StringToRegNumConstIter it;
2022  AJAAutoLock lock(&mGuardMutex);
2023  if (inMatchStyle == EXACTMATCH)
2024  {
2025  it = mStringToRegNumMMap.find(nameStr);
2026  if (it != mStringToRegNumMMap.end())
2027  result.insert(it->second);
2028  return result;
2029  }
2030  // Inexact match...
2031  for (it = mStringToRegNumMMap.begin(); it != mStringToRegNumMMap.end(); ++it)
2032  {
2033  const size_t pos(it->first.find(nameStr));
2034  if (pos == string::npos)
2035  continue;
2036  switch (inMatchStyle)
2037  {
2038  case CONTAINS: result.insert(it->second); break;
2039  case STARTSWITH: if (pos == 0)
2040  {result.insert(it->second);}
2041  break;
2042  case ENDSWITH: if (pos+nameStrLen == it->first.length())
2043  {result.insert(it->second);}
2044  break;
2045  default: break;
2046  }
2047  }
2048  return result;
2049  }
2050 
2051  bool GetXptRegNumAndMaskIndex (const NTV2InputCrosspointID inInputXpt, uint32_t & outXptRegNum, uint32_t & outMaskIndex) const
2052  {
2053  AJAAutoLock lock(&mGuardMutex);
2054  outXptRegNum = 0xFFFFFFFF;
2055  outMaskIndex = 0xFFFFFFFF;
2056  InputXpt2XptRegNumMaskIndexMapConstIter iter (mInputXpt2XptRegNumMaskIndexMap.find (inInputXpt));
2057  if (iter == mInputXpt2XptRegNumMaskIndexMap.end())
2058  return false;
2059  outXptRegNum = iter->second.first;
2060  outMaskIndex = iter->second.second;
2061  return true;
2062  }
2063 
2064  NTV2InputCrosspointID GetInputCrosspointID (const uint32_t inXptRegNum, const uint32_t inMaskIndex) const
2065  {
2066  AJAAutoLock lock(&mGuardMutex);
2067  const XptRegNumAndMaskIndex key (inXptRegNum, inMaskIndex);
2068  XptRegNumMaskIndex2InputXptMapConstIter iter (mXptRegNumMaskIndex2InputXptMap.find (key));
2069  if (iter != mXptRegNumMaskIndex2InputXptMap.end())
2070  return iter->second;
2071  return NTV2_INPUT_CROSSPOINT_INVALID;
2072  }
2073 
2074  ostream & Print (ostream & inOutStream) const
2075  {
2076  AJAAutoLock lock(&mGuardMutex);
2077  static const string sLineBreak (96, '=');
2078  static const uint32_t sMasks[4] = {0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000};
2079 
2080  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegNumToStringMap: " << mRegNumToStringMap.size() << " mappings:" << endl << sLineBreak << endl;
2081  for (RegNumToStringMap::const_iterator it (mRegNumToStringMap.begin()); it != mRegNumToStringMap.end(); ++it)
2082  inOutStream << "reg " << setw(5) << it->first << "(" << HEX0N(it->first,8) << dec << ") => '" << it->second << "'" << endl;
2083 
2084  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegNumToDecoderMap: " << mRegNumToDecoderMap.size() << " mappings:" << endl << sLineBreak << endl;
2085  for (RegNumToDecoderMap::const_iterator it (mRegNumToDecoderMap.begin()); it != mRegNumToDecoderMap.end(); ++it)
2086  inOutStream << "reg " << setw(5) << it->first << "(" << HEX0N(it->first,8) << dec << ") => " << (it->second == &mDefaultRegDecoder ? "(default decoder)" : "Custom Decoder") << endl;
2087 
2088  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of RegClassToRegNumMMap: " << mRegClassToRegNumMMap.size() << " mappings:" << endl << sLineBreak << endl;
2089  for (RegClassToRegNumMMap::const_iterator it (mRegClassToRegNumMMap.begin()); it != mRegClassToRegNumMMap.end(); ++it)
2090  inOutStream << setw(32) << it->first << " => reg " << setw(5) << it->second << "(" << HEX0N(it->second,8) << dec << ") " << RegNameToString(it->second) << endl;
2091 
2092  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of StringToRegNumMMap: " << mStringToRegNumMMap.size() << " mappings:" << endl << sLineBreak << endl;
2093  for (StringToRegNumMMap::const_iterator it (mStringToRegNumMMap.begin()); it != mStringToRegNumMMap.end(); ++it)
2094  inOutStream << setw(32) << it->first << " => reg " << setw(5) << it->second << "(" << HEX0N(it->second,8) << dec << ") " << RegNameToString(it->second) << endl;
2095 
2096  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of InputXpt2XptRegNumMaskIndexMap: " << mInputXpt2XptRegNumMaskIndexMap.size() << " mappings:" << endl << sLineBreak << endl;
2097  for (InputXpt2XptRegNumMaskIndexMap::const_iterator it (mInputXpt2XptRegNumMaskIndexMap.begin()); it != mInputXpt2XptRegNumMaskIndexMap.end(); ++it)
2098  inOutStream << setw(32) << ::NTV2InputCrosspointIDToString(it->first) << "(" << HEX0N(it->first,2)
2099  << ") => reg " << setw(3) << it->second.first << "(" << HEX0N(it->second.first,3) << dec << "|" << setw(20) << RegNameToString(it->second.first)
2100  << ") mask " << it->second.second << "(" << HEX0N(sMasks[it->second.second],8) << ")" << endl;
2101 
2102  inOutStream << endl << sLineBreak << endl << "RegisterExpert: Dump of XptRegNumMaskIndex2InputXptMap: " << mXptRegNumMaskIndex2InputXptMap.size() << " mappings:" << endl << sLineBreak << endl;
2103  for (XptRegNumMaskIndex2InputXptMap::const_iterator it (mXptRegNumMaskIndex2InputXptMap.begin()); it != mXptRegNumMaskIndex2InputXptMap.end(); ++it)
2104  inOutStream << "reg " << setw(3) << it->first.first << "(" << HEX0N(it->first.first,4) << "|" << setw(20) << RegNameToString(it->first.first)
2105  << ") mask " << it->first.second << "(" << HEX0N(sMasks[it->first.second],8) << ") => "
2106  << setw(27) << ::NTV2InputCrosspointIDToString(it->second) << "(" << HEX0N(it->second,2) << ")" << endl;
2107  return inOutStream;
2108  }
2109 
2110 private:
2111  typedef std::map<uint32_t, string> RegNumToStringMap;
2112  typedef std::pair<uint32_t, string> RegNumToStringPair;
2113 
2114  static string ToLower (const string & inStr)
2115  {
2116  string result (inStr);
2117  std::transform (result.begin (), result.end (), result.begin (), ::tolower);
2118  return result;
2119  }
2120 
2121  struct DecodeGlobalControlReg : public Decoder
2122  {
2123  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2124  {
2125  (void) inRegNum;
2126  (void) inDeviceID;
2127  const NTV2FrameGeometry frameGeometry (NTV2FrameGeometry (((inRegValue & kRegMaskGeometry ) >> 3)));
2128  const NTV2Standard videoStandard (NTV2Standard ((inRegValue & kRegMaskStandard ) >> 7));
2129  const NTV2ReferenceSource referenceSource (NTV2ReferenceSource ((inRegValue & kRegMaskRefSource ) >> 10));
2130  const NTV2RegisterWriteMode registerWriteMode (NTV2RegisterWriteMode ((inRegValue & kRegMaskRegClocking ) >> 20));
2131  const NTV2FrameRate frameRate (NTV2FrameRate (((inRegValue & kRegMaskFrameRate ) >> kRegShiftFrameRate)
2132  | ((inRegValue & kRegMaskFrameRateHiBit) >> (kRegShiftFrameRateHiBit - 3))));
2133  ostringstream oss;
2134  oss << "Frame Rate: " << ::NTV2FrameRateToString (frameRate, true) << endl
2135  << "Frame Geometry: " << ::NTV2FrameGeometryToString (frameGeometry, true) << endl
2136  << "Standard: " << ::NTV2StandardToString (videoStandard, true) << endl
2137  << "Reference Source: " << ::NTV2ReferenceSourceToString (referenceSource, true) << endl
2138  << "Ch 2 link B 1080p 50/60: " << ((inRegValue & kRegMaskSmpte372Enable) ? "On" : "Off") << endl
2139  << "LEDs ";
2140  for (int led(0); led < 4; ++led)
2141  oss << (((inRegValue & kRegMaskLED) >> (16 + led)) ? "*" : ".");
2142  oss << endl
2143  << "Register Clocking: " << ::NTV2RegisterWriteModeToString (registerWriteMode, true).c_str() << endl
2144  << "Ch 1 RP-188 output: " << EnabDisab(inRegValue & kRegMaskRP188ModeCh1) << endl
2145  << "Ch 2 RP-188 output: " << EnabDisab(inRegValue & kRegMaskRP188ModeCh2) << endl
2146  << "Color Correction: " << "Channel: " << ((inRegValue & BIT(31)) ? "2" : "1")
2147  << " Bank " << ((inRegValue & BIT (30)) ? "1" : "0");
2148  return oss.str();
2149  }
2150  } mDecodeGlobalControlReg;
2151 
2152  // reg 267 aka kRegGlobalControl2
2153  struct DecodeGlobalControl2 : public Decoder
2154  {
2155  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2156  {
2157  (void) inRegNum;
2158  (void) inDeviceID;
2159  static const ULWord playCaptModes[] = { kRegMaskAud1PlayCapMode,kRegMaskAud2PlayCapMode,kRegMaskAud3PlayCapMode,kRegMaskAud4PlayCapMode,
2160  kRegMaskAud5PlayCapMode,kRegMaskAud6PlayCapMode,kRegMaskAud7PlayCapMode,kRegMaskAud8PlayCapMode};
2161  static const ULWord rp188Modes[] = { 0, 0, kRegMaskRP188ModeCh3,kRegMaskRP188ModeCh4,kRegMaskRP188ModeCh5,ULWord(kRegMaskRP188ModeCh6),kRegMaskRP188ModeCh7,kRegMaskRP188ModeCh8};
2162  static const ULWord k425Masks[] = { kRegMask425FB12, kRegMask425FB34, kRegMask425FB56, kRegMask425FB78};
2163  static const ULWord BLinkModes[] = { kRegMaskSmpte372Enable4, kRegMaskSmpte372Enable6, kRegMaskSmpte372Enable8};
2164  ostringstream oss;
2165  oss << "Reference source bit 4: " << SetNotset(inRegValue & kRegMaskRefSource2) << endl
2166  << "Quad Mode Channel 1-4: " << SetNotset(inRegValue & kRegMaskQuadMode) << endl
2167  << "Quad Mode Channel 5-8: " << SetNotset(inRegValue & kRegMaskQuadMode2) << endl
2168  << "Independent Channel Mode: " << SetNotset(inRegValue & kRegMaskIndependentMode) << endl
2169  << "2MB Frame Support: " << SuppNotsupp(inRegValue & kRegMask2MFrameSupport) << endl
2170  << "Audio Mixer: " << PresNotPres(inRegValue & kRegMaskAudioMixerPresent) << endl
2171  << "Is DNXIV Product: " << YesNo(inRegValue & kRegMaskIsDNXIV) << endl;
2172  for (unsigned ch(0); ch < 8; ch++)
2173  oss << "Audio " << DEC(ch+1) << " Play/Capture Mode: " << OnOff(inRegValue & playCaptModes[ch]) << endl;
2174  for (unsigned ch(2); ch < 8; ch++)
2175  oss << "Ch " << DEC(ch+1) << " RP188 Output: " << EnabDisab(inRegValue & rp188Modes[ch]) << endl;
2176  for (unsigned ch(0); ch < 3; ch++)
2177  oss << "Ch " << DEC(2*(ch+2)) << " 1080p50/p60 Link-B Mode: " << EnabDisab(inRegValue & BLinkModes[ch]) << endl;
2178  for (unsigned ch(0); ch < 4; ch++)
2179  oss << "Ch " << DEC(ch+1) << "/" << DEC(ch+2) << " 2SI Mode: " << EnabDisab(inRegValue & k425Masks[ch]) << endl;
2180  oss << "2SI Min Align Delay 1-4: " << EnabDisab(inRegValue & BIT(24)) << endl
2181  << "2SI Min Align Delay 5-8: " << EnabDisab(inRegValue & BIT(25));
2182  return oss.str();
2183  }
2184  } mDecodeGlobalControl2;
2185 
2186  // reg 108 aka kRegGlobalControl3
2187  struct DecodeGlobalControl3 : public Decoder
2188  {
2189  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2190  {
2191  (void) inRegNum;
2192  (void) inDeviceID;
2193  ostringstream oss;
2194  oss << "Bidirectional analog audio 1-4: " << (inRegValue & kRegMaskAnalogIOControl_14 ? "Receive" : "Transmit") << endl
2195  << "Bidirectional analog audio 5-8: " << (inRegValue & kRegMaskAnalogIOControl_58 ? "Receive" : "Transmit") << endl
2196  << "VU Meter Audio Select: " << (inRegValue & kRegMaskVUMeterSelect ? "AudMixer" : "AudSys1") << endl
2197  << "Quad Quad Mode FrameStores 1-2: " << EnabDisab(inRegValue & kRegMaskQuadQuadMode) << endl
2198  << "Quad Quad Mode FrameStores 3-4: " << EnabDisab(inRegValue & kRegMaskQuadQuadMode2) << endl
2199  << "Quad Quad Squares Mode 1-4: " << EnabDisab(inRegValue & kRegMaskQuadQuadSquaresMode) << endl
2200  << "Frame Pulse Enable: " << EnabDisab(inRegValue & kRegMaskFramePulseEnable);
2201  if (inRegValue & kRegMaskFramePulseEnable)
2202  oss << endl
2203  << "Frame Pulse Ref Src: " << DEC((inRegValue & kRegMaskFramePulseRefSelect) >> kRegShiftFramePulseRefSelect);
2204  return oss.str();
2205  }
2206  } mDecodeGlobalControl3;
2207 
2208  // Regs 377,378,379,380,381,382,383 aka kRegGlobalControlCh2,kRegGlobalControlCh3,kRegGlobalControlCh4,kRegGlobalControlCh5,kRegGlobalControlCh6,kRegGlobalControlCh7,kRegGlobalControlCh8
2209  struct DecodeGlobalControlChanReg : public Decoder
2210  {
2211  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2212  {
2213  (void) inRegNum;
2214  (void) inDeviceID;
2215  ostringstream oss;
2216  const NTV2FrameGeometry frameGeometry = NTV2FrameGeometry((inRegValue & kRegMaskGeometry) >> 3);
2217  const NTV2Standard videoStandard = NTV2Standard((inRegValue & kRegMaskStandard) >> 7);
2218  const NTV2FrameRate frameRate = NTV2FrameRate(((inRegValue & kRegMaskFrameRate) >> kRegShiftFrameRate) | ((inRegValue & kRegMaskFrameRateHiBit) >> (kRegShiftFrameRateHiBit - 3)));
2219  oss << "Frame Rate: " << ::NTV2FrameRateToString (frameRate) << endl
2220  << "Frame Geometry: " << ::NTV2FrameGeometryToString (frameGeometry) << endl
2221  << "Standard: " << ::NTV2StandardToString (videoStandard);
2222  return oss.str();
2223  }
2224  } mDecodeGlobalControlChanRegs;
2225 
2226  // Regs 1/5/257/260/384/388/392/396 aka kRegCh1Control,kRegCh2Control,kRegCh3Control,kRegCh4Control,kRegCh5Control,kRegCh6Control,kRegCh7Control,kRegCh8Control
2227  struct DecodeChannelControlReg : public Decoder
2228  {
2229  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2230  {
2231  (void) inRegNum;
2232  (void) inDeviceID;
2233  ostringstream oss;
2234  const ULWord fbfUpper ((inRegValue & kRegMaskFrameFormatHiBit) >> 2);
2235  const ULWord fbfLower ((inRegValue & kRegMaskFrameFormat) >> 1);
2236  oss << "Mode: " << (inRegValue & kRegMaskMode ? "Capture" : "Display") << endl
2237  << "Format: " << ::NTV2FrameBufferFormatToString(NTV2PixelFormat(fbfUpper | fbfLower),false) << endl
2238  << "Channel: " << DisabEnab(inRegValue & kRegMaskChannelDisable) << endl
2239  << "Viper Squeeze: " << (inRegValue & BIT(9) ? "Squeeze" : "Normal") << endl
2240  << "Flip Vertical: " << (inRegValue & kRegMaskFrameOrientation ? "Upside Down" : "Normal") << endl
2241  << "DRT Display: " << OnOff(inRegValue & kRegMaskQuarterSizeMode) << endl
2242  << "Frame Buffer Mode: " << (inRegValue & kRegMaskFrameBufferMode ? "Field" : "Frame") << endl
2243  << "Dither: " << (inRegValue & kRegMaskDitherOn8BitInput ? "Dither 8-bit inputs" : "No dithering") << endl
2244  << "Frame Size: " << (1 << (((inRegValue & kK2RegMaskFrameSize) >> 20) + 1)) << " MB" << endl;
2245  if (inRegNum == kRegCh1Control && ::NTV2DeviceSoftwareCanChangeFrameBufferSize(inDeviceID))
2246  oss << "Frame Size Override: " << EnabDisab(inRegValue & kRegMaskFrameSizeSetBySW) << endl;
2247  oss << "RGB Range: " << (inRegValue & BIT(24) ? "Black = 0x40" : "Black = 0") << endl
2248  << "VANC Data Shift: " << (inRegValue & kRegMaskVidProcVANCShift ? "Enabled" : "Normal 8 bit conversion");
2249  return oss.str();
2250  }
2251  } mDecodeChannelControl;
2252 
2253  struct DecodeFBControlReg : public Decoder
2254  {
2255  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2256  {
2257  (void) inRegNum;
2258  (void) inDeviceID;
2259  const bool isOn ((inRegValue & (1 << 29)) != 0);
2260  const uint16_t format ((inRegValue >> 15) & 0x1F);
2261  ostringstream oss;
2262  oss << OnOff(isOn) << endl
2263  << "Format: " << xHEX0N(format,4) << " (" << DEC(format) << ")";
2264  return oss.str();
2265  }
2266  } mDecodeFBControlReg;
2267 
2268  struct DecodeChannelControlExtReg : public Decoder
2269  {
2270  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2271  {
2272  (void) inRegNum;
2273  (void) inDeviceID;
2274  ostringstream oss;
2275  oss << "Input Video 2:1 Decimate: " << EnabDisab(inRegValue & BIT(0)) << endl
2276  << "HDMI Rx Direct: " << EnabDisab(inRegValue & BIT(1)) << endl
2277  << "3:2 Pulldown Mode: " << EnabDisab(inRegValue & BIT(2));
2278  return oss.str();
2279  }
2280  } mDecodeChannelControlExt;
2281 
2282  struct DecodeSysmonVccIntDieTemp : public Decoder
2283  {
2284  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2285  {
2286  (void) inRegNum;
2287  (void) inDeviceID;
2288  const UWord rawDieTemp ((inRegValue & 0x0000FFFF) >> 6);
2289  const UWord rawVoltage ((inRegValue >> 22) & 0x3FF);
2290  const double dieTempC ((double(rawDieTemp)) * 503.975 / 1024.0 - 273.15 );
2291  const double dieTempF (dieTempC * 9.0 / 5.0 + 32.0);
2292  const double voltage (double(rawVoltage)/ 1024.0 * 3.0);
2293  ostringstream oss;
2294  oss << "Die Temperature: " << fDEC(dieTempC,5,2) << " Celcius (" << fDEC(dieTempF,5,2) << " Fahrenheit)" << endl
2295  << "Core Voltage: " << fDEC(voltage,5,2) << " Volts DC";
2296  return oss.str();
2297  }
2298  } mDecodeSysmonVccIntDieTemp;
2299 
2300  struct DecodeSDITransmitCtrl : public Decoder
2301  {
2302  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2303  {
2304  (void) inRegNum;
2305  const UWord numInputs (::NTV2DeviceGetNumVideoInputs(inDeviceID));
2306  const UWord numOutputs (::NTV2DeviceGetNumVideoOutputs(inDeviceID));
2307  const UWord numSpigots (numInputs > numOutputs ? numInputs : numOutputs);
2308  ostringstream oss;
2309  if (::NTV2DeviceHasBiDirectionalSDI(inDeviceID))
2310  {
2311  const uint32_t txEnableBits (((inRegValue & 0x0F000000) >> 20) | ((inRegValue & 0xF0000000) >> 28));
2312  if (numSpigots)
2313  for (UWord spigot(0); spigot < numSpigots; )
2314  {
2315  const uint32_t txEnabled (txEnableBits & BIT(spigot));
2316  oss << "SDI " << DEC(++spigot) << ": " << (txEnabled ? "Output/Transmit" : "Input/Receive");
2317  if (spigot < numSpigots)
2318  oss << endl;
2319  }
2320  else
2321  oss << "(No SDI inputs or outputs)";
2322  }
2323  else
2324  oss << "(Bi-directional SDI not supported)";
2325  // CRC checking
2326  return oss.str();
2327  }
2328  } mDecodeSDITransmitCtrl;
2329 
2330  struct DecodeConversionCtrl : public Decoder
2331  {
2332  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2333  { (void) inRegNum;
2334  ostringstream oss;
2335  if (!::NTV2DeviceGetUFCVersion(inDeviceID))
2336  {
2337  const ULWord bitfileID((inRegValue & kK2RegMaskConverterInRate) >> kK2RegShiftConverterInRate);
2338  oss << "Bitfile ID: " << xHEX0N(bitfileID, 2) << endl
2339  << "Memory Test: Start: " << YesNo(inRegValue & BIT(28)) << endl
2340  << "Memory Test: Done: " << YesNo(inRegValue & BIT(29)) << endl
2341  << "Memory Test: Passed: " << YesNo(inRegValue & BIT(30));
2342  }
2343  else
2344  {
2345  const NTV2Standard inStd ( NTV2Standard( inRegValue & kK2RegMaskConverterInStandard ));
2346  const NTV2Standard outStd ( NTV2Standard((inRegValue & kK2RegMaskConverterOutStandard ) >> kK2RegShiftConverterOutStandard));
2347  const NTV2FrameRate inRate ( NTV2FrameRate((inRegValue & kK2RegMaskConverterInRate ) >> kK2RegShiftConverterInRate));
2348  const NTV2FrameRate outRate ( NTV2FrameRate((inRegValue & kK2RegMaskConverterOutRate ) >> kK2RegShiftConverterOutRate));
2349  const NTV2UpConvertMode upCvtMode ( NTV2UpConvertMode((inRegValue & kK2RegMaskUpConvertMode ) >> kK2RegShiftUpConvertMode));
2350  const NTV2DownConvertMode dnCvtMode (NTV2DownConvertMode((inRegValue & kK2RegMaskDownConvertMode ) >> kK2RegShiftDownConvertMode));
2351  const NTV2IsoConvertMode isoCvtMode ( NTV2IsoConvertMode((inRegValue & kK2RegMaskIsoConvertMode ) >> kK2RegShiftIsoConvertMode));
2352  oss << "Input Video Standard: " << ::NTV2StandardToString(inStd, true) << endl
2353  << "Input Video Frame Rate: " << ::NTV2FrameRateToString(inRate, true) << endl
2354  << "Output Video Standard: " << ::NTV2StandardToString(outStd, true) << endl
2355  << "Output Video Frame Rate: " << ::NTV2FrameRateToString(outRate, true) << endl
2356  << "Up Convert Mode: " << ::NTV2UpConvertModeToString(upCvtMode, true) << endl
2357  << "Down Convert Mode: " << ::NTV2DownConvertModeToString(dnCvtMode, true) << endl
2358  << "SD Anamorphic ISO Convert Mode: " << ::NTV2IsoConvertModeToString(isoCvtMode, true) << endl
2359  << "DownCvt 2-3 Pulldown: " << EnabDisab(inRegValue & kK2RegMaskConverterPulldown) << endl
2360  << "Vert Filter Preload: " << DisabEnab(inRegValue & BIT(7)) << endl
2361  << "Output Vid Std PsF (Deint Mode): " << EnabDisab(inRegValue & kK2RegMaskDeinterlaceMode) << endl
2362  << "Up Conv Line21 Pass|Blank Mode: " << DEC(ULWord(inRegValue & kK2RegMaskUCPassLine21) >> kK2RegShiftUCAutoLine21) << endl
2363  << "UFC Clock: " << EnabDisab(inRegValue & kK2RegMaskEnableConverter);
2364  }
2365  return oss.str();
2366  }
2367  } mConvControlRegDecoder;
2368 
2369  struct DecodeRelayCtrlStat : public Decoder
2370  {
2371  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2372  {
2373  (void) inRegNum;
2374  ostringstream oss;
2375  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2376  {
2377  oss << "SDI1-SDI2 Relay Control: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayControl12) << endl
2378  << "SDI3-SDI4 Relay Control: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayControl34) << endl
2379  << "SDI1-SDI2 Relay Watchdog: " << EnabDisab(inRegValue & kRegMaskSDIWatchdogEnable12) << endl
2380  << "SDI3-SDI4 Relay Watchdog: " << EnabDisab(inRegValue & kRegMaskSDIWatchdogEnable34) << endl
2381  << "SDI1-SDI2 Relay Position: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayPosition12) << endl
2382  << "SDI3-SDI4 Relay Position: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIRelayPosition34) << endl
2383  << "Watchdog Timer Status: " << ThruDeviceOrBypassed(inRegValue & kRegMaskSDIWatchdogStatus);
2384  }
2385  else
2386  oss << "(SDI bypass relays not supported)";
2387  return oss.str();
2388  }
2389  } mDecodeRelayCtrlStat;
2390 
2391  struct DecodeWatchdogTimeout : public Decoder
2392  {
2393  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2394  {
2395  (void) inRegNum;
2396  ostringstream oss;
2397  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2398  {
2399  const uint32_t ticks8nanos (inRegValue); // number of 8-nanosecond ticks
2400  const double microsecs (double(ticks8nanos) * 8.0 / 1000.0);
2401  const double millisecs (microsecs / 1000.0);
2402  oss << "Watchdog Timeout [8-ns ticks]: " << xHEX0N(ticks8nanos,8) << " (" << DEC(ticks8nanos) << ")" << endl
2403  << "Watchdog Timeout [usec]: " << microsecs << endl
2404  << "Watchdog Timeout [msec]: " << millisecs;
2405  }
2406  else
2407  oss << "(SDI bypass relays not supported)";
2408  return oss.str();
2409  }
2410  } mDecodeWatchdogTimeout;
2411 
2412  struct DecodeWatchdogKick : public Decoder
2413  {
2414  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2415  {
2416  (void) inRegNum;
2417  ostringstream oss;
2418  if (::NTV2DeviceHasSDIRelays(inDeviceID))
2419  {
2420  const uint32_t whichReg(inRegNum - kRegSDIWatchdogKick1);
2421  NTV2_ASSERT(whichReg < 2);
2422  const uint32_t expectedValue(whichReg ? 0x01234567 : 0xA5A55A5A);
2423  oss << xHEX0N(inRegValue,8);
2424  if (inRegValue == expectedValue)
2425  oss << " (Normal)";
2426  else
2427  oss << " (Not expected, should be " << xHEX0N(expectedValue,8) << ")";
2428  }
2429  else
2430  oss << "(SDI bypass relays not supported)";
2431  return oss.str();
2432  }
2433  } mDecodeWatchdogKick;
2434 
2435  struct DecodeInputVPID: public Decoder
2436  {
2437  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2438  {
2439  (void) inRegNum;
2440  (void) inDeviceID;
2441  const uint32_t regValue (NTV2EndianSwap32(inRegValue)); // Input VPID register values require endian-swap
2442  ostringstream oss;
2443  AJALabelValuePairs info;
2444  const CNTV2VPID ntv2vpid(regValue);
2445  PrintLabelValuePairs(oss, ntv2vpid.GetInfo(info));
2446  return oss.str();
2447  }
2448  } mVPIDInpRegDecoder;
2449 
2450  struct DecodeOutputVPID: public Decoder
2451  {
2452  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2453  {
2454  (void) inRegNum;
2455  (void) inDeviceID;
2456  ostringstream oss;
2457  AJALabelValuePairs info;
2458  const CNTV2VPID ntv2vpid(inRegValue);
2459  PrintLabelValuePairs(oss, ntv2vpid.GetInfo(info));
2460  return oss.str();
2461  }
2462  } mVPIDOutRegDecoder;
2463 
2464  struct DecodeBitfileDateTime : public Decoder
2465  {
2466  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2467  {
2468  (void) inDeviceID;
2469  ostringstream oss;
2470  if (inRegNum == kRegBitfileDate)
2471  {
2472  const UWord yyyy ((inRegValue & 0xFFFF0000) >> 16);
2473  const UWord mm ((inRegValue & 0x0000FF00) >> 8);
2474  const UWord dd (inRegValue & 0x000000FF);
2475  if (yyyy > 0x2015 && mm > 0 && mm < 0x13 && dd > 0 && dd < 0x32)
2476  oss << "Bitfile Date: " << HEX0N(mm,2) << "/" << HEX0N(dd,2) << "/" << HEX0N(yyyy,4);
2477  else
2478  oss << "Bitfile Date: " << xHEX0N(inRegValue, 8);
2479  }
2480  else if (inRegNum == kRegBitfileTime)
2481  {
2482  const UWord hh ((inRegValue & 0x00FF0000) >> 16);
2483  const UWord mm ((inRegValue & 0x0000FF00) >> 8);
2484  const UWord ss (inRegValue & 0x000000FF);
2485  if (hh < 0x24 && mm < 0x60 && ss < 0x60)
2486  oss << "Bitfile Time: " << HEX0N(hh,2) << ":" << HEX0N(mm,2) << ":" << HEX0N(ss,2);
2487  else
2488  oss << "Bitfile Time: " << xHEX0N(inRegValue, 8);
2489  }
2490  else NTV2_ASSERT(false); // impossible
2491  return oss.str();
2492  }
2493  } mDecodeBitfileDateTime;
2494 
2495  struct DecodeBoardID : public Decoder
2496  {
2497  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2498  { (void) inRegNum; (void) inDeviceID;
2499  const string str1 (::NTV2DeviceIDToString(NTV2DeviceID(inRegValue), false));
2500  const string str2 (::NTV2DeviceIDToString(NTV2DeviceID(inRegValue), true));
2501  ostringstream oss;
2502  oss << "NTV2DeviceID: " << ::NTV2DeviceIDString(NTV2DeviceID(inRegValue)) << endl
2503  << "Device Name: '" << str1 << "'";
2504  if (str1 != str2)
2505  oss << endl
2506  << "Retail Device Name: '" << str2 << "'";
2507  return oss.str();
2508  }
2509  } mDecodeBoardID;
2510 
2511  struct DecodeDynFWUpdateCounts : public Decoder
2512  {
2513  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2514  { (void) inRegNum; (void) inDeviceID;
2515  ostringstream oss;
2516  oss << "# attempts: " << DEC(inRegValue >> 16) << endl
2517  << "# successes: " << DEC(inRegValue & 0x0000FFFF);
2518  return oss.str();
2519  }
2520  } mDecodeDynFWUpdateCounts;
2521 
2522  struct DecodeFWUserID : public Decoder
2523  {
2524  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2525  { (void) inRegNum; (void) inDeviceID;
2526  ostringstream oss;
2527  if (inRegValue)
2528  oss << "Current Design ID: " << xHEX0N(NTV2BitfileHeaderParser::GetDesignID(inRegValue),4) << endl
2529  << "Current Design Version: " << xHEX0N(NTV2BitfileHeaderParser::GetDesignVersion(inRegValue),4) << endl
2530  << "Current Bitfile ID: " << xHEX0N(NTV2BitfileHeaderParser::GetBitfileID(inRegValue),4) << endl
2531  << "Current Bitfile Version: " << xHEX0N(NTV2BitfileHeaderParser::GetBitfileVersion(inRegValue),4);
2532  return oss.str();
2533  }
2534  } mDecodeFirmwareUserID;
2535 
2536  struct DecodeCanDoStatus : public Decoder
2537  {
2538  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2539  { (void) inRegNum; (void) inDeviceID;
2540  ostringstream oss;
2541  oss << "Has CanConnect Xpt Route ROM: " << YesNo(inRegValue & BIT(0)) << endl
2542  << "AudioSystems can start on VBI: " << YesNo(inRegValue & BIT(1));
2543  return oss.str();
2544  }
2545  } mDecodeCanDoStatus;
2546 
2547  struct DecodeVidControlReg : public Decoder // Bit31=Is16x9 | Bit30=IsMono
2548  {
2549  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2550  {
2551  (void) inRegNum;
2552  (void) inDeviceID;
2553  const bool is16x9 ((inRegValue & BIT(31)) != 0);
2554  const bool isMono ((inRegValue & BIT(30)) != 0);
2555  ostringstream oss;
2556  oss << "Aspect Ratio: " << (is16x9 ? "16x9" : "4x3") << endl
2557  << "Depth: " << (isMono ? "Monochrome" : "Color");
2558  return oss.str();
2559  }
2560  } mDecodeVidControlReg;
2561 
2562  struct DecodeVidIntControl : public Decoder
2563  {
2564  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2565  {
2566  (void) inRegNum;
2567  (void) inDeviceID;
2568  ostringstream oss;
2569  oss << "Output 1 Vertical Enable: " << YesNo(inRegValue & BIT(0)) << endl
2570  << "Input 1 Vertical Enable: " << YesNo(inRegValue & BIT(1)) << endl
2571  << "Input 2 Vertical Enable: " << YesNo(inRegValue & BIT(2)) << endl
2572  << "Audio Out Wrap Interrupt Enable: " << YesNo(inRegValue & BIT(4)) << endl
2573  << "Audio In Wrap Interrupt Enable: " << YesNo(inRegValue & BIT(5)) << endl
2574  << "Wrap Rate Interrupt Enable: " << YesNo(inRegValue & BIT(6)) << endl
2575  << "UART Tx Interrupt Enable" << YesNo(inRegValue & BIT(7)) << endl
2576  << "UART Rx Interrupt Enable" << YesNo(inRegValue & BIT(8)) << endl
2577  << "UART Rx Interrupt Clear" << ActInact(inRegValue & BIT(15)) << endl
2578  << "UART 2 Tx Interrupt Enable" << YesNo(inRegValue & BIT(17)) << endl
2579  << "Output 2 Vertical Enable: " << YesNo(inRegValue & BIT(18)) << endl
2580  << "Output 3 Vertical Enable: " << YesNo(inRegValue & BIT(19)) << endl
2581  << "Output 4 Vertical Enable: " << YesNo(inRegValue & BIT(20)) << endl
2582  << "Output 4 Vertical Clear: " << ActInact(inRegValue & BIT(21)) << endl
2583  << "Output 3 Vertical Clear: " << ActInact(inRegValue & BIT(22)) << endl
2584  << "Output 2 Vertical Clear: " << ActInact(inRegValue & BIT(23)) << endl
2585  << "UART Tx Interrupt Clear" << ActInact(inRegValue & BIT(24)) << endl
2586  << "Wrap Rate Interrupt Clear" << ActInact(inRegValue & BIT(25)) << endl
2587  << "UART 2 Tx Interrupt Clear" << ActInact(inRegValue & BIT(26)) << endl
2588  << "Audio Out Wrap Interrupt Clear" << ActInact(inRegValue & BIT(27)) << endl
2589  << "Input 2 Vertical Clear: " << ActInact(inRegValue & BIT(29)) << endl
2590  << "Input 1 Vertical Clear: " << ActInact(inRegValue & BIT(30)) << endl
2591  << "Output 1 Vertical Clear: " << ActInact(inRegValue & BIT(31));
2592  return oss.str();
2593  }
2594  } mDecodeVidIntControl;
2595 
2596  struct DecodeVidIntControl2 : public Decoder
2597  {
2598  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2599  {
2600  (void) inRegNum;
2601  (void) inDeviceID;
2602  ostringstream oss;
2603  oss << "Input 3 Vertical Enable: " << YesNo(inRegValue & BIT(1)) << endl
2604  << "Input 4 Vertical Enable: " << YesNo(inRegValue & BIT(2)) << endl
2605  << "Input 5 Vertical Enable: " << YesNo(inRegValue & BIT(8)) << endl
2606  << "Input 6 Vertical Enable: " << YesNo(inRegValue & BIT(9)) << endl
2607  << "Input 7 Vertical Enable: " << YesNo(inRegValue & BIT(10)) << endl
2608  << "Input 8 Vertical Enable: " << YesNo(inRegValue & BIT(11)) << endl
2609  << "Output 5 Vertical Enable: " << YesNo(inRegValue & BIT(12)) << endl
2610  << "Output 6 Vertical Enable: " << YesNo(inRegValue & BIT(13)) << endl
2611  << "Output 7 Vertical Enable: " << YesNo(inRegValue & BIT(14)) << endl
2612  << "Output 8 Vertical Enable: " << YesNo(inRegValue & BIT(15)) << endl
2613  << "Output 8 Vertical Clear: " << ActInact(inRegValue & BIT(16)) << endl
2614  << "Output 7 Vertical Clear: " << ActInact(inRegValue & BIT(17)) << endl
2615  << "Output 6 Vertical Clear: " << ActInact(inRegValue & BIT(18)) << endl
2616  << "Output 5 Vertical Clear: " << ActInact(inRegValue & BIT(19)) << endl
2617  << "Input 8 Vertical Clear: " << ActInact(inRegValue & BIT(25)) << endl
2618  << "Input 7 Vertical Clear: " << ActInact(inRegValue & BIT(26)) << endl
2619  << "Input 6 Vertical Clear: " << ActInact(inRegValue & BIT(27)) << endl
2620  << "Input 5 Vertical Clear: " << ActInact(inRegValue & BIT(28)) << endl
2621  << "Input 4 Vertical Clear: " << ActInact(inRegValue & BIT(29)) << endl
2622  << "Input 3 Vertical Clear: " << ActInact(inRegValue & BIT(30));
2623  return oss.str();
2624  }
2625  } mDecodeVidIntControl2;
2626 
2627  struct DecodeStatusReg : public Decoder
2628  {
2629  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2630  {
2631  (void) inRegNum;
2632  (void) inDeviceID;
2633  ostringstream oss;
2634  oss << "Input 1 Vertical Blank: " << ActInact(inRegValue & BIT(20)) << endl
2635  << "Input 1 Field ID: " << (inRegValue & BIT(21) ? "1" : "0") << endl
2636  << "Input 1 Vertical Interrupt: " << ActInact(inRegValue & BIT(30)) << endl
2637  << "Input 2 Vertical Blank: " << ActInact(inRegValue & BIT(18)) << endl
2638  << "Input 2 Field ID: " << (inRegValue & BIT(19) ? "1" : "0") << endl
2639  << "Input 2 Vertical Interrupt: " << ActInact(inRegValue & BIT(29)) << endl
2640  << "Output 1 Vertical Blank: " << ActInact(inRegValue & BIT(22)) << endl
2641  << "Output 1 Field ID: " << (inRegValue & BIT(23) ? "1" : "0") << endl
2642  << "Output 1 Vertical Interrupt: " << ActInact(inRegValue & BIT(31)) << endl
2643  << "Output 2 Vertical Blank: " << ActInact(inRegValue & BIT(4)) << endl
2644  << "Output 2 Field ID: " << (inRegValue & BIT(5) ? "1" : "0") << endl
2645  << "Output 2 Vertical Interrupt: " << ActInact(inRegValue & BIT(8)) << endl;
2646  if (::NTV2DeviceGetNumVideoOutputs(inDeviceID) > 2)
2647  oss << "Output 3 Vertical Blank: " << ActInact(inRegValue & BIT(2)) << endl
2648  << "Output 3 Field ID: " << (inRegValue & BIT(3) ? "1" : "0") << endl
2649  << "Output 3 Vertical Interrupt: " << ActInact(inRegValue & BIT(7)) << endl
2650  << "Output 4 Vertical Blank: " << ActInact(inRegValue & BIT(0)) << endl
2651  << "Output 4 Field ID: " << (inRegValue & BIT(1) ? "1" : "0") << endl
2652  << "Output 4 Vertical Interrupt: " << ActInact(inRegValue & BIT(6)) << endl;
2653  oss << "Aux Vertical Interrupt: " << ActInact(inRegValue & BIT(12)) << endl
2654  << "I2C 1 Interrupt: " << ActInact(inRegValue & BIT(14)) << endl
2655  << "I2C 2 Interrupt: " << ActInact(inRegValue & BIT(13)) << endl
2656  << "Chunk Rate Interrupt: " << ActInact(inRegValue & BIT(16)) << endl;
2657  if (::NTV2DeviceGetNumSerialPorts(inDeviceID))
2658  oss << "Generic UART Interrupt: " << ActInact(inRegValue & BIT(9)) << endl
2659  << "Uart 1 Rx Interrupt: " << ActInact(inRegValue & BIT(15)) << endl
2660  << "Uart 1 Tx Interrupt: " << ActInact(inRegValue & BIT(24)) << endl;
2661  if (::NTV2DeviceGetNumSerialPorts(inDeviceID) > 1)
2662  oss << "Uart 2 Tx Interrupt: " << ActInact(inRegValue & BIT(26)) << endl;
2663  if (::NTV2DeviceGetNumLTCInputs(inDeviceID))
2664  oss << "LTC In 1 Present: " << YesNo(inRegValue & BIT(17)) << endl;
2665  oss << "Wrap Rate Interrupt: " << ActInact(inRegValue & BIT(25)) << endl
2666  << "Audio Out Wrap Interrupt: " << ActInact(inRegValue & BIT(27)) << endl
2667  << "Audio 50Hz Interrupt: " << ActInact(inRegValue & BIT(28));
2668  return oss.str();
2669  }
2670  } mDecodeStatusReg;
2671 
2672  struct DecodeCPLDVersion : public Decoder
2673  {
2674  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2675  {
2676  (void) inRegNum;
2677  (void) inDeviceID;
2678  ostringstream oss;
2679  oss << "CPLD Version: " << DEC(inRegValue & (BIT(0)|BIT(1))) << endl
2680  << "Failsafe Bitfile Loaded: " << (inRegValue & BIT(4) ? "Yes" : "No") << endl
2681  << "Force Reload: " << YesNo(inRegValue & BIT(8));
2682  return oss.str();
2683  }
2684  } mDecodeCPLDVersion;
2685 
2686  struct DecodeStatus2Reg : public Decoder
2687  {
2688  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2689  {
2690  (void) inRegNum;
2691  (void) inDeviceID;
2692  static const uint8_t bitNumsInputVBlank[] = {20, 18, 16, 14, 12, 10}; // Input 3/4/5/6/7/8 Vertical Blank
2693  static const uint8_t bitNumsInputFieldID[] = {21, 19, 17, 15, 13, 11}; // Input 3/4/5/6/7/8 Field ID
2694  static const uint8_t bitNumsInputVertInt[] = {30, 29, 28, 27, 26, 25}; // Input 3/4/5/6/7/8 Vertical Interrupt
2695  static const uint8_t bitNumsOutputVBlank[] = { 8, 6, 4, 2}; // Output 5/6/7/8 Vertical Blank
2696  static const uint8_t bitNumsOutputFieldID[] = { 9, 7, 5, 3}; // Output 5/6/7/8 Field ID
2697  static const uint8_t bitNumsOutputVertInt[] = {31, 24, 23, 22}; // Output 5/6/7/8 Vertical Interrupt
2698  ostringstream oss;
2699  for (unsigned ndx(0); ndx < 6; ndx++)
2700  oss << "Input " << (ndx+3) << " Vertical Blank: " << ActInact(inRegValue & BIT(bitNumsInputVBlank[ndx])) << endl
2701  << "Input " << (ndx+3) << " Field ID: " << (inRegValue & BIT(bitNumsInputFieldID[ndx]) ? "1" : "0") << endl
2702  << "Input " << (ndx+3) << " Vertical Interrupt: " << ActInact(inRegValue & BIT(bitNumsInputVertInt[ndx])) << endl;
2703  for (unsigned ndx(0); ndx < 4; ndx++)
2704  oss << "Output " << (ndx+5) << " Vertical Blank: " << ActInact(inRegValue & BIT(bitNumsOutputVBlank[ndx])) << endl
2705  << "Output " << (ndx+5) << " Field ID: " << (inRegValue & BIT(bitNumsOutputFieldID[ndx]) ? "1" : "0") << endl
2706  << "Output " << (ndx+5) << " Vertical Interrupt: " << ActInact(inRegValue & BIT(bitNumsOutputVertInt[ndx])) << endl;
2707  oss << "HDMI In Hot-Plug Detect Interrupt: " << ActInact(inRegValue & BIT(0)) << endl
2708  << "HDMI In Chip Interrupt: " << ActInact(inRegValue & BIT(1));
2709  return oss.str();
2710  }
2711  } mDecodeStatus2Reg;
2712 
2713  struct DecodeInputStatusReg : public Decoder
2714  {
2715  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2716  {
2717  (void) inRegNum;
2718  (void) inDeviceID;
2719  NTV2FrameRate fRate1 (NTV2FrameRate( (inRegValue & (BIT( 0)|BIT( 1)|BIT( 2) )) | ((inRegValue & BIT(28)) >> (28-3)) ));
2720  NTV2FrameRate fRate2 (NTV2FrameRate(((inRegValue & (BIT( 8)|BIT( 9)|BIT(10) )) >> 8) | ((inRegValue & BIT(29)) >> (29-3)) ));
2721  NTV2FrameRate fRateRf (NTV2FrameRate(((inRegValue & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) >> 16) ));
2722  ostringstream oss;
2723  oss << "Input 1 Frame Rate: " << ::NTV2FrameRateToString(fRate1, true) << endl
2724  << "Input 1 Geometry: ";
2725  if (BIT(30) & inRegValue)
2726  switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2727  {
2728  case 0: oss << "2K x 1080"; break;
2729  case 1: oss << "2K x 1556"; break;
2730  default: oss << "Invalid HI"; break;
2731  }
2732  else
2733  switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2734  {
2735  case 0: oss << "Unknown"; break;
2736  case 1: oss << "525"; break;
2737  case 2: oss << "625"; break;
2738  case 3: oss << "750"; break;
2739  case 4: oss << "1125"; break;
2740  case 5: oss << "1250"; break;
2741  case 6: case 7: oss << "Reserved"; break;
2742  default: oss << "Invalid LO"; break;
2743  }
2744  oss << endl
2745  << "Input 1 Scan Mode: " << ((BIT(7) & inRegValue) ? "Progressive" : "Interlaced") << endl
2746  << "Input 2 Frame Rate: " << ::NTV2FrameRateToString(fRate2, true) << endl
2747  << "Input 2 Geometry: ";
2748  if (BIT(31) & inRegValue)
2749  switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2750  {
2751  case 0: oss << "2K x 1080"; break;
2752  case 1: oss << "2K x 1556"; break;
2753  default: oss << "Invalid HI"; break;
2754  }
2755  else
2756  switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2757  {
2758  case 0: oss << "Unknown"; break;
2759  case 1: oss << "525"; break;
2760  case 2: oss << "625"; break;
2761  case 3: oss << "750"; break;
2762  case 4: oss << "1125"; break;
2763  case 5: oss << "1250"; break;
2764  case 6: case 7: oss << "Reserved"; break;
2765  default: oss << "Invalid LO"; break;
2766  }
2767  oss << endl
2768  << "Input 2 Scan Mode: " << ((BIT(15) & inRegValue) ? "Progressive" : "Interlaced") << endl
2769  << "Reference Frame Rate: " << ::NTV2FrameRateToString(fRateRf, true) << endl
2770  << "Reference Geometry: ";
2771  switch (((BIT(20)|BIT(21)|BIT(22)) & inRegValue) >> 20) // Ref scan geometry
2772  {
2773  case 0: oss << "NTV2_SG_UNKNOWN"; break;
2774  case 1: oss << "NTV2_SG_525"; break;
2775  case 2: oss << "NTV2_SG_625"; break;
2776  case 3: oss << "NTV2_SG_750"; break;
2777  case 4: oss << "NTV2_SG_1125"; break;
2778  case 5: oss << "NTV2_SG_1250"; break;
2779  default: oss << "Invalid"; break;
2780  }
2781  oss << endl
2782  << "Reference Scan Mode: " << ((BIT(23) & inRegValue) ? "Progressive" : "Interlaced") << endl
2783  << "AES Channel 1-2: " << ((BIT(24) & inRegValue) ? "Invalid" : "Valid") << endl
2784  << "AES Channel 3-4: " << ((BIT(25) & inRegValue) ? "Invalid" : "Valid") << endl
2785  << "AES Channel 5-6: " << ((BIT(26) & inRegValue) ? "Invalid" : "Valid") << endl
2786  << "AES Channel 7-8: " << ((BIT(27) & inRegValue) ? "Invalid" : "Valid");
2787  return oss.str();
2788  }
2789  } mDecodeInputStatusReg;
2790 
2791  struct DecodeSDIInputStatusReg : public Decoder
2792  {
2793  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2794  {
2795  (void) inDeviceID;
2796  uint16_t numSpigots(0), startSpigot(0), doTsiMuxSync(0);
2797  ostringstream oss;
2798  switch (inRegNum)
2799  {
2800  case kRegSDIInput3GStatus: numSpigots = 2; startSpigot = 1; doTsiMuxSync = 1; break;
2801  case kRegSDIInput3GStatus2: numSpigots = 2; startSpigot = 3; break;
2802  case kRegSDI5678Input3GStatus: numSpigots = 4; startSpigot = 5; break;
2803  }
2804  if ((startSpigot-1) >= ::NTV2DeviceGetNumVideoInputs(inDeviceID))
2805  return oss.str(); // Skip if no such SDI inputs
2806 
2807  for (uint16_t spigotNdx(0); spigotNdx < numSpigots; )
2808  {
2809  const uint16_t spigotNum (spigotNdx + startSpigot);
2810  const uint8_t statusBits ((inRegValue >> (spigotNdx*8)) & 0xFF);
2811  const uint8_t speedBits (statusBits & 0xC1);
2812  ostringstream ossSpeed, ossSpigot;
2813  ossSpigot << "SDI In " << spigotNum << " ";
2814  const string spigotLabel (ossSpigot.str());
2815  if (speedBits & 0x01) ossSpeed << " 3G";
2816  if (::NTV2DeviceCanDo12GSDI(inDeviceID))
2817  {
2818  if (speedBits & 0x40) ossSpeed << " 6G";
2819  if (speedBits & 0x80) ossSpeed << " 12G";
2820  }
2821  if (speedBits == 0) ossSpeed << " 1.5G";
2822  oss << spigotLabel << "Link Speed:" << ossSpeed.str() << endl
2823  << spigotLabel << "SMPTE Level B: " << YesNo(statusBits & 0x02) << endl
2824  << spigotLabel << "Link A VPID Valid: " << YesNo(statusBits & 0x10) << endl
2825  << spigotLabel << "Link B VPID Valid: " << YesNo(statusBits & 0x20) << endl;
2826  if (::NTV2DeviceCanDo3GLevelConversion(inDeviceID))
2827  oss << spigotLabel << "3Gb-to-3Ga Conversion: " << EnabDisab(statusBits & 0x04);
2828  else
2829  oss << spigotLabel << "3Gb-to-3Ga Conversion: n/a";
2830  if (++spigotNdx < numSpigots)
2831  oss << endl;
2832  } // for each spigot
2833  if (doTsiMuxSync && ::NTV2DeviceCanDo425Mux(inDeviceID))
2834  for (UWord tsiMux(0); tsiMux < 4; ++tsiMux)
2835  oss << endl
2836  << "TsiMux" << DEC(tsiMux+1) << " Sync Fail: " << ((inRegValue & (0x00010000UL << tsiMux)) ? "FAILED" : "OK");
2837  return oss.str();
2838  }
2839  } mDecodeSDIInputStatusReg;
2840 
2841  struct DecodeSDIInputStatus2Reg : public Decoder
2842  {
2843  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2844  {
2845  (void) inDeviceID;
2846  const string sOdd (inRegNum == kRegInputStatus2 ? "Input 3" : (inRegNum == kRegInput56Status ? "Input 5" : "Input 7"));
2847  const string sEven (inRegNum == kRegInputStatus2 ? "Input 4" : (inRegNum == kRegInput56Status ? "Input 6" : "Input 8"));
2848  const NTV2FrameRate fRate1 (NTV2FrameRate( (inRegValue & (BIT( 0)|BIT( 1)|BIT( 2) )) | ((inRegValue & BIT(28)) >> (28-3)) ));
2849  const NTV2FrameRate fRate2 (NTV2FrameRate(((inRegValue & (BIT( 8)|BIT( 9)|BIT(10) )) >> 8) | ((inRegValue & BIT(29)) >> (29-3)) ));
2850  ostringstream oss;
2851  oss << sOdd << " Scan Mode: " << ((BIT(7) & inRegValue) ? "Progressive" : "Interlaced") << endl
2852  << sOdd << " Frame Rate: " << ::NTV2FrameRateToString(fRate1, true) << endl
2853  << sOdd << " Geometry: ";
2854  if (BIT(30) & inRegValue) switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2855  {
2856  case 0: oss << "2K x 1080"; break;
2857  case 1: oss << "2K x 1556"; break;
2858  default: oss << "Invalid HI"; break;
2859  }
2860  else switch (((BIT(4)|BIT(5)|BIT(6)) & inRegValue) >> 4)
2861  {
2862  case 0: oss << "Unknown"; break;
2863  case 1: oss << "525"; break;
2864  case 2: oss << "625"; break;
2865  case 3: oss << "750"; break;
2866  case 4: oss << "1125"; break;
2867  case 5: oss << "1250"; break;
2868  case 6: case 7: oss << "Reserved"; break;
2869  default: oss << "Invalid LO"; break;
2870  }
2871  oss << endl
2872  << sEven << " Scan Mode: " << ((BIT(15) & inRegValue) ? "Progressive" : "Interlaced") << endl
2873  << sEven << " Frame Rate: " << ::NTV2FrameRateToString(fRate2, true) << endl
2874  << sEven << " Geometry: ";
2875  if (BIT(31) & inRegValue) switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2876  {
2877  case 0: oss << "2K x 1080"; break;
2878  case 1: oss << "2K x 1556"; break;
2879  default: oss << "Invalid HI"; break;
2880  }
2881  else switch (((BIT(12)|BIT(13)|BIT(14)) & inRegValue) >> 12)
2882  {
2883  case 0: oss << "Unknown"; break;
2884  case 1: oss << "525"; break;
2885  case 2: oss << "625"; break;
2886  case 3: oss << "750"; break;
2887  case 4: oss << "1125"; break;
2888  case 5: oss << "1250"; break;
2889  case 6: case 7: oss << "Reserved"; break;
2890  default: oss << "Invalid LO"; break;
2891  }
2892  return oss.str();
2893  }
2894  } mDecodeSDIInputStatus2Reg;
2895 
2896  struct DecodeFS1RefSelectReg : public Decoder
2897  {
2898  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2899  {
2900  (void) inDeviceID; (void) inRegNum; // kRegFS1ReferenceSelect
2901  ostringstream oss;
2902  oss << "BNC Select(LHi): " << (inRegValue & 0x00000010 ? "LTCIn1" : "Ref") << endl
2903  << "Ref BNC (Corvid): " << EnabDisab(inRegValue & 0x00000020) << endl
2904  << "LTC Present (also Reg 21): " << YesNo(inRegValue & 0x00000040) << endl
2905  << "LTC Emb Out Enable: " << YesNo(inRegValue & 0x00000080) << endl
2906  << "LTC Emb In Enable: " << YesNo(inRegValue & 0x00000100) << endl
2907  << "LTC Emb In Received: " << YesNo(inRegValue & 0x00000200) << endl
2908  << "LTC BNC Out Source: " << (inRegValue & 0x00000400 ? "E-E" : "Reg112/113");
2909  return oss.str();
2910  }
2911  } mDecodeFS1RefSelectReg;
2912 
2913  struct DecodeLTCStatusControlReg : public Decoder
2914  {
2915  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2916  {
2917  (void) inDeviceID; (void) inRegNum; // kRegLTCStatusControl
2918  const uint16_t LTC1InTimingSelect ((inRegValue >> 1) & 0x0000007);
2919  const uint16_t LTC2InTimingSelect ((inRegValue >> 9) & 0x0000007);
2920  const uint16_t LTC1OutTimingSelect ((inRegValue >> 16) & 0x0000007);
2921  const uint16_t LTC2OutTimingSelect ((inRegValue >> 20) & 0x0000007);
2922  ostringstream oss;
2923  oss << "LTC 1 Input Present: " << YesNo(inRegValue & 0x00000001) << endl
2924  << "LTC 1 Input FB Timing Select): " << xHEX0N(LTC1InTimingSelect,2) << " (" << DEC(LTC1InTimingSelect) << ")" << endl
2925  << "LTC 1 Bypass: " << EnabDisab(inRegValue & 0x00000010) << endl
2926  << "LTC 1 Bypass Select: " << DEC(ULWord((inRegValue >> 5) & 0x00000001)) << endl
2927  << "LTC 2 Input Present: " << YesNo(inRegValue & 0x00000100) << endl
2928  << "LTC 2 Input FB Timing Select): " << xHEX0N(LTC2InTimingSelect,2) << " (" << DEC(LTC2InTimingSelect) << ")" << endl
2929  << "LTC 2 Bypass: " << EnabDisab(inRegValue & 0x00001000) << endl
2930  << "LTC 2 Bypass Select: " << DEC(ULWord((inRegValue >> 13) & 0x00000001)) << endl
2931  << "LTC 1 Output FB Timing Select): " << xHEX0N(LTC1OutTimingSelect,2) << " (" << DEC(LTC1OutTimingSelect) << ")" << endl
2932  << "LTC 2 Output FB Timing Select): " << xHEX0N(LTC2OutTimingSelect,2) << " (" << DEC(LTC2OutTimingSelect) << ")";
2933  return oss.str();
2934  }
2935  } mLTCStatusControlDecoder;
2936 
2937  struct DecodeAudDetectReg : public Decoder
2938  {
2939  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2940  {
2941  (void) inDeviceID;
2942  ostringstream oss;
2943  switch (inRegNum)
2944  {
2945  case kRegAud1Detect:
2946  case kRegAudDetect2:
2947  for (uint16_t num(0); num < 8; )
2948  {
2949  const uint16_t group (num / 2);
2950  const bool isChan34 (num & 1);
2951  oss << "Group " << group << " CH " << (isChan34 ? "3-4: " : "1-2: ") << (inRegValue & BIT(num) ? "Present" : "Absent");
2952  if (++num < 8)
2953  oss << endl;
2954  }
2955  break;
2956 
2957  case kRegAudioDetect5678:
2958  break;
2959  }
2960  return oss.str();
2961  }
2962  } mDecodeAudDetectReg;
2963 
2964  struct DecodeAudControlReg : public Decoder
2965  {
2966  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
2967  {
2968  (void) inRegNum;
2969  (void) inDeviceID;
2970  static const string ChStrs [] = { "Ch 1/2", "Ch 3/4", "Ch 5/6", "Ch 7/8" };
2971  uint16_t sdiOutput (0);
2972  switch (inRegNum)
2973  { case kRegAud1Control: sdiOutput = 1; break;
2974  case kRegAud3Control: sdiOutput = 3; break;
2975  case kRegAud5Control: sdiOutput = 5; break;
2976  case kRegAud7Control: sdiOutput = 7; break;
2977  default: break;
2978  }
2979 
2980  ostringstream oss;
2981  oss << "Audio Capture: " << EnabDisab(BIT(0) & inRegValue) << endl
2982  << "Audio Loopback: " << EnabDisab(BIT(3) & inRegValue) << endl
2983  << "Audio Input: " << DisabEnab(BIT(8) & inRegValue) << endl
2984  << "Audio Output: " << DisabEnab(BIT(9) & inRegValue) << endl
2985  << "Output Paused: " << YesNo(BIT(11) & inRegValue) << endl;
2986  if (sdiOutput)
2987  oss << "Audio Embedder SDIOut" << sdiOutput << ": " << DisabEnab(BIT(13) & inRegValue) << endl
2988  << "Audio Embedder SDIOut" << (sdiOutput+1) << ": " << DisabEnab(BIT(15) & inRegValue) << endl;
2989 
2990  oss << "A/V Sync Mode: " << EnabDisab(BIT(15) & inRegValue) << endl
2991  << "AES Rate Converter: " << DisabEnab(BIT(19) & inRegValue) << endl
2992  << "Audio Buffer Format: " << (BIT(20) & inRegValue ? "16-Channel " : (BIT(16) & inRegValue ? "8-Channel " : "6-Channel ")) << endl
2993  << (BIT(18) & inRegValue ? "96kHz" : "48kHz") << endl
2994  << (BIT(18) & inRegValue ? "96kHz Support" : "48kHz Support") << endl
2995  // << (BIT(22) & inRegValue ? "Embedded Support" : "No Embedded Support") << endl // JeffL says this bit is obsolete
2996  << "Slave Mode (64-chl): " << EnabDisab(BIT(23) & inRegValue) << endl // Redeployed in 16.2 for 64-ch audio
2997  << "K-box, Monitor: " << ChStrs [(BIT(24) & BIT(25) & inRegValue) >> 24] << endl
2998  << "K-Box Input: " << (BIT(26) & inRegValue ? "XLR" : "BNC") << endl
2999  << "K-Box: " << (BIT(27) & inRegValue ? "Present" : "Absent") << endl
3000  << "Cable: " << (BIT(28) & inRegValue ? "XLR" : "BNC") << endl
3001  << "Audio Buffer Size: " << (BIT(31) & inRegValue ? "4 MB" : "1 MB");
3002  return oss.str();
3003  }
3004  } mDecodeAudControlReg;
3005 
3006  struct DecodeAudSourceSelectReg : public Decoder
3007  {
3008  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3009  {
3010  (void) inRegNum;
3011  (void) inDeviceID;
3012  static const string SrcStrs [] = { "AES Input", "Embedded Groups 1 and 2", "" };
3013  static const unsigned SrcStrMap [] = { 0, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 };
3014  const uint16_t vidInput = (inRegValue & BIT(23) ? 2 : 0) + (inRegValue & BIT(16) ? 1 : 0);
3015  // WARNING! BIT(23) had better be clear on 0 & 1-input boards!!
3016  ostringstream oss;
3017  oss << "Audio Source: " << SrcStrs [SrcStrMap [(BIT(0) | BIT(1) | BIT(2) | BIT(3)) & inRegValue]] << endl
3018  << "Embedded Source Select: Video Input " << (1 + vidInput) << endl
3019  << "AES Sync Mode bit (fib): " << EnabDisab(inRegValue & BIT(18)) << endl
3020  << "PCM disabled: " << YesNo(inRegValue & BIT(17)) << endl
3021  << "Erase head enable: " << YesNo(inRegValue & BIT(19)) << endl
3022  << "Embedded Clock Select: " << (inRegValue & BIT(22) ? "Video Input" : "Board Reference") << endl
3023  << "3G audio source: " << (inRegValue & BIT(21) ? "Data stream 2" : "Data stream 1");
3024  return oss.str();
3025  }
3026  } mDecodeAudSourceSelectReg;
3027 
3028  struct DecodeAudOutputSrcMap : public Decoder
3029  {
3030  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3031  {
3032  (void) inRegNum;
3033  (void) inDeviceID;
3034  static const string AESOutputStrs[] = { "AES Outputs 1-4", "AES Outputs 5-8", "AES Outputs 9-12", "AES Outputs 13-16", ""};
3035  static const string SrcStrs[] = { "AudSys1, Audio Channels 1-4", "AudSys1, Audio Channels 5-8",
3036  "AudSys1, Audio Channels 9-12", "AudSys1, Audio Channels 13-16",
3037  "AudSys2, Audio Channels 1-4", "AudSys2, Audio Channels 5-8",
3038  "AudSys2, Audio Channels 9-12", "AudSys2, Audio Channels 13-16",
3039  "AudSys3, Audio Channels 1-4", "AudSys3, Audio Channels 5-8",
3040  "AudSys3, Audio Channels 9-12", "AudSys3, Audio Channels 13-16",
3041  "AudSys4, Audio Channels 1-4", "AudSys4, Audio Channels 5-8",
3042  "AudSys4, Audio Channels 9-12", "AudSys4, Audio Channels 13-16", ""};
3043  static const unsigned AESChlMappingShifts [4] = {0, 4, 8, 12};
3044 
3045  ostringstream oss;
3046  const uint32_t AESOutMapping (inRegValue & 0x0000FFFF);
3047  const uint32_t AnlgMonInfo ((inRegValue & kRegMaskMonitorSource) >> kRegShiftMonitorSource);
3048  const NTV2AudioSystem AnlgMonAudSys (NTV2AudioSystem(AnlgMonInfo >> 4));
3049  const NTV2AudioChannelPair AnlgMonChlPair (NTV2AudioChannelPair(AnlgMonInfo & 0xF));
3050  for (unsigned AESOutputQuad(0); AESOutputQuad < 4; AESOutputQuad++)
3051  oss << AESOutputStrs[AESOutputQuad] << " Source: " << SrcStrs[(AESOutMapping >> AESChlMappingShifts[AESOutputQuad]) & 0x0000000F] << endl;
3052  oss << "Analog Audio Monitor Output Source: " << ::NTV2AudioSystemToString(AnlgMonAudSys,true) << ", Channels " << ::NTV2AudioChannelPairToString(AnlgMonChlPair,true) << endl;
3053 
3054  // HDMI Audio Output Mapping -- interpretation depends on bit 29 of register 125 kRegHDMIOutControl MULTIREG_SPARSE_BITS
3055  const uint32_t HDMIMonInfo ((inRegValue & kRegMaskHDMIOutAudioSource) >> kRegShiftHDMIOutAudioSource);
3056  {
3057  // HDMI Audio 2-channel Mode:
3058  const NTV2AudioSystem HDMIMonAudSys (NTV2AudioSystem(HDMIMonInfo >> 4));
3059  const NTV2AudioChannelPair HDMIMonChlPair (NTV2AudioChannelPair(HDMIMonInfo & 0xF));
3060  oss << "HDMI 2-Chl Audio Output Source: " << ::NTV2AudioSystemToString(HDMIMonAudSys,true) << ", Channels " << ::NTV2AudioChannelPairToString(HDMIMonChlPair,true) << endl;
3061  }
3062  {
3063  // HDMI Audio 8-channel Mode:
3064  const uint32_t HDMIMon1234Info (HDMIMonInfo & 0x0F);
3065  const NTV2AudioSystem HDMIMon1234AudSys (NTV2AudioSystem(HDMIMon1234Info >> 2));
3066  const NTV2Audio4ChannelSelect HDMIMon1234SrcPairs (NTV2Audio4ChannelSelect(HDMIMon1234Info & 0x3));
3067  const uint32_t HDMIMon5678Info ((HDMIMonInfo >> 4) & 0x0F);
3068  const NTV2AudioSystem HDMIMon5678AudSys (NTV2AudioSystem(HDMIMon5678Info >> 2));
3069  const NTV2Audio4ChannelSelect HDMIMon5678SrcPairs (NTV2Audio4ChannelSelect(HDMIMon5678Info & 0x3));
3070  oss << "or HDMI 8-Chl Audio Output 1-4 Source: " << ::NTV2AudioSystemToString(HDMIMon1234AudSys,true) << ", Channels " << ::NTV2AudioChannelQuadToString(HDMIMon1234SrcPairs,true) << endl
3071  << "or HDMI 8-Chl Audio Output 5-8 Source: " << ::NTV2AudioSystemToString(HDMIMon5678AudSys,true) << ", Channels " << ::NTV2AudioChannelQuadToString(HDMIMon5678SrcPairs,true);
3072  }
3073  return oss.str();
3074  }
3075  } mDecodeAudOutputSrcMap;
3076 
3077  struct DecodePCMControlReg : public Decoder
3078  {
3079  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3080  {
3081  (void) inDeviceID;
3082  ostringstream oss;
3083  const UWord startAudioSystem (inRegNum == kRegPCMControl4321 ? 1 : 5);
3084  for (uint8_t audChan (0); audChan < 4; audChan++)
3085  {
3086  oss << "Audio System " << (startAudioSystem + audChan) << ": ";
3087  const uint8_t pcmBits (uint32_t(inRegValue >> (audChan * 8)) & 0x000000FF);
3088  if (pcmBits == 0x00)
3089  oss << "normal";
3090  else
3091  {
3092  oss << "non-PCM channels";
3093  for (uint8_t chanPair (0); chanPair < 8; chanPair++)
3094  if (pcmBits & (0x01 << chanPair))
3095  oss << " " << (chanPair*2+1) << "-" << (chanPair*2+2);
3096  }
3097  if (audChan < 3)
3098  oss << endl;
3099  }
3100  return oss.str();
3101  }
3102  } mDecodePCMControlReg;
3103 
3104  struct DecodeAudioMixerInputSelectReg : public Decoder
3105  { // kRegAudioMixerInputSelects
3106  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3107  { (void) inDeviceID; (void) inRegNum;
3108  const UWord mainInputSrc((inRegValue ) & 0x0000000F);
3109  const UWord aux1InputSrc((inRegValue >> 4) & 0x0000000F);
3110  const UWord aux2InputSrc((inRegValue >> 8) & 0x0000000F);
3111  ostringstream oss;
3112  oss << "Main Input Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(mainInputSrc)) << " (bits 0-3)" << endl
3113  << "Aux Input 1 Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(aux1InputSrc)) << " (bits 4-7)" << endl
3114  << "Aux Input 2 Source: " << ::NTV2AudioSystemToString(NTV2AudioSystem(aux2InputSrc)) << " (bits 8-11)";
3115  return oss.str();
3116  }
3117  } mAudMxrInputSelDecoder;
3118 
3119  struct DecodeAudioMixerGainRegs : public Decoder
3120  { // kRegAudioMixerMainGain,
3121  // kRegAudioMixerAux1GainCh1, kRegAudioMixerAux1GainCh2,
3122  // kRegAudioMixerAux2GainCh1, kRegAudioMixerAux2GainCh2
3123  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3124  { (void)inRegNum; (void)inDeviceID;
3125  static const double kUnityGain (0x00010000);
3126  const bool atUnity (inRegValue == 0x00010000);
3127  ostringstream oss;
3128  if (atUnity)
3129  oss << "Gain: 0 dB (Unity)";
3130  else
3131  {
3132  const double dValue (inRegValue);
3133  const bool aboveUnity (inRegValue >= 0x00010000);
3134  const string plusMinus (atUnity ? "" : (aboveUnity ? "+" : "-"));
3135  const string aboveBelow (atUnity ? "at" : (aboveUnity ? "above" : "below"));
3136  const uint32_t unityDiff (aboveUnity ? inRegValue - 0x00010000 : 0x00010000 - inRegValue);
3137  const double dB (double(20.0) * ::log10(dValue/kUnityGain));
3138  oss << "Gain: " << dB << " dB, " << plusMinus << xHEX0N(unityDiff,6)
3139  << " (" << plusMinus << DEC(unityDiff) << ") " << aboveBelow << " unity gain";
3140  }
3141  return oss.str();
3142  }
3143  } mAudMxrGainDecoder;
3144 
3145  struct DecodeAudioMixerChannelSelectReg : public Decoder
3146  { // kRegAudioMixerChannelSelect
3147  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3148  { (void) inRegNum; (void) inDeviceID;
3149  ostringstream oss;
3150  const uint32_t mainChanPair((inRegValue & kRegMaskAudioMixerChannelSelect ) >> kRegShiftAudioMixerChannelSelect );
3151  const uint32_t powerOfTwo ((inRegValue & kRegMaskAudioMixerLevelSampleCount) >> kRegShiftAudioMixerLevelSampleCount);
3152  oss << "Main Input Source Channel Pair: " << ::NTV2AudioChannelPairToString(NTV2AudioChannelPair(mainChanPair)) << " (bits 0-2)" << endl
3153  << "Level Measurement Sample Count: " << DEC(ULWord(1 << powerOfTwo)) << " (bits 8-15)";
3154  return oss.str();
3155  }
3156  } mAudMxrChanSelDecoder;
3157 
3158 
3159  struct DecodeAudioMixerMutesReg : public Decoder
3160  { // kRegAudioMixerMutes
3161  protected:
3162  typedef std::bitset<16> AudioChannelSet16;
3163  typedef std::bitset<2> AudioChannelSet2;
3164  static void SplitAudioChannelSet16(const AudioChannelSet16 & inChSet, NTV2StringList & outSet, NTV2StringList & outClear)
3165  {
3166  outSet.clear(); outClear.clear();
3167  for (size_t ndx(0); ndx < 16; ndx++)
3168  { ostringstream oss; oss << DEC(ndx+1);
3169  if (inChSet.test(ndx))
3170  outSet.push_back(oss.str());
3171  else
3172  outClear.push_back(oss.str());
3173  }
3174  if (outSet.empty()) outSet.push_back("<none>");
3175  if (outClear.empty()) outClear.push_back("<none>");
3176  }
3177  static void SplitAudioChannelSet2(const AudioChannelSet2 & inChSet, NTV2StringList & outSet, NTV2StringList & outClear)
3178  {
3179  outSet.clear(); outClear.clear(); static const string LR[] = {"L", "R"};
3180  for (size_t ndx(0); ndx < 2; ndx++)
3181  if (inChSet.test(ndx))
3182  outSet.push_back(LR[ndx]);
3183  else
3184  outClear.push_back(LR[ndx]);
3185  if (outSet.empty()) outSet.push_back("<none>");
3186  if (outClear.empty()) outClear.push_back("<none>");
3187  }
3188  public:
3189  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3190  { (void) inRegNum; (void) inDeviceID;
3191  uint32_t mainOutputMuteBits ((inRegValue & kRegMaskAudioMixerOutputChannelsMute) >> kRegShiftAudioMixerOutputChannelsMute); // Bits 0-15
3192  uint32_t mainInputMuteBits ((inRegValue & kRegMaskAudioMixerMainInputEnable ) >> kRegShiftAudioMixerMainInputEnable ); // Bits 16-17
3193  uint32_t aux1InputMuteBits ((inRegValue & kRegMaskAudioMixerAux1InputEnable ) >> kRegShiftAudioMixerAux1InputEnable ); // Bits 18-19
3194  uint32_t aux2InputMuteBits ((inRegValue & kRegMaskAudioMixerAux2InputEnable ) >> kRegShiftAudioMixerAux2InputEnable ); // Bits 20-21
3195  ostringstream oss;
3196  NTV2StringList mutedMainOut, unmutedMainOut, mutedMain, unmutedMain, mutedAux1, unmutedAux1, mutedAux2, unmutedAux2;
3197  SplitAudioChannelSet16(AudioChannelSet16(mainOutputMuteBits), mutedMainOut, unmutedMainOut);
3198  SplitAudioChannelSet2(AudioChannelSet2(mainInputMuteBits), mutedMain, unmutedMain);
3199  SplitAudioChannelSet2(AudioChannelSet2(aux1InputMuteBits), mutedAux1, unmutedAux1);
3200  SplitAudioChannelSet2(AudioChannelSet2(aux2InputMuteBits), mutedAux2, unmutedAux2);
3201  oss << "Main Output Muted/Disabled Channels: " << mutedMainOut << endl // bits[0:15]
3202  << "Main Output Unmuted/Enabled Channels: " << unmutedMainOut << endl;
3203  oss << "Main Input Muted/Disabled Channels: " << mutedMain << endl // bits[16:17]
3204  << "Main Input Unmuted/Enabled Channels: " << unmutedMain << endl;
3205  oss << "Aux Input 1 Muted/Disabled Channels: " << mutedAux1 << endl // bits[18:19]
3206  << "Aux Input 1 Unmuted/Enabled Channels: " << unmutedAux1 << endl;
3207  oss << "Aux Input 2 Muted/Disabled Channels: " << mutedAux2 << endl // bits[20-21]
3208  << "Aux Input 2 Unmuted/Enabled Channels: " << unmutedAux2;
3209  return oss.str();
3210  }
3211  } mAudMxrMutesDecoder;
3212 
3213  struct DecodeAudioMixerLevelsReg : public Decoder
3214  { // kRegAudioMixerAux1InputLevels, kRegAudioMixerAux2InputLevels,
3215  // kRegAudioMixerMainInputLevelsPair0 thru kRegAudioMixerMainInputLevelsPair7,
3216  // kRegAudioMixerMixedChannelOutputLevels
3217  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3218  { (void) inDeviceID;
3219  static const string sLabels[] = { "Aux Input 1", "Aux Input 2", "Main Input Audio Channels 1|2", "Main Input Audio Channels 3|4",
3220  "Main Input Audio Channels 5|6", "Main Input Audio Channels 7|8", "Main Input Audio Channels 9|10",
3221  "Main Input Audio Channels 11|12", "Main Input Audio Channels 13|14", "Main Input Audio Channels 15|16",
3222  "Main Output Audio Channels 1|2", "Main Output Audio Channels 3|4", "Main Output Audio Channels 5|6",
3223  "Main Output Audio Channels 7|8", "Main Output Audio Channels 9|10", "Main Output Audio Channels 11|12",
3224  "Main Output Audio Channels 13|14", "Main Output Audio Channels 15|16"};
3225  NTV2_ASSERT(inRegNum >= kRegAudioMixerAux1InputLevels);
3226  const uint32_t labelOffset(inRegNum - kRegAudioMixerAux1InputLevels);
3227  NTV2_ASSERT(labelOffset < 18);
3228  const string & label(sLabels[labelOffset]);
3229  const uint16_t leftLevel ((inRegValue & kRegMaskAudioMixerInputLeftLevel) >> kRegShiftAudioMixerInputLeftLevel);
3230  const uint16_t rightLevel ((inRegValue & kRegMaskAudioMixerInputRightLevel) >> kRegShiftAudioMixerInputRightLevel);
3231  ostringstream oss;
3232  oss << label << " Left Level:" << xHEX0N(leftLevel, 4) << " (" << DEC(leftLevel) << ")" << endl // bits[0:15]
3233  << label << " Right Level:" << xHEX0N(rightLevel,4) << " (" << DEC(rightLevel) << ")"; // bits[16:31]
3234  return oss.str();
3235  }
3236  } mAudMxrLevelDecoder;
3237 
3238  struct DecodeAncExtControlReg : public Decoder
3239  {
3240  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3241  {
3242  (void) inRegNum;
3243  (void) inDeviceID;
3244  ostringstream oss;
3245  static const string SyncStrs [] = { "field", "frame", "immediate", "unknown" };
3246  oss << "HANC Y enable: " << YesNo(inRegValue & BIT( 0)) << endl
3247  << "VANC Y enable: " << YesNo(inRegValue & BIT( 4)) << endl
3248  << "HANC C enable: " << YesNo(inRegValue & BIT( 8)) << endl
3249  << "VANC C enable: " << YesNo(inRegValue & BIT(12)) << endl
3250  << "Progressive video: " << YesNo(inRegValue & BIT(16)) << endl
3251  << "Synchronize: " << SyncStrs [(inRegValue & (BIT(24) | BIT(25))) >> 24] << endl
3252  << "Memory writes: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3253  << "SD Y+C Demux: " << EnabDisab(inRegValue & BIT(30)) << endl
3254  << "Metadata from: " << (inRegValue & BIT(31) ? "LSBs" : "MSBs");
3255  return oss.str();
3256  }
3257  } mDecodeAncExtControlReg;
3258 
3259  struct DecodeAuxExtControlReg : public Decoder
3260  {
3261  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3262  {
3263  (void) inRegNum;
3264  (void) inDeviceID;
3265  ostringstream oss;
3266  static const string SyncStrs [] = { "field", "frame", "immediate", "unknown" };
3267  oss << "Progressive video: " << YesNo(inRegValue & BIT(16)) << endl
3268  << "Synchronize: " << SyncStrs [(inRegValue & (BIT(24) | BIT(25))) >> 24] << endl
3269  << "Memory writes: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3270  << "Filter inclusion: " << EnabDisab(inRegValue & BIT(29));
3271  return oss.str();
3272  }
3273  } mDecodeAuxExtControlReg;
3274 
3275  // Also used for HDMI Aux regs: regAuxExtFieldVBLStartLine, regAuxExtFID
3276  struct DecodeAncExtFieldLinesReg : public Decoder
3277  {
3278  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3279  {
3280  (void) inDeviceID;
3281  ostringstream oss;
3282  const uint32_t which (inRegNum & 0x1F);
3283  const uint32_t valueLow (inRegValue & 0xFFF);
3284  const uint32_t valueHigh ((inRegValue >> 16) & 0xFFF);
3285  switch (which)
3286  {
3287  case 5: oss << "F1 cutoff line: " << valueLow << endl // regAncExtFieldCutoffLine
3288  << "F2 cutoff line: " << valueHigh;
3289  break;
3290  case 9: oss << "F1 VBL start line: " << valueLow << endl // regAncExtFieldVBLStartLine
3291  << "F2 VBL start line: " << valueHigh;
3292  break;
3293  case 11: oss << "Field ID high on line: " << valueLow << endl // regAncExtFID
3294  << "Field ID low on line: " << valueHigh;
3295  break;
3296  case 17: oss << "F1 analog start line: " << valueLow << endl // regAncExtAnalogStartLine
3297  << "F2 analog start line: " << valueHigh;
3298  break;
3299  default:
3300  oss << "Invalid register type";
3301  break;
3302  }
3303  return oss.str();
3304  }
3305  } mDecodeAncExtFieldLines;
3306 
3307  // Also used for HDMI Aux regs: regAuxExtTotalStatus, regAuxExtField1Status, regAuxExtField2Status
3308  struct DecodeAncExtStatusReg : public Decoder
3309  {
3310  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3311  {
3312  (void) inDeviceID;
3313  ostringstream oss;
3314  const uint32_t which (inRegNum & 0x1F);
3315  const uint32_t byteTotal (inRegValue & 0xFFFFFF);
3316  const bool overrun ((inRegValue & BIT(28)) ? true : false);
3317  switch (which)
3318  {
3319  case 6: oss << "Total bytes: "; break;
3320  case 7: oss << "Total F1 bytes: "; break;
3321  case 8: oss << "Total F2 bytes: "; break;
3322  default: oss << "Invalid register type"; break;
3323  }
3324  oss << DEC(byteTotal) << endl
3325  << "Overrun: " << YesNo(overrun);
3326  return oss.str();
3327  }
3328  } mDecodeAncExtStatus;
3329 
3330  // Also used for HDMI Aux Packet filtering
3331  struct DecodeAncExtIgnoreDIDReg : public Decoder
3332  {
3333  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3334  {
3335  (void) inRegNum;
3336  (void) inDeviceID;
3337  ostringstream oss;
3338  oss << "Ignoring DIDs " << HEX0N((inRegValue >> 0) & 0xFF, 2)
3339  << ", " << HEX0N((inRegValue >> 8) & 0xFF, 2)
3340  << ", " << HEX0N((inRegValue >> 16) & 0xFF, 2)
3341  << ", " << HEX0N((inRegValue >> 24) & 0xFF, 2);
3342  return oss.str();
3343  }
3344  } mDecodeAncExtIgnoreDIDs;
3345 
3346  struct DecodeAncExtAnalogFilterReg : public Decoder
3347  {
3348  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3349  {
3350  (void) inRegValue;
3351  (void) inDeviceID;
3352  ostringstream oss;
3353  uint32_t which (inRegNum & 0x1F);
3354  oss << "Each 1 bit specifies capturing ";
3355  switch (which)
3356  {
3357  case 18: oss << "F1 Y"; break;
3358  case 19: oss << "F2 Y"; break;
3359  case 20: oss << "F1 C"; break;
3360  case 21: oss << "F2 C"; break;
3361  default: return "Invalid register type";
3362  }
3363  oss << " line as analog, else digital";
3364  return oss.str();
3365  }
3366  } mDecodeAncExtAnalogFilter;
3367 
3368  struct DecodeAncInsValuePairReg : public Decoder
3369  {
3370  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3371  {
3372  (void) inDeviceID;
3373  ostringstream oss;
3374  const uint32_t which (inRegNum & 0x1F);
3375  const uint32_t valueLow (inRegValue & 0xFFFF);
3376  const uint32_t valueHigh ((inRegValue >> 16) & 0xFFFF);
3377 
3378  switch (which)
3379  {
3380  case 0: oss << "F1 byte count low: " << valueLow << endl
3381  << "F2 byte count low: " << valueHigh;
3382  break;
3383  case 4: oss << "HANC pixel delay: " << (valueLow & 0x3FF) << endl
3384  << "VANC pixel delay: " << (valueHigh & 0x7FF);
3385  break;
3386  case 5: oss << "F1 first active line: " << (valueLow & 0x7FF) << endl
3387  << "F2 first active line: " << (valueHigh & 0x7FF);
3388  break;
3389  case 6: oss << "Active line length: " << (valueLow & 0x7FF) << endl
3390  << "Total line length: " << (valueHigh & 0xFFF);
3391  break;
3392  case 8: oss << "Field ID high on line: " << (valueLow & 0x7FF) << endl
3393  << "Field ID low on line: " << (valueHigh & 0x7FF);
3394  break;
3395  case 11: oss << "F1 chroma blnk start line: " << (valueLow & 0x7FF) << endl
3396  << "F2 chroma blnk start line: " << (valueHigh & 0x7FF);
3397  break;
3398  case 14: oss << "F1 byte count high: " << valueLow << endl
3399  << "F2 byte count high: " << valueHigh;
3400  break;
3401  default: return "Invalid register type";
3402  }
3403  return oss.str();
3404  }
3405  } mDecodeAncInsValuePairReg;
3406 
3407  struct DecodeAncInsControlReg : public Decoder
3408  {
3409  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3410  {
3411  (void) inRegNum;
3412  (void) inDeviceID;
3413  ostringstream oss;
3414  oss << "HANC Y enable: " << YesNo(inRegValue & BIT( 0)) << endl
3415  << "VANC Y enable: " << YesNo(inRegValue & BIT( 4)) << endl
3416  << "HANC C enable: " << YesNo(inRegValue & BIT( 8)) << endl
3417  << "VANC C enable: " << YesNo(inRegValue & BIT(12)) << endl
3418  << "Payload Y insert: " << YesNo(inRegValue & BIT(16)) << endl
3419  << "Payload C insert: " << YesNo(inRegValue & BIT(17)) << endl
3420  << "Payload F1 insert: " << YesNo(inRegValue & BIT(20)) << endl
3421  << "Payload F2 insert: " << YesNo(inRegValue & BIT(21)) << endl
3422  << "Progressive video: " << YesNo(inRegValue & BIT(24)) << endl
3423  << "Memory reads: " << EnabDisab(!(inRegValue & BIT(28))) << endl
3424  << "SD Packet Split: " << EnabDisab(inRegValue & BIT(31));
3425  return oss.str();
3426  }
3427  } mDecodeAncInsControlReg;
3428 
3429  struct DecodeAncInsChromaBlankReg : public Decoder
3430  {
3431  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3432  {
3433  (void) inRegValue;
3434  (void) inDeviceID;
3435  ostringstream oss;
3436  uint32_t which (inRegNum & 0x1F);
3437 
3438  oss << "Each 1 bit specifies if chroma in ";
3439  switch (which)
3440  {
3441  case 12: oss << "F1"; break;
3442  case 13: oss << "F2"; break;
3443  default: return "Invalid register type";
3444  }
3445  oss << " should be blanked or passed thru";
3446  return oss.str();
3447  }
3448  } mDecodeAncInsChromaBlankReg;
3449 
3450  struct DecodeXptGroupReg : public Decoder
3451  { // Every byte in the reg value is an NTV2OutputXptID
3452  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3453  { (void) inRegNum;
3454  static unsigned sShifts[4] = {0, 8, 16, 24};
3455  NTV2StringList strs;
3456  for (unsigned ndx(0); ndx < 4; ndx++)
3457  {
3458  const NTV2InputCrosspointID inputXpt (CNTV2RegisterExpert::GetInputCrosspointID (inRegNum, ndx));
3459  const NTV2OutputCrosspointID outputXpt (NTV2OutputCrosspointID((inRegValue >> sShifts[ndx]) & 0xFF));
3460  if (NTV2_IS_VALID_InputCrosspointID(inputXpt))
3461  {
3462  if (outputXpt != NTV2_XptBlack)
3463  {
3464  NTV2WidgetID wgtID(NTV2_WIDGET_INVALID);
3465  ostringstream oss;
3466  oss << ::NTV2InputCrosspointIDToString(inputXpt, false);
3467  /* Don't bother with inputXpt check, since wgtID guaranteed valid for every inputXpt seen here:
3468  if (!CNTV2SignalRouter::GetWidgetForInput (inputXpt, wgtID, inDeviceID))
3469  oss << " (unimpl)";
3470  */
3471  oss << " <== " << ::NTV2OutputCrosspointIDToString(outputXpt, false);
3472  if (!CNTV2SignalRouter::GetWidgetForOutput (outputXpt, wgtID, inDeviceID))
3473  oss << " (unimpl)";
3474  strs.push_back(oss.str());
3475  }
3476  }
3477  }
3478  return aja::join(strs, "\n");
3479  }
3480  } mDecodeXptGroupReg;
3481 
3482  struct DecodeXptValidReg : public Decoder
3483  {
3484  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3485  {
3486  NTV2_ASSERT(inRegNum >= uint32_t(kRegFirstValidXptROMRegister));
3487  NTV2_ASSERT(inRegNum < uint32_t(kRegInvalidValidXptROMRegister));
3488  ostringstream oss;
3489  NTV2InputXptID inputXpt;
3490  NTV2OutputXptIDSet outputXpts;
3491  if (CNTV2SignalRouter::GetRouteROMInfoFromReg (inRegNum, inRegValue, inputXpt, outputXpts)
3492  && NTV2_IS_VALID_InputCrosspointID(inputXpt))
3493  {
3494  NTV2StringList outputXptNames;
3495  for (NTV2OutputXptIDSetConstIter it(outputXpts.begin()); it != outputXpts.end(); ++it)
3496  {
3497  const NTV2OutputXptID outputXpt(*it);
3498  const string name(::NTV2OutputCrosspointIDToString(outputXpt,true));
3499  ostringstream ss;
3500  if (name.empty())
3501  ss << xHEX0N(outputXpt,2) << "(" << DEC(outputXpt) << ")";
3502  else
3503  ss << "'" << name << "'";
3504  outputXptNames.push_back(ss.str());
3505  }
3506  if (!outputXptNames.empty())
3507  oss << "Valid Xpts: " << outputXptNames;
3508  return oss.str();
3509  }
3510  else
3511  return Decoder::operator()(inRegNum, inRegValue, inDeviceID);
3512  }
3513  } mDecodeXptValidReg;
3514 
3515  struct DecodeNTV4FSReg : public Decoder
3516  {
3517  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3518  { (void) inDeviceID;
3519  static const string sPixClkSelects[] = {"27", "74.1758", "74.25", "148.3516", "148.5", "inv5", "inv6", "inv7"};
3520  static const string sSyncs[] = {"Sync to Frame", "Sync to Field", "Immediate", "Sync to External"};
3521  const ULWord ntv4RegNum ((inRegNum - kNTV4FrameStoreFirstRegNum) % kNumNTV4FrameStoreRegisters);
3522  ostringstream oss;
3523  switch (NTV4FrameStoreRegs(ntv4RegNum))
3524  {
3525  case regNTV4FS_RasterControl:
3526  { const ULWord disabled (inRegValue & BIT(1));
3527  const ULWord sync ((inRegValue & (BIT(20)|BIT(21))) >> 20);
3528  const ULWord pixClkSel((inRegValue & (BIT(16)|BIT(17)|BIT(18))) >> 16);
3529  const ULWord pixFmt((inRegValue & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12))) >> 8);
3530  if (!disabled)
3531  oss << "Enabled: " << YesNo(!disabled) << endl
3532  << "Mode: " << ((inRegValue & BIT( 0)) ? "Capture" : "Display") << endl
3533  << "DRT_DISP: " << OnOff(inRegValue & BIT( 2)) << endl
3534  << "Fill Bit: " << DEC((inRegValue & BIT( 3)) ? 1 : 0) << endl
3535  << "Dither: " << EnabDisab(inRegValue & BIT( 4)) << endl
3536  << "RGB8 Convert: " << ((inRegValue & BIT( 5)) ? "Use '00'" : "Copy MSBs") << endl
3537  << "Progressive: " << YesNo(inRegValue & BIT( 6)) << endl
3538  << "Pixel Format: " << DEC(pixFmt) << " " << ::NTV2FrameBufferFormatToString(NTV2PixelFormat(pixFmt)) << endl
3539  << "Pix Clk Sel: " << sPixClkSelects[pixClkSel] << " MHz" << endl
3540  << "Sync: " << sSyncs[sync];
3541  else
3542  oss << "Enabled: " << YesNo(!disabled);
3543  break;
3544  }
3545  case regNTV4FS_Status:
3546  { const ULWord lineCnt ((inRegValue & (0xFFFF0000)) >> 16);
3547  oss << "Field ID: " << OddEven(inRegValue & BIT( 0)) << endl
3548  << "Line Count: " << DEC(lineCnt);
3549  break;
3550  }
3551  case regNTV4FS_LineLengthPitch:
3552  { const int32_t xferByteCnt((inRegValue & 0xFFFF0000) >> 16), linePitch(inRegValue & 0x0000FFFF);
3553  oss << "Line Pitch: " << linePitch << (linePitch < 0 ? " (flipped)" : "") << endl
3554  << "Xfer Byte Count: " << xferByteCnt << " [bytes/line]" << (linePitch < 0 ? " (flipped)" : "");
3555  break;
3556  }
3557  case regNTV4FS_ROIVHSize:
3558  { const ULWord ROIVSize((inRegValue & (0x0FFF0000)) >> 16), ROIHSize(inRegValue & 0x00000FFF);
3559  oss << "ROI Horz Size: " << DEC(ROIHSize) << " [pixels]" << endl
3560  << "ROI Vert Size: " << DEC(ROIVSize) << " [lines]";
3561  break;
3562  }
3563  case regNTV4FS_ROIF1VHOffsets:
3564  case regNTV4FS_ROIF2VHOffsets:
3565  { const ULWord ROIVOff((inRegValue & (0x0FFF0000)) >> 16), ROIHOff(inRegValue & 0x00000FFF);
3566  const string fld(ntv4RegNum == regNTV4FS_ROIF1VHOffsets ? "F1" : "F2");
3567  oss << "ROI " << fld << " Horz Offset: " << DEC(ROIHOff) << endl
3568  << "ROI " << fld << " Vert Offset: " << DEC(ROIVOff);
3569  break;
3570  }
3571  case regNTV4FS_DisplayHorzPixelsPerLine:
3572  { const ULWord tot((inRegValue & (0x0FFF0000)) >> 16), act(inRegValue & 0x00000FFF);
3573  oss << "Disp Horz Active: " << DEC(act) << endl
3574  << "Disp Horz Total: " << DEC(tot);
3575  break;
3576  }
3577  case regNTV4FS_DisplayFID:
3578  { const ULWord lo((inRegValue & (0x07FF0000)) >> 16), hi(inRegValue & 0x000007FF);
3579  oss << "Disp FID Lo: " << DEC(lo) << endl
3580  << "Disp FID Hi: " << DEC(hi);
3581  break;
3582  }
3583  case regNTV4FS_F1ActiveLines:
3584  case regNTV4FS_F2ActiveLines:
3585  { const ULWord actEnd((inRegValue & (0x07FF0000)) >> 16), actStart(inRegValue & 0x000007FF);
3586  const string fld(ntv4RegNum == regNTV4FS_F1ActiveLines ? "F1" : "F2");
3587  oss << "Disp " << fld << " Active Start: " << DEC(actStart) << endl
3588  << "Disp " << fld << " Active End: " << DEC(actEnd);
3589  break;
3590  }
3591  case regNTV4FS_RasterPixelSkip:
3592  oss << "Unpacker Horz Offset: " << DEC(inRegValue & 0x0000FFFF);
3593  break;
3594  case regNTV4FS_RasterVideoFill_YCb_GB:
3595  case regNTV4FS_RasterVideoFill_Cr_AR:
3596  { const ULWord hi((inRegValue & (0xFFFF0000)) >> 16), lo(inRegValue & 0x0000FFFF);
3597  const string YGorA(ntv4RegNum == regNTV4FS_RasterVideoFill_YCb_GB ? "Y|G" : "A");
3598  const string CbBorCrR(ntv4RegNum == regNTV4FS_RasterVideoFill_YCb_GB ? "Cb|B" : "Cr|R");
3599  oss << "Disp Fill " << CbBorCrR << ": " << DEC(lo) << " " << xHEX0N(lo,4) << endl
3600  << "Disp Fill " << YGorA << ": " << DEC(hi) << " " << xHEX0N(hi,4);
3601  break;
3602  }
3603  case regNTV4FS_RasterROIFillAlpha:
3604  { const ULWord lo(inRegValue & 0x0000FFFF);
3605  oss << "ROI Fill Alpha: " << DEC(lo) << " " << xHEX0N(lo,4);
3606  break;
3607  }
3608  case regNTV4FS_RasterOutputTimingPreset:
3609  oss << "Output Timing Frame Pulse Preset: " << DEC(inRegValue & 0x00FFFFFF) << " "
3610  << xHEX0N(inRegValue & 0x00FFFFFF,6);
3611  break;
3612  case regNTV4FS_RasterOffsetBlue:
3613  case regNTV4FS_RasterOffsetRed:
3614  case regNTV4FS_RasterOffsetAlpha:
3615  { const int32_t lo (inRegValue & 0x00001FFF);
3616  oss << "Output Video Offset: " << lo << " " << xHEX0N(lo,6);
3617  break;
3618  }
3619  default:
3620  return Decoder::operator()(inRegNum, inRegValue, inDeviceID);
3621  }
3622  return oss.str();
3623  }
3624  } mDecodeNTV4FSReg;
3625 
3626  struct DecodeHDMIOutputControl : public Decoder
3627  {
3628  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3629  {
3630  (void) inRegNum;
3631  ostringstream oss;
3632  static const string sHDMIStdV1[] = { "1080i", "720p", "480i", "576i", "1080p", "SXGA", "", "", "", "", "", "", "", "", "", "" };
3633  static const string sHDMIStdV2V3[] = { "1080i", "720p", "480i", "576i", "1080p", "1556i", "2Kx1080p", "2Kx1080i", "UHD", "4K", "", "", "", "", "", "" };
3634  static const string sVidRates[] = { "", "60.00", "59.94", "30.00", "29.97", "25.00", "24.00", "23.98", "50.00", "48.00", "47.95", "", "", "", "", "" };
3635  static const string sSrcSampling[] = { "YC422", "RGB", "YC420", "Unknown/invalid" };
3636  static const string sBitDepth[] = { "8", "10", "12", "Unknown/invalid" };
3637  const ULWord hdmiVers (::NTV2DeviceGetHDMIVersion(inDeviceID));
3638  const ULWord rawVideoStd (inRegValue & kRegMaskHDMIOutV2VideoStd);
3639  const string hdmiVidStdStr (hdmiVers > 1 ? sHDMIStdV2V3[rawVideoStd] : (hdmiVers == 1 ? sHDMIStdV1[rawVideoStd] : ""));
3640  const string vidStdStr (::NTV2StandardToString (NTV2Standard(rawVideoStd), true));
3641  const uint32_t srcSampling ((inRegValue & kRegMaskHDMISampling) >> kRegShiftHDMISampling);
3642  const uint32_t srcBPC ((inRegValue & (BIT(16)|BIT(17))) >> 16);
3643  const uint32_t txBitDepth ((inRegValue & (BIT(20)|BIT(21))) >> 20);
3644  oss << "Video Standard: " << hdmiVidStdStr;
3645  if (hdmiVidStdStr != vidStdStr)
3646  oss << " (" << vidStdStr << ")";
3647  oss << endl
3648  << "Color Mode: " << ((inRegValue & BIT( 8)) ? "RGB" : "YCbCr") << endl
3649  << "Video Rate: " << sVidRates[(inRegValue & kLHIRegMaskHDMIOutFPS) >> kLHIRegShiftHDMIOutFPS] << endl
3650  << "Scan Mode: " << ((inRegValue & BIT(13)) ? "Progressive" : "Interlaced") << endl
3651  << "Bit Depth: " << ((inRegValue & BIT(14)) ? "10-bit" : "8-bit") << endl
3652  << "Output Color Sampling: " << ((inRegValue & BIT(15)) ? "4:4:4" : "4:2:2") << endl
3653  << "Output Bit Depth: " << sBitDepth[txBitDepth] << endl
3654  << "Src Color Sampling: " << sSrcSampling[srcSampling] << endl
3655  << "Src Bits Per Component: " << sBitDepth[srcBPC] << endl
3656  << "Output Range: " << ((inRegValue & BIT(28)) ? "Full" : "SMPTE") << endl
3657  << "Audio Channels: " << ((inRegValue & BIT(29)) ? "8" : "2") << endl
3658  << "Output: " << ((inRegValue & BIT(30)) ? "DVI" : "HDMI");
3659  if (::NTV2DeviceGetNumHDMIVideoInputs(inDeviceID) && ::NTV2DeviceGetNumHDMIVideoOutputs(inDeviceID))
3660  oss << endl
3661  << "Audio Loopback: " << OnOff(inRegValue & BIT(31));
3662  return oss.str();
3663  }
3664  } mDecodeHDMIOutputControl;
3665 
3666  struct DecodeHDMIInputStatus : public Decoder
3667  {
3668  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3669  {
3670  (void) inRegNum;
3671  ostringstream oss;
3672  const ULWord hdmiVers(::NTV2DeviceGetHDMIVersion (inDeviceID));
3673  const uint32_t vidStd (hdmiVers >= 2 ? (inRegValue & kRegMaskHDMIInV2VideoStd) >> kRegShiftHDMIInV2VideoStd : (inRegValue & kRegMaskInputStatusStd) >> kRegShiftInputStatusStd);
3674  const uint32_t rate ((inRegValue & kRegMaskInputStatusFPS) >> kRegShiftInputStatusFPS);
3675  static const string sStds[32] = {"1080i", "720p", "480i", "576i", "1080p", "SXGA", "2K1080p", "2K1080i", "3840p", "4096p"};
3676  static const string sRates[32] = {"invalid", "60.00", "59.94", "30.00", "29.97", "25.00", "24.00", "23.98", "50.00", "48.00", "47.95" };
3677  oss << "HDMI Input: " << (inRegValue & BIT(0) ? "Locked" : "Unlocked") << endl
3678  << "HDMI Input: " << (inRegValue & BIT(1) ? "Stable" : "Unstable") << endl
3679  << "Color Mode: " << (inRegValue & BIT(2) ? "RGB" : "YCbCr") << endl
3680  << "Bitdepth: " << (inRegValue & BIT(3) ? "10-bit" : "8-bit") << endl
3681  << "Audio Channels: " << (inRegValue & BIT(12) ? 2 : 8) << endl
3682  << "Scan Mode: " << (inRegValue & BIT(13) ? "Progressive" : "Interlaced") << endl
3683  << "Standard: " << (inRegValue & BIT(14) ? "SD" : "HD") << endl
3684  << "Video Standard: " << sStds[vidStd] << endl
3685  << "Protocol: " << (inRegValue & BIT(27) ? "DVI" : "HDMI") << endl
3686  << "Video Rate : " << (rate < 11 ? sRates[rate] : string("invalid"));
3687  return oss.str();
3688  }
3689  } mDecodeHDMIInputStatus;
3690 
3691  struct DecodeHDMIInputControl : public Decoder
3692  {
3693  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3694  {
3695  (void) inRegNum; (void) inDeviceID;
3696  ostringstream oss;
3697  const UWord chanPair ((inRegValue & (BIT(2) | BIT(3))) >> 2);
3698  const UWord txSrcSel ((inRegValue & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) >> 20);
3699  const UWord txCh12Sel ((inRegValue & (BIT(29)|BIT(30))) >> 29);
3700  static const NTV2AudioChannelPair pairs[] = {NTV2_AudioChannel1_2, NTV2_AudioChannel3_4, NTV2_AudioChannel5_6, NTV2_AudioChannel7_8};
3701  oss << "HDMI In EDID Write-Enable: " << EnabDisab(inRegValue & BIT(0)) << endl
3702  << "HDMI Force Output Params: " << SetNotset(inRegValue & BIT(1)) << endl
3703  << "HDMI In Audio Chan Select: " << ::NTV2AudioChannelPairToString(pairs[chanPair], true) << endl
3704  << "hdmi_rx_8ch_src_off: " << YesNo(inRegValue & BIT(4)) << endl
3705  << "Swap HDMI In Audio Ch. 3/4: " << YesNo(inRegValue & BIT(5)) << endl
3706  << "Swap HDMI Out Audio Ch. 3/4: " << YesNo(inRegValue & BIT(6)) << endl
3707  << "HDMI Prefer 420: " << SetNotset(inRegValue & BIT(7)) << endl
3708  << "hdmi_rx_spdif_err: " << SetNotset(inRegValue & BIT(8)) << endl
3709  << "hdmi_rx_afifo_under: " << SetNotset(inRegValue & BIT(9)) << endl
3710  << "hdmi_rx_afifo_empty: " << SetNotset(inRegValue & BIT(10)) << endl
3711  << "H polarity: " << (inRegValue & BIT(16) ? "Inverted" : "Normal") << endl
3712  << "V polarity: " << (inRegValue & BIT(17) ? "Inverted" : "Normal") << endl
3713  << "F polarity: " << (inRegValue & BIT(18) ? "Inverted" : "Normal") << endl
3714  << "DE polarity: " << (inRegValue & BIT(19) ? "Inverted" : "Normal") << endl
3715  << "Tx Src Sel: " << DEC(txSrcSel) << " (" << xHEX0N(txSrcSel,4) << ")" << endl
3716  << "Tx Center Cut: " << SetNotset(inRegValue & BIT(24)) << endl
3717  << "Tx 12 bit: " << SetNotset(inRegValue & BIT(26)) << endl
3718  << "RGB Input Gamut: " << (inRegValue & BIT(28) ? "Full Range" : "Narrow Range (SMPTE)") << endl
3719  << "Tx_ch12_sel: " << DEC(txCh12Sel) << " (" << xHEX0N(txCh12Sel,4) << ")" << endl
3720  << "Input AVI Gamut: " << (inRegValue & BIT(31) ? "Full Range" : "Narrow Range (SMPTE)") << endl
3721  << "EDID: " << SetNotset(inRegValue & BIT(31));
3722  return oss.str();
3723  }
3724  } mDecodeHDMIInputControl;
3725 
3726  struct DecodeHDMIOutputStatus : public Decoder
3727  {
3728  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3729  { (void) inRegNum; (void) inDeviceID;
3730  const NTV2HDMIOutputStatus stat (inRegValue);
3731  ostringstream oss;
3732  stat.Print(oss);
3733  return oss.str();
3734  }
3735  } mDecodeHDMIOutputStatus;
3736 
3737  struct DecodeHDMIOutHDRPrimary : public Decoder
3738  {
3739  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3740  {
3741  (void) inRegNum;
3742  ostringstream oss;
3743  if (::NTV2DeviceCanDoHDMIHDROut (inDeviceID))
3744  switch (inRegNum)
3745  {
3746  case kRegHDMIHDRGreenPrimary:
3747  case kRegHDMIHDRBluePrimary:
3748  case kRegHDMIHDRRedPrimary:
3749  case kRegHDMIHDRWhitePoint:
3750  { // Asserts to validate this one code block will handle all cases:
3751  NTV2_ASSERT (kRegMaskHDMIHDRGreenPrimaryX == kRegMaskHDMIHDRBluePrimaryX && kRegMaskHDMIHDRBluePrimaryX == kRegMaskHDMIHDRRedPrimaryX);
3752  NTV2_ASSERT (kRegMaskHDMIHDRGreenPrimaryY == kRegMaskHDMIHDRBluePrimaryY && kRegMaskHDMIHDRBluePrimaryY == kRegMaskHDMIHDRRedPrimaryY);
3753  NTV2_ASSERT (kRegMaskHDMIHDRRedPrimaryX == kRegMaskHDMIHDRWhitePointX && kRegMaskHDMIHDRRedPrimaryY == kRegMaskHDMIHDRWhitePointY);
3754  NTV2_ASSERT (kRegShiftHDMIHDRGreenPrimaryX == kRegShiftHDMIHDRBluePrimaryX && kRegShiftHDMIHDRBluePrimaryX == kRegShiftHDMIHDRRedPrimaryX);
3755  NTV2_ASSERT (kRegShiftHDMIHDRGreenPrimaryY == kRegShiftHDMIHDRBluePrimaryY && kRegShiftHDMIHDRBluePrimaryY == kRegShiftHDMIHDRRedPrimaryY);
3756  NTV2_ASSERT (kRegShiftHDMIHDRRedPrimaryX == kRegShiftHDMIHDRWhitePointX && kRegShiftHDMIHDRRedPrimaryY == kRegShiftHDMIHDRWhitePointY);
3757  const uint16_t xPrimary ((inRegValue & kRegMaskHDMIHDRRedPrimaryX) >> kRegShiftHDMIHDRRedPrimaryX);
3758  const uint16_t yPrimary ((inRegValue & kRegMaskHDMIHDRRedPrimaryY) >> kRegShiftHDMIHDRRedPrimaryY);
3759  const double xFloat (double(xPrimary) * 0.00002);
3760  const double yFloat (double(yPrimary) * 0.00002);
3761  if (NTV2_IS_VALID_HDR_PRIMARY (xPrimary))
3762  oss << "X: " << fDEC(xFloat,7,5) << endl;
3763  else
3764  oss << "X: " << HEX0N(xPrimary, 4) << "(invalid)" << endl;
3765  if (NTV2_IS_VALID_HDR_PRIMARY (yPrimary))
3766  oss << "Y: " << fDEC(yFloat,7,5);
3767  else
3768  oss << "Y: " << HEX0N(yPrimary, 4) << "(invalid)";
3769  break;
3770  }
3771  case kRegHDMIHDRMasteringLuminence:
3772  {
3773  const uint16_t minValue ((inRegValue & kRegMaskHDMIHDRMinMasteringLuminance) >> kRegShiftHDMIHDRMinMasteringLuminance);
3774  const uint16_t maxValue ((inRegValue & kRegMaskHDMIHDRMaxMasteringLuminance) >> kRegShiftHDMIHDRMaxMasteringLuminance);
3775  const double minFloat (double(minValue) * 0.00001);
3776  const double maxFloat (maxValue);
3777  oss << "Min: " << fDEC(minFloat,7,5) << endl
3778  << "Max: " << fDEC(maxFloat,7,5);
3779  break;
3780  }
3781  case kRegHDMIHDRLightLevel:
3782  {
3783  const uint16_t cntValue ((inRegValue & kRegMaskHDMIHDRMaxContentLightLevel) >> kRegShiftHDMIHDRMaxContentLightLevel);
3784  const uint16_t frmValue ((inRegValue & kRegMaskHDMIHDRMaxFrameAverageLightLevel) >> kRegShiftHDMIHDRMaxFrameAverageLightLevel);
3785  const double cntFloat (cntValue);
3786  const double frmFloat (frmValue);
3787  oss << "Max Content Light Level: " << fDEC(cntFloat,7,5) << endl
3788  << "Max Frame Light Level: " << fDEC(frmFloat,7,5);
3789  break;
3790  }
3791  default: NTV2_ASSERT(false);
3792  }
3793  return oss.str();
3794  }
3795  } mDecodeHDMIOutHDRPrimary;
3796 
3797  struct DecodeHDMIOutHDRControl : public Decoder
3798  {
3799  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3800  {
3801  (void) inRegNum;
3802  static const string sEOTFs[] = {"Trad Gamma SDR", "Trad Gamma HDR", "SMPTE ST 2084", "HLG"};
3803  ostringstream oss;
3804  if (::NTV2DeviceCanDoHDMIHDROut (inDeviceID))
3805  {
3806  const uint16_t EOTFvalue ((inRegValue & kRegMaskElectroOpticalTransferFunction) >> kRegShiftElectroOpticalTransferFunction);
3807  const uint16_t staticMetaDataDescID ((inRegValue & kRegMaskHDRStaticMetadataDescriptorID) >> kRegShiftHDRStaticMetadataDescriptorID);
3808  oss << "HDMI Out Dolby Vision Enabled: " << YesNo(inRegValue & kRegMaskHDMIHDRDolbyVisionEnable) << endl
3809  << "HDMI HDR Out Enabled: " << YesNo(inRegValue & kRegMaskHDMIHDREnable) << endl
3810  << "Constant Luminance: " << YesNo(inRegValue & kRegMaskHDMIHDRNonContantLuminance) << endl
3811  << "EOTF: " << sEOTFs[(EOTFvalue < 3) ? EOTFvalue : 3] << endl
3812  << "Static MetaData Desc ID: " << HEX0N(staticMetaDataDescID, 2) << " (" << DEC(staticMetaDataDescID) << ")";
3813  }
3814  return oss.str();
3815  }
3816  } mDecodeHDMIOutHDRControl;
3817 
3818  struct DecodeHDMIOutMRControl : public Decoder
3819  {
3820  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3821  { (void) inRegNum; (void) inDeviceID;
3822  ostringstream oss;
3823  static const string sMRStandard[] = { "1080i", "720p", "480i", "576i", "1080p", "1556i", "2Kx1080p", "2Kx1080i", "UHD", "4K", "", "", "", "", "", "" };
3824  const ULWord rawVideoStd (inRegValue & kRegMaskMRStandard);
3825  const string hdmiVidStdStr (sMRStandard[rawVideoStd]);
3826  const string vidStdStr (::NTV2StandardToString (NTV2Standard(rawVideoStd), true));
3827  oss << "Video Standard: " << hdmiVidStdStr;
3828  if (hdmiVidStdStr != vidStdStr)
3829  oss << " (" << vidStdStr << ")";
3830  oss << endl
3831  << "Capture Mode: " << ((inRegValue & kRegMaskMREnable) ? "Enabled" : "Disabled");
3832  return oss.str();
3833  }
3834  } mDecodeHDMIOutMRControl;
3835 
3836  struct DecodeSDIOutputControl : public Decoder
3837  {
3838  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3839  {
3840  (void) inRegNum;
3841  (void) inDeviceID;
3842  ostringstream oss;
3843  const uint32_t vidStd (inRegValue & (BIT(0)|BIT(1)|BIT(2)));
3844  static const string sStds[32] = {"1080i", "720p", "480i", "576i", "1080p", "1556i", "6", "7"};
3845  oss << "Video Standard: " << sStds[vidStd] << endl
3846  << "2Kx1080 mode: " << (inRegValue & BIT(3) ? "2048x1080" : "1920x1080") << endl
3847  << "HBlank RGB Range: Black=" << (inRegValue & BIT(7) ? "0x40" : "0x04") << endl
3848  << "12G enable: " << YesNo(inRegValue & BIT(17)) << endl
3849  << "6G enable: " << YesNo(inRegValue & BIT(16)) << endl
3850  << "3G enable: " << YesNo(inRegValue & BIT(24)) << endl
3851  << "3G mode: " << (inRegValue & BIT(25) ? "b" : "a") << endl
3852  << "VPID insert enable: " << YesNo(inRegValue & BIT(26)) << endl
3853  << "VPID overwrite enable: " << YesNo(inRegValue & BIT(27)) << endl
3854  << "DS 1 audio source: " "AudSys";
3855  switch ((inRegValue & (BIT(28)|BIT(30))) >> 28)
3856  {
3857  case 0: oss << (inRegValue & BIT(18) ? 5 : 1); break;
3858  case 1: oss << (inRegValue & BIT(18) ? 7 : 3); break;
3859  case 4: oss << (inRegValue & BIT(18) ? 6 : 2); break;
3860  case 5: oss << (inRegValue & BIT(18) ? 8 : 4); break;
3861  }
3862  oss << endl << "DS 2 audio source: AudSys";
3863  switch ((inRegValue & (BIT(29)|BIT(31))) >> 29)
3864  {
3865  case 0: oss << (inRegValue & BIT(19) ? 5 : 1); break;
3866  case 1: oss << (inRegValue & BIT(19) ? 7 : 3); break;
3867  case 4: oss << (inRegValue & BIT(19) ? 6 : 2); break;
3868  case 5: oss << (inRegValue & BIT(19) ? 8 : 4); break;
3869  }
3870  return oss.str();
3871  }
3872  } mDecodeSDIOutputControl;
3873 
3874  struct DecodeSDIOutTimingCtrl : public Decoder
3875  {
3876  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3877  { (void)inRegNum; (void)inDeviceID;
3878  ostringstream oss;
3879  const uint32_t hMask(0x00001FFF), vMask(0x1FFF0000);
3880  const uint32_t hOffset(inRegValue & hMask), vOffset((inRegValue & vMask) >> 16);
3881  oss << "Horz Offset: " << xHEX0N(UWord(hOffset),4) << endl
3882  << "Vert Offset: " << xHEX0N(UWord(vOffset),4) << endl
3883  << "E-E Timing Override: " << EnabDisab(inRegValue & BIT(31));
3884  return oss.str();
3885  }
3886  } mDecodeSDIOutTimingCtrl;
3887 
3888  struct DecodeDMAControl : public Decoder
3889  {
3890  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3891  {
3892  (void) inRegNum;
3893  (void) inDeviceID;
3894  const uint16_t gen ((inRegValue & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) >> 20);
3895  const uint16_t lanes ((inRegValue & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) >> 16);
3896  const uint16_t fwRev ((inRegValue & 0x0000FF00) >> 8);
3897  ostringstream oss;
3898  for (uint16_t engine(0); engine < 4; engine++)
3899  oss << "DMA " << (engine+1) << " Int Active?: " << YesNo(inRegValue & BIT(27+engine)) << endl;
3900  oss << "Bus Error Int Active?: " << YesNo(inRegValue & BIT(31)) << endl;
3901  for (uint16_t engine(0); engine < 4; engine++)
3902  oss << "DMA " << (engine+1) << " Busy?: " << YesNo(inRegValue & BIT(27+engine)) << endl;
3903  oss << "Strap: " << ((inRegValue & BIT(7)) ? "Installed" : "Not Installed") << endl
3904  << "Firmware Rev: " << xHEX0N(fwRev, 2) << " (" << DEC(fwRev) << ")" << endl
3905  << "Gen: " << gen << ((gen > 0 && gen < 4) ? "" : " <invalid>") << endl
3906  << "Lanes: " << DEC(lanes) << ((lanes < 9) ? "" : " <invalid>");
3907  return oss.str();
3908  }
3909  } mDMAControlRegDecoder;
3910 
3911  struct DecodeDMAIntControl : public Decoder
3912  {
3913  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3914  {
3915  (void) inRegNum;
3916  (void) inDeviceID;
3917  ostringstream oss;
3918  for (uint16_t eng(0); eng < 4; eng++)
3919  oss << "DMA " << (eng+1) << " Enabled?: " << YesNo(inRegValue & BIT(eng)) << endl;
3920  oss << "Bus Error Enabled?: " << YesNo(inRegValue & BIT(4)) << endl;
3921  for (uint16_t eng(0); eng < 4; eng++)
3922  oss << "DMA " << (eng+1) << " Active?: " << YesNo(inRegValue & BIT(27+eng)) << endl;
3923  oss << "Bus Error: " << YesNo(inRegValue & BIT(31));
3924  return oss.str();
3925  }
3926  } mDMAIntControlRegDecoder;
3927 
3928  struct DecodeDMAXferRate : public Decoder
3929  {
3930  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3931  { (void) inRegNum; (void) inDeviceID;
3932  ostringstream oss;
3933  oss << DEC(inRegValue) << " [MB/sec] [kB/ms] [B/us]";
3934  return oss.str();
3935  }
3936  } mDMAXferRateRegDecoder;
3937 
3938  struct DecodeRP188InOutDBB : public Decoder
3939  {
3940  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3941  {
3942  (void) inRegNum;
3943  (void) inDeviceID;
3944  const bool isReceivingRP188 (inRegValue & BIT(16));
3945  const bool isReceivingSelectedRP188 (inRegValue & BIT(17));
3946  const bool isReceivingLTC (inRegValue & BIT(18));
3947  const bool isReceivingVITC (inRegValue & BIT(19));
3948  ostringstream oss;
3949  oss << "RP188: " << (isReceivingRP188 ? (isReceivingSelectedRP188 ? "Selected" : "Unselected") : "No") << " RP-188 received"
3950  << (isReceivingLTC ? " +LTC" : "") << (isReceivingVITC ? " +VITC" : "") << endl
3951  << "Bypass: " << (inRegValue & BIT(23) ? (inRegValue & BIT(22) ? "SDI In 2" : "SDI In 1") : "Disabled") << endl
3952  << "Filter: " << HEX0N((inRegValue & 0xFF000000) >> 24, 2) << endl
3953  << "DBB: " << HEX0N((inRegValue & 0x0000FF00) >> 8, 2) << " " << HEX0N(inRegValue & 0x000000FF, 2);
3954  return oss.str();
3955  }
3956  } mRP188InOutDBBRegDecoder;
3957 
3958  struct DecodeVidProcControl : public Decoder
3959  {
3960  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3961  {
3962  (void) inRegNum;
3963  (void) inDeviceID;
3964  ostringstream oss;
3965  static const string sSplitStds [8] = {"1080i", "720p", "480i", "576i", "1080p", "1556i", "?6?", "?7?"};
3966  oss << "Mode: " << (inRegValue & kRegMaskVidProcMode ? ((inRegValue & BIT(24)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
3967  << "FG Control: " << (inRegValue & kRegMaskVidProcFGControl ? ((inRegValue & BIT(20)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
3968  << "BG Control: " << (inRegValue & kRegMaskVidProcBGControl ? ((inRegValue & BIT(22)) ? "Shaped" : "Unshaped") : "Full Raster") << endl
3969  << "VANC Pass-Thru: " << ((inRegValue & BIT(13)) ? "Background" : "Foreground") << endl
3970  << "FG Matte: " << EnabDisab(inRegValue & kRegMaskVidProcFGMatteEnable) << endl
3971  << "BG Matte: " << EnabDisab(inRegValue & kRegMaskVidProcBGMatteEnable) << endl
3972  << "Input Sync: " << (inRegValue & kRegMaskVidProcSyncFail ? "not in sync" : "in sync") << endl
3973  << "Limiting: " << ((inRegValue & BIT(11)) ? "Off" : ((inRegValue & BIT(12)) ? "Legal Broadcast" : "Legal SDI")) << endl
3974  << "Split Video Std: " << sSplitStds[inRegValue & kRegMaskVidProcSplitStd];
3975  return oss.str();
3976  }
3977  } mVidProcControlRegDecoder;
3978 
3979  struct DecodeSplitControl : public Decoder
3980  {
3981  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
3982  {
3983  (void) inRegNum;
3984  (void) inDeviceID;
3985  ostringstream oss;
3986  const uint32_t startmask (0x0000FFFF); // 16 bits
3987  const uint32_t slopemask (0x3FFF0000); // 14 bits / high order byte
3988  const uint32_t fractionmask(0x00000007); // 3 bits for fractions
3989  oss << "Split Start: " << HEX0N((inRegValue & startmask) & ~fractionmask, 4) << " "
3990  << HEX0N((inRegValue & startmask) & fractionmask, 4) << endl
3991  << "Split Slope: " << HEX0N(((inRegValue & slopemask) >> 16) & ~fractionmask, 4) << " "
3992  << HEX0N(((inRegValue & slopemask) >> 16) & fractionmask, 4) << endl
3993  << "Split Type: " << ((inRegValue & BIT(30)) ? "Vertical" : "Horizontal");
3994  return oss.str();
3995  }
3996  } mSplitControlRegDecoder;
3997 
3998  struct DecodeFlatMatteValue : public Decoder
3999  {
4000  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4001  {
4002  (void) inRegNum;
4003  (void) inDeviceID;
4004  ostringstream oss;
4005  const uint32_t mask (0x000003FF); // 10 bits
4006  oss << "Flat Matte Cb: " << HEX0N(inRegValue & mask, 3) << endl
4007  << "Flat Matte Y: " << HEX0N(((inRegValue >> 10) & mask) - 0x40, 3) << endl
4008  << "Flat Matte Cr: " << HEX0N((inRegValue >> 20) & mask, 3);
4009  return oss.str();
4010  }
4011  } mFlatMatteValueRegDecoder;
4012 
4013  struct DecodeEnhancedCSCMode : public Decoder
4014  {
4015  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4016  {
4017  (void) inRegNum;
4018  (void) inDeviceID;
4019  static const string sFiltSel[] = {"Full", "Simple", "None", "?"};
4020  static const string sEdgeCtrl[] = {"black", "extended pixels"};
4021  static const string sPixFmts[] = {"RGB 4:4:4", "YCbCr 4:4:4", "YCbCr 4:2:2", "?"};
4022  const uint32_t filterSelect ((inRegValue >> 12) & 0x3);
4023  const uint32_t edgeControl ((inRegValue >> 8) & 0x1);
4024  const uint32_t outPixFmt ((inRegValue >> 4) & 0x3);
4025  const uint32_t inpPixFmt (inRegValue & 0x3);
4026  ostringstream oss;
4027  oss << "Filter select: " << sFiltSel[filterSelect] << endl
4028  << "Filter edge control: " << "Filter to " << sEdgeCtrl[edgeControl] << endl
4029  << "Output pixel format: " << sPixFmts[outPixFmt] << endl
4030  << "Input pixel format: " << sPixFmts[inpPixFmt];
4031  return oss.str();
4032  }
4033  } mEnhCSCModeDecoder;
4034 
4035  struct DecodeEnhancedCSCOffset : public Decoder
4036  {
4037  static string U10Dot6ToFloat (const uint32_t inOffset)
4038  {
4039  double result (double((inOffset >> 6) & 0x3FF));
4040  result += double(inOffset & 0x3F) / 64.0;
4041  ostringstream oss; oss << fDEC(result,12,5); string resultStr(oss.str());
4042  return aja::replace (resultStr, sSpace, sNull);
4043  }
4044  static string U12Dot4ToFloat (const uint32_t inOffset)
4045  {
4046  double result (double((inOffset >> 4) & 0xFFF));
4047  result += double(inOffset & 0xF) / 16.0;
4048  ostringstream oss; oss << fDEC(result,12,4); string resultStr(oss.str());
4049  return aja::replace (resultStr, sSpace, sNull);
4050  }
4051  static string S13Dot2ToFloat (const uint32_t inOffset)
4052  {
4053  double result (double((inOffset >> 2) & 0x1FFF));
4054  result += double(inOffset & 0x3) / 4.0;
4055  if (inOffset & BIT(15))
4056  result = -result;
4057  ostringstream oss; oss << fDEC(result,12,2); string resultStr(oss.str());
4058  return aja::replace (resultStr, sSpace, sNull);
4059  }
4060  static string S11Dot4ToFloat (const uint32_t inOffset)
4061  {
4062  double result (double((inOffset >> 4) & 0x7FF));
4063  result += double(inOffset & 0xF) / 16.0;
4064  if (inOffset & BIT(15))
4065  result = -result;
4066  ostringstream oss; oss << fDEC(result,12,4); string resultStr(oss.str());
4067  return aja::replace (resultStr, sSpace, sNull);
4068  }
4069  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4070  {
4071  (void) inDeviceID;
4072  const uint32_t regNum (inRegNum & 0x1F);
4073  const uint32_t lo (inRegValue & 0x0000FFFF);
4074  const uint32_t hi ((inRegValue >> 16) & 0xFFFF);
4075  ostringstream oss;
4076  switch (regNum)
4077  {
4078  case 1: oss << "Component 0 input offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)" << endl
4079  << "Component 1 input offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4080  break;
4081  case 2: oss << "Component 2 input offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)";
4082  break;
4083  case 12: oss << "Component A output offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)" << endl
4084  << "Component B output offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4085  break;
4086  case 13: oss << "Component C output offset: " << U12Dot4ToFloat(lo) << " (12-bit), " << U10Dot6ToFloat(lo) << " (10-bit)";
4087  break;
4088  case 15: oss << "Key input offset: " << S13Dot2ToFloat(lo) << " (12-bit), " << S11Dot4ToFloat(lo) << " (10-bit)" << endl
4089  << "Key output offset: " << U12Dot4ToFloat(hi) << " (12-bit), " << U10Dot6ToFloat(hi) << " (10-bit)";
4090  break;
4091  default: break;
4092  }
4093  return oss.str();
4094  }
4095  } mEnhCSCOffsetDecoder;
4096 
4097  struct DecodeEnhancedCSCKeyMode : public Decoder
4098  {
4099  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4100  {
4101  (void) inRegNum;
4102  (void) inDeviceID;
4103  static const string sSrcSel[] = {"Key Input", "Video Y Input"};
4104  static const string sRange[] = {"Full Range", "SMPTE Range"};
4105  const uint32_t keySrcSelect (inRegValue & 0x1);
4106  const uint32_t keyOutRange ((inRegValue >> 4) & 0x1);
4107  ostringstream oss;
4108  oss << "Key Source Select: " << sSrcSel[keySrcSelect] << endl
4109  << "Key Output Range: " << sRange[keyOutRange];
4110  return oss.str();
4111  }
4112  } mEnhCSCKeyModeDecoder;
4113 
4114  struct DecodeEnhancedCSCCoefficient : public Decoder
4115  {
4116  static string S2Dot15ToFloat (const uint32_t inCoefficient)
4117  {
4118  double result = (double((inCoefficient >> 15) & 0x3));
4119  result += double(inCoefficient & 0x7FFF) / 32768.0;
4120  if (inCoefficient & BIT(17))
4121  result = -result;
4122  ostringstream oss; oss << fDEC(result,12,10); string resultStr(oss.str());
4123  return aja::replace(resultStr, sSpace, sNull);
4124  }
4125  static string S12Dot12ToFloat (const uint32_t inCoefficient)
4126  {
4127  double result(double((inCoefficient >> 12) & 0xFFF));
4128  result += double(inCoefficient & 0xFFF) / 4096.0;
4129  if (inCoefficient & BIT(24))
4130  result = -result;
4131  ostringstream oss; oss << fDEC(result,12,6); string resultStr(oss.str());
4132  return aja::replace(resultStr, sSpace, sNull);
4133  }
4134  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4135  {
4136  (void) inDeviceID;
4137  uint32_t regNum (inRegNum & 0x1F);
4138  ostringstream oss;
4139  if (regNum > 2 && regNum < 12)
4140  {
4141  regNum -= 3;
4142  static const string sCoeffNames[] = {"A0", "A1", "A2", "B0", "B1", "B2", "C0", "C1", "C2"};
4143  const uint32_t coeff ((inRegValue >> 9) & 0x0003FFFF);
4144  oss << sCoeffNames[regNum] << " coefficient: " << S2Dot15ToFloat(coeff) << " (" << xHEX0N(coeff,8) << ")";
4145  }
4146  else if (regNum == 16)
4147  {
4148  const uint32_t gain ((inRegValue >> 4) & 0x01FFFFFF);
4149  oss << "Key gain: " << S12Dot12ToFloat(gain) << " (" << HEX0N(gain,8) << ")";
4150  }
4151  return oss.str();
4152  }
4153  } mEnhCSCCoeffDecoder;
4154 
4155  struct DecodeCSCoeff1234 : public Decoder
4156  {
4157  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4158  {
4159  (void) inDeviceID;
4160  const uint32_t coeff1 (((inRegValue >> 11) & 0x00000003) | uint32_t(inRegValue & 0x000007FF));
4161  const uint32_t coeff2 ((inRegValue >> 14) & 0x00001FFF);
4162  uint16_t nCoeff1(1), nCoeff2(2);
4163  switch(inRegNum)
4164  {
4165  case kRegCSCoefficients3_4: case kRegCS2Coefficients3_4: case kRegCS3Coefficients3_4: case kRegCS4Coefficients3_4:
4166  case kRegCS5Coefficients3_4: case kRegCS6Coefficients3_4: case kRegCS7Coefficients3_4: case kRegCS8Coefficients3_4:
4167  nCoeff1 = 3; nCoeff2 = 4; break;
4168  }
4169  // kRegCS?Coefficients1_2 kRegCS?Coefficients3_4
4170  // CSC 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
4171  // RegNum 142 147 291 296 347 460 465 470 143 148 292 297 348 461 466 471
4172  // kRegCS?Coefficients1_2: kK2RegMaskVidKeySyncStatus = BIT(28) 0=OK 1=SyncFail GetColorSpaceVideoKeySyncFail
4173  // kRegCS?Coefficients1_2: kK2RegMaskMakeAlphaFromKeySelect = BIT(29) 0=No 1=Yes GetColorSpaceMakeAlphaFromKey
4174  // kRegCS?Coefficients1_2: kK2RegMaskColorSpaceMatrixSelect = BIT(30) 0=Rec709 1=Rec601 GetColorSpaceMatrixSelect
4175  // kRegCS?Coefficients1_2: kK2RegMaskUseCustomCoefSelect = BIT(31) 0=No 1=Yes GetColorSpaceUseCustomCoefficient
4176  // kRegCS?Coefficients3_4: kK2RegMaskXena2RGBRange = BIT(31) 0=Full 1=SMPTE GetColorSpaceRGBBlackRange
4177  // kK2RegMaskCustomCoefficientLow = BITS(0-10) CSCCustomCoeffs.Coefficient1 GetColorSpaceCustomCoefficients
4178  // kK2RegMaskCustomCoefficientHigh = BITS(16-26) CSCCustomCoeffs.Coefficient2 GetColorSpaceCustomCoefficients
4179  // kK2RegMaskCustomCoefficient12BitLow = BITS(0-12) CSCCustomCoeffs.Coefficient1 GetColorSpaceCustomCoefficients12Bit
4180  // kK2RegMaskCustomCoefficient12BitHigh= BITS(14-26) CSCCustomCoeffs.Coefficient2 GetColorSpaceCustomCoefficients12Bit
4181  ostringstream oss;
4182  if (nCoeff1 == 1)
4183  oss << "Video Key Sync Status: " << (inRegValue & BIT(28) ? "SyncFail" : "OK") << endl
4184  << "Make Alpha From Key Input: " << EnabDisab(inRegValue & BIT(29)) << endl
4185  << "Matrix Select: " << (inRegValue & BIT(30) ? "Rec601" : "Rec709") << endl
4186  << "Use Custom Coeffs: " << YesNo(inRegValue & BIT(31)) << endl;
4187  else
4188  oss << "RGB Range: " << (inRegValue & BIT(31) ? "SMPTE (0x040-0x3C0)" : "Full (0x000-0x3FF)") << endl;
4189  oss << "Coefficient" << DEC(nCoeff1) << ": " << xHEX0N(coeff1, 4) << endl
4190  << "Coefficient" << DEC(nCoeff2) << ": " << xHEX0N(coeff2, 4);
4191  return oss.str();
4192  }
4193  } mCSCoeff1234Decoder;
4194 
4195  struct DecodeCSCoeff567890 : public Decoder
4196  {
4197  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4198  {
4199  (void) inDeviceID;
4200  const uint32_t coeff5 (((inRegValue >> 11) & 0x00000003) | uint32_t(inRegValue & 0x000007FF));
4201  const uint32_t coeff6 ((inRegValue >> 14) & 0x00001FFF);
4202  uint16_t nCoeff5(5), nCoeff6(6);
4203  switch(inRegNum)
4204  {
4205  case kRegCSCoefficients7_8: case kRegCS2Coefficients7_8: case kRegCS3Coefficients7_8: case kRegCS4Coefficients7_8:
4206  case kRegCS5Coefficients7_8: case kRegCS6Coefficients7_8: case kRegCS7Coefficients7_8: case kRegCS8Coefficients7_8:
4207  nCoeff5 = 7; nCoeff6 = 8; break;
4208  case kRegCSCoefficients9_10: case kRegCS2Coefficients9_10: case kRegCS3Coefficients9_10: case kRegCS4Coefficients9_10:
4209  case kRegCS5Coefficients9_10: case kRegCS6Coefficients9_10: case kRegCS7Coefficients9_10: case kRegCS8Coefficients9_10:
4210  nCoeff5 = 9; nCoeff6 = 10; break;
4211  }
4212  // kRegCS?Coefficients5_6 kRegCS?Coefficients7_8 kRegCS?Coefficients9_10
4213  // CSC 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
4214  // RegNum 143 148 292 297 348 461 466 471 144 149 293 298 349 462 467 472 145 150 294 299 350 463 468 473
4215  // kK2RegMaskCustomCoefficientLow = BITS(0-10) CSCCustomCoeffs.Coefficient5 GetColorSpaceCustomCoefficients
4216  // kK2RegMaskCustomCoefficientHigh = BITS(16-26) CSCCustomCoeffs.Coefficient6 GetColorSpaceCustomCoefficients
4217  // kK2RegMaskCustomCoefficient12BitLow = BITS(0-12) CSCCustomCoeffs.Coefficient5 GetColorSpaceCustomCoefficients12Bit
4218  // kK2RegMaskCustomCoefficient12BitHigh= BITS(14-26) CSCCustomCoeffs.Coefficient6 GetColorSpaceCustomCoefficients12Bit
4219  ostringstream oss;
4220  oss << "Coefficient" << DEC(nCoeff5) << ": " << xHEX0N(coeff5, 4) << endl
4221  << "Coefficient" << DEC(nCoeff6) << ": " << xHEX0N(coeff6, 4);
4222  return oss.str();
4223  }
4224  } mCSCoeff567890Decoder;
4225 
4226  struct DecodeLUTV1ControlReg : public Decoder // kRegCh1ColorCorrectionControl (68), kRegCh2ColorCorrectionControl (69)
4227  {
4228  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4229  { static const string sModes[] = {"Off", "RGB", "YCbCr", "3-Way", "Invalid"};
4230  const ULWord lutVersion (::NTV2DeviceGetLUTVersion(inDeviceID));
4231  const UWord saturation (UWord(inRegValue & kRegMaskSaturationValue));
4232  const UWord mode (UWord((inRegValue & kRegMaskCCMode) >> kRegShiftCCMode));
4233  const bool outBankSelect (((inRegValue & kRegMaskCCOutputBankSelect) >> kRegShiftCCOutputBankSelect) ? true : false);
4234  const bool cc5HostBank (((inRegValue & kRegMaskCC5HostAccessBankSelect) >> kRegShiftCC5HostAccessBankSelect) ? true : false);
4235  const bool cc5OutputBank (((inRegValue & kRegMaskCC5OutputBankSelect) >> kRegShiftCC5OutputBankSelect) ? true : false);
4236  const bool cc5Select (((inRegValue & kRegMaskLUT5Select) >> kRegShiftLUT5Select) ? true : false);
4237  const bool ccConfig2 (((inRegValue & kRegMaskLUTSelect) >> kRegShiftLUTSelect) ? true : false);
4238  const bool cc3BankSel (((inRegValue & kRegMaskCC3OutputBankSelect) >> kRegShiftCC3OutputBankSelect) ? true : false);
4239  const bool cc4BankSel (((inRegValue & kRegMaskCC4OutputBankSelect) >> kRegShiftCC4OutputBankSelect) ? true : false);
4240  NTV2_ASSERT(mode < 4);
4241  ostringstream oss;
4242  if (lutVersion != 1)
4243  oss << "(Register data relevant for V1 LUT, this device has V" << DEC(lutVersion) << " LUT)";
4244  else
4245  {
4246  oss << "LUT Saturation Value: " << xHEX0N(saturation,4) << " (" << DEC(saturation) << ")" << endl
4247  << "LUT Output Bank Select: " << SetNotset(outBankSelect) << endl
4248  << "LUT Mode: " << sModes[mode] << " (" << DEC(mode) << ")";
4249  if (inRegNum == kRegCh1ColorCorrectionControl)
4250  oss << endl
4251  << "LUT5 Host Bank Select: " << SetNotset(cc5HostBank) << endl
4252  << "LUT5 Output Bank Select: " << SetNotset(cc5OutputBank) << endl
4253  << "LUT5 Select: " << SetNotset(cc5Select) << endl
4254  << "Config 2nd LUT Set: " << YesNo(ccConfig2);
4255  }
4256  oss << endl
4257  << "LUT3 Bank Select: " << SetNotset(cc3BankSel) << endl
4258  << "LUT4 Bank Select: " << SetNotset(cc4BankSel);
4259  return oss.str();
4260  }
4261  } mLUTV1ControlRegDecoder;
4262 
4263  struct DecodeLUTV2ControlReg : public Decoder // kRegLUTV2Control 376
4264  {
4265  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4266  { (void) inRegNum;
4267  const ULWord lutVersion (::NTV2DeviceGetLUTVersion(inDeviceID));
4268  ostringstream oss;
4269  if (lutVersion != 2)
4270  oss << "(Register data relevant for V2 LUT, this device has V" << DEC(lutVersion) << "LUT)";
4271  else
4272  {
4273  for (UWord lutNum(0); lutNum < 8; lutNum++)
4274  oss << "LUT" << DEC(lutNum+1) << " Enabled: " << (YesNo(inRegValue & (1<<lutNum))) << endl
4275  << "LUT" << DEC(lutNum+1) << " Host Access Bank Select: " << (inRegValue & (1<<(lutNum+8)) ? '1' : '0') << endl
4276  << "LUT" << DEC(lutNum+1) << " Output Bank Select: " << (inRegValue & (1<<(lutNum+16)) ? '1' : '0') << endl;
4277  oss << "12-Bit LUT mode: " << ((inRegValue & BIT(28)) ? "12-bit" : "10-bit") << endl
4278  << "12-Bit LUT page reg: " << DEC(UWord((inRegValue & (BIT(24)|BIT(25))) >> 24));
4279  }
4280  return oss.str();
4281  }
4282  } mLUTV2ControlRegDecoder;
4283 
4284  struct DecodeLUT : public Decoder
4285  {
4286  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4287  {
4288  (void) inDeviceID;
4289  static const ULWord RedReg(kColorCorrectionLUTOffset_Red/4), GreenReg(kColorCorrectionLUTOffset_Green/4), BlueReg(kColorCorrectionLUTOffset_Blue/4);
4290  const bool isRed(inRegNum >= RedReg && inRegNum < GreenReg), isGreen(inRegNum >= GreenReg && inRegNum < BlueReg), isBlue(inRegNum>=BlueReg);
4291  NTV2_ASSERT(isRed||isGreen||isBlue);
4292  ostringstream oss;
4293  // Within each 32-bit LUT word are stored two 10-bit values:
4294  // - bits <31:22> ==> LUT[2i+1]
4295  // - bits <15:6> ==> LUT[2i]
4296  const string label(isRed ? "Red[" : (isGreen ? "Green[" : "Blue["));
4297  const ULWord ndx((inRegNum - (isRed ? RedReg : (isGreen ? GreenReg : BlueReg))) * 2);
4298  const ULWord lo((inRegValue >> kRegColorCorrectionLUTEvenShift) & 0x000003FF);
4299  const ULWord hi((inRegValue >> kRegColorCorrectionLUTOddShift) & 0x000003FF);
4300  oss << label << DEC0N(ndx+0,3) << "]: " << DEC0N(lo,3) << endl
4301  << label << DEC0N(ndx+1,3) << "]: " << DEC0N(hi,3);
4302  return oss.str();
4303  }
4304  } mLUTDecoder;
4305 
4306  struct DecodeSDIErrorStatus : public Decoder
4307  {
4308  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4309  {
4310  (void) inRegNum;
4311  (void) inDeviceID;
4312  ostringstream oss;
4313  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
4314  oss << "Unlock Tally: " << DEC(inRegValue & 0x7FFF) << endl
4315  << "Locked: " << YesNo(inRegValue & BIT(16)) << endl
4316  << "Link A VPID Valid: " << YesNo(inRegValue & BIT(20)) << endl
4317  << "Link B VPID Valid: " << YesNo(inRegValue & BIT(21)) << endl
4318  << "TRS Error Detected: " << YesNo(inRegValue & BIT(24));
4319  return oss.str();
4320  }
4321  } mSDIErrorStatusRegDecoder;
4322 
4323  struct DecodeSDIErrorCount : public Decoder
4324  {
4325  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4326  {
4327  (void) inRegNum;
4328  (void) inDeviceID;
4329  ostringstream oss;
4330  if (::NTV2DeviceCanDoSDIErrorChecks(inDeviceID))
4331  oss << "Link A: " << DEC(inRegValue & 0x0000FFFF) << endl
4332  << "Link B: " << DEC((inRegValue & 0xFFFF0000) >> 16);
4333  return oss.str();
4334  }
4335  } mSDIErrorCountRegDecoder;
4336 
4337  struct DecodeDriverVersion : public Decoder
4338  {
4339  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4340  { (void) inDeviceID;
4341  NTV2_ASSERT(inRegNum == kVRegDriverVersion);
4342  ULWord vMaj(NTV2DriverVersionDecode_Major(inRegValue)), vMin(NTV2DriverVersionDecode_Minor(inRegValue));
4343  ULWord vDot(NTV2DriverVersionDecode_Point(inRegValue)), vBld(NTV2DriverVersionDecode_Build(inRegValue));
4344  ULWord buildType((inRegValue >> 30) & 0x00000003);
4345  static const string sBuildTypes[] = { "Release", "Beta", "Alpha", "Development"};
4346  static const string sBldTypes[] = { "", "b", "a", "d"};
4347  ostringstream oss;
4348  oss << "Driver Version: " << DEC(vMaj) << "." << DEC(vMin) << "." << DEC(vDot);
4349  if (buildType) oss << sBldTypes[buildType] << DEC(vBld);
4350  oss << endl
4351  << "Major Version: " << DEC(vMaj) << endl
4352  << "Minor Version: " << DEC(vMin) << endl
4353  << "Point Version: " << DEC(vDot) << endl
4354  << "Build Type: " << sBuildTypes[buildType] << endl
4355  << "Build Number: " << DEC(vBld);
4356  return oss.str();
4357  }
4358  } mDriverVersionDecoder;
4359 
4360  struct DecodeFourCC : public Decoder
4361  {
4362  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4363  { (void) inDeviceID; (void) inRegNum;
4364  char ch; string str4cc;
4365  ch = char((inRegValue & 0xFF000000) >> 24);
4366  str4cc += ::isprint(ch) ? ch : '?';
4367  ch = char((inRegValue & 0x00FF0000) >> 16);
4368  str4cc += ::isprint(ch) ? ch : '?';
4369  ch = char((inRegValue & 0x0000FF00) >> 8);
4370  str4cc += ::isprint(ch) ? ch : '?';
4371  ch = char((inRegValue & 0x000000FF) >> 0);
4372  str4cc += ::isprint(ch) ? ch : '?';
4373 
4374  ostringstream oss;
4375  oss << "'" << str4cc << "'";
4376  return oss.str();
4377  }
4378  } mDecodeFourCC;
4379 
4380  struct DecodeDriverType : public Decoder
4381  {
4382  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4383  { (void) inDeviceID; (void) inRegNum;
4384  ostringstream oss;
4385  #if defined(AJAMac)
4386  if (inRegValue == 0x44455854) // 'DEXT'
4387  oss << "DriverKit ('DEXT')";
4388  else if (inRegValue)
4389  oss << "(Unknown/Invalid " << xHEX0N(inRegValue,8) << ")";
4390  else
4391  oss << "Kernel Extension ('KEXT')";
4392  #else
4393  (void) inRegValue;
4394  oss << "(Normal)";
4395  #endif
4396  return oss.str();
4397  }
4398  } mDecodeDriverType;
4399 
4400  struct DecodeIDSwitchStatus : public Decoder
4401  {
4402  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4403  { (void) inRegNum;
4404  ostringstream oss;
4405  if (::NTV2DeviceCanDoIDSwitch(inDeviceID))
4406  {
4407  const uint32_t switchEnableBits (((inRegValue & 0x0F000000) >> 20) | ((inRegValue & 0xF0000000) >> 28));
4408  for (UWord idSwitch(0); idSwitch < 4; )
4409  {
4410  const uint32_t switchEnabled (switchEnableBits & BIT(idSwitch));
4411  oss << "Switch " << DEC(++idSwitch) << ": " << (switchEnabled ? "Enabled" : "Disabled");
4412  if (idSwitch < 4)
4413  oss << endl;
4414  }
4415  }
4416  else
4417  {
4418  oss << "(ID Switch not supported)";
4419  }
4420 
4421  return oss.str();
4422  }
4423  } mDecodeIDSwitchStatus;
4424 
4425  struct DecodePWMFanControl : public Decoder
4426  {
4427  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4428  { (void) inRegNum;
4429  ostringstream oss;
4430  if (::NTV2DeviceHasPWMFanControl(inDeviceID))
4431  oss << "Fan Speed: " << DEC(inRegValue & kRegMaskPWMFanSpeed) << endl
4432  << "Fan Control Enabled: " << ((inRegValue & kRegMaskPWMFanSpeedControl) ? "Enabled" : "Disabled");
4433  return oss.str();
4434  }
4435  } mDecodePWMFanControl;
4436 
4437  struct DecodePWMFanMonitor : public Decoder
4438  {
4439  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4440  { (void) inRegNum;
4441  ostringstream oss;
4442  if (::NTV2DeviceHasPWMFanControl(inDeviceID))
4443  oss << "Tach Period: " << DEC(inRegValue & kRegMaskPWMFanTachPeriodStatus) << endl
4444  << "Fan Status: " << ((inRegValue & kRegMaskPWMFanStatus) ? "Stopped" : "Running");
4445  return oss.str();
4446  }
4447  } mDecodePWMFanMonitor;
4448 
4449  struct DecodeBOBStatus : public Decoder
4450  {
4451  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4452  { (void) inRegNum;
4453  ostringstream oss;
4454  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4455  oss << "BOB : " << ((inRegValue & kRegMaskBOBAbsent) ? "Disconnected" : "Connected") << endl
4456  << "ADAV801 Initializatioin: " << ((inRegValue & kRegMaskBOBADAV801UpdateStatus) ? "Complete" : "In Progress") << endl
4457  << "ADAV801 DIR Locked(Debug): " << DEC(inRegValue & kRegMaskBOBADAV801DIRLocked);
4458  else
4459  oss << "Device does not support a breakout board";
4460  return oss.str();
4461  }
4462  } mDecodeBOBStatus;
4463 
4464  struct DecodeBOBGPIIn : public Decoder
4465  {
4466  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4467  { (void) inRegNum;
4468  ostringstream oss;
4469  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4470  oss << "GPI In 1: " << DEC(inRegValue & kRegMaskBOBGPIIn1Data) << endl
4471  << "GPI In 2: " << DEC(inRegValue & kRegMaskBOBGPIIn2Data) << endl
4472  << "GPI In 3: " << DEC(inRegValue & kRegMaskBOBGPIIn3Data) << endl
4473  << "GPI In 4: " << DEC(inRegValue & kRegMaskBOBGPIIn4Data) ;
4474  else
4475  oss << "Device does not support a breakout board";
4476  return oss.str();
4477  }
4478  } mDecodeBOBGPIIn;
4479 
4480  struct DecodeBOBGPIInInterruptControl : public Decoder
4481  {
4482  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4483  { (void) inRegNum;
4484  ostringstream oss;
4485  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4486  oss << "GPI In 1 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn1InterruptControl) << endl
4487  << "GPI In 2 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn2InterruptControl) << endl
4488  << "GPI In 3 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn3InterruptControl) << endl
4489  << "GPI In 4 Int: " << DEC(inRegValue & kRegMaskBOBGPIIn4InterruptControl) ;
4490  else
4491  oss << "Device does not support a breakout board";
4492  return oss.str();
4493  }
4494  } mDecodeBOBGPIInInterruptControl;
4495 
4496  struct DecodeBOBGPIOut : public Decoder
4497  {
4498  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4499  { (void) inRegNum;
4500  ostringstream oss;
4501  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4502  oss << "GPI Out 1 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut1Data) << endl
4503  << "GPI Out 2 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut2Data) << endl
4504  << "GPI Out 3 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut3Data) << endl
4505  << "GPI Out 4 Int: " << DEC(inRegValue & kRegMaskBOBGPIOut4Data) ;
4506  else
4507  oss << "Device does not support a breakout board";
4508  return oss.str();
4509  }
4510  } mDecodeBOBGPIOut;
4511 
4512  struct DecodeBOBAudioControl : public Decoder
4513  {
4514  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4515  { (void) inRegNum;
4516  ostringstream oss;
4517  if (::NTV2DeviceCanDoBreakoutBoard(inDeviceID))
4518  {
4519  string dBuLabel;
4520  switch(inRegValue & kRegMaskBOBAnalogLevelControl)
4521  {
4522  case 0:
4523  dBuLabel = "+24dBu";
4524  break;
4525  case 1:
4526  dBuLabel = "+18dBu";
4527  break;
4528  case 2:
4529  dBuLabel = "+12dBu";
4530  break;
4531  case 3:
4532  dBuLabel = "+15dBu";
4533  break;
4534 
4535  }
4536  oss << "ADC/DAC Re-init: " << DEC(inRegValue & kRegMaskBOBADAV801Reset) << endl
4537  << "Analog Level Control: " << dBuLabel << endl
4538  << "Analog Select: " << DEC(inRegValue & kRegMaskBOBAnalogInputSelect);
4539  }
4540  else
4541  oss << "Device does not support a breakout board";
4542  return oss.str();
4543  }
4544  } mDecodeBOBAudioControl;
4545 
4546  struct DecodeLEDControl : public Decoder
4547  {
4548  virtual string operator()(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
4549  { (void) inRegNum;
4550  ostringstream oss;
4551  if (::NTV2DeviceHasBracketLED(inDeviceID))
4552  oss << "Blue: " << DEC(inRegValue & kRegMaskLEDBlueControl) << endl
4553  << "Green: " << DEC(inRegValue & kRegMaskLEDGreenControl) << endl
4554  << "Red: " << DEC(inRegValue & kRegMaskLEDRedControl);
4555  else
4556  oss << "Device does not support a breakout board";
4557  return oss.str();
4558  }
4559  } mDecodeLEDControl;
4560 
4561  static const int NOREADWRITE = 0;
4562  static const int READONLY = 1;
4563  static const int WRITEONLY = 2;
4564  static const int READWRITE = 3;
4565 
4566  static const int CONTAINS = 0;
4567  static const int STARTSWITH = 1;
4568  static const int ENDSWITH = 2;
4569  static const int EXACTMATCH = 3;
4570 
4571  typedef map <uint32_t, const Decoder *> RegNumToDecoderMap;
4572  typedef pair <uint32_t, const Decoder *> RegNumToDecoderPair;
4573  typedef multimap <string, uint32_t> RegClassToRegNumMMap, StringToRegNumMMap;
4574  typedef pair <string, uint32_t> StringToRegNumPair;
4575  typedef RegClassToRegNumMMap::const_iterator RegClassToRegNumConstIter;
4576  typedef StringToRegNumMMap::const_iterator StringToRegNumConstIter;
4577 
4578  typedef pair <uint32_t, uint32_t> XptRegNumAndMaskIndex; // First: register number; second: mask index (0=0x000000FF, 1=0x0000FF00, 2=0x00FF0000, 3=0xFF000000)
4579  typedef map <NTV2InputCrosspointID, XptRegNumAndMaskIndex> InputXpt2XptRegNumMaskIndexMap;
4580  typedef map <XptRegNumAndMaskIndex, NTV2InputCrosspointID> XptRegNumMaskIndex2InputXptMap;
4581  typedef InputXpt2XptRegNumMaskIndexMap::const_iterator InputXpt2XptRegNumMaskIndexMapConstIter;
4582  typedef XptRegNumMaskIndex2InputXptMap::const_iterator XptRegNumMaskIndex2InputXptMapConstIter;
4583 
4584 private: // INSTANCE DATA
4585  mutable AJALock mGuardMutex;
4586  RegNumToStringMap mRegNumToStringMap;
4587  RegNumToDecoderMap mRegNumToDecoderMap;
4588  RegClassToRegNumMMap mRegClassToRegNumMMap;
4589  StringToRegNumMMap mStringToRegNumMMap;
4590  mutable NTV2StringSet mAllRegClasses; // Mutable -- caches results from 'const' method GetAllRegisterClasses
4591  InputXpt2XptRegNumMaskIndexMap mInputXpt2XptRegNumMaskIndexMap;
4592  XptRegNumMaskIndex2InputXptMap mXptRegNumMaskIndex2InputXptMap;
4593 
4594 }; // RegisterExpert
4595 
4596 
4597 static RegisterExpertPtr gpRegExpert; // Points to Register Expert Singleton
4598 static AJALock gRegExpertGuardMutex;
4599 
4600 
4601 RegisterExpertPtr RegisterExpert::GetInstance(const bool inCreateIfNecessary)
4602 {
4603  AJAAutoLock locker(&gRegExpertGuardMutex);
4604  if (!gpRegExpert && inCreateIfNecessary)
4605  gpRegExpert = new RegisterExpert;
4606  return gpRegExpert;
4607 }
4608 
4609 bool RegisterExpert::DisposeInstance(void)
4610 {
4611  AJAAutoLock locker(&gRegExpertGuardMutex);
4612  if (!gpRegExpert)
4613  return false;
4614  gpRegExpert = AJA_NULL;
4615  return true;
4616 }
4617 
4618 bool CNTV2RegisterExpert::Allocate(void)
4619 {
4620  AJAAutoLock lock(&gRegExpertGuardMutex);
4621  RegisterExpertPtr pInst(RegisterExpert::GetInstance(true));
4622  return pInst ? true : false;
4623 }
4624 
4625 bool CNTV2RegisterExpert::IsAllocated(void)
4626 {
4627  AJAAutoLock lock(&gRegExpertGuardMutex);
4628  RegisterExpertPtr pInst(RegisterExpert::GetInstance(false));
4629  return pInst ? true : false;
4630 }
4631 
4632 bool CNTV2RegisterExpert::Deallocate(void)
4633 {
4634  AJAAutoLock lock(&gRegExpertGuardMutex);
4635  RegisterExpertPtr pInst(RegisterExpert::GetInstance(false));
4636  return pInst ? pInst->DisposeInstance() : false;
4637 }
4638 
4639 string CNTV2RegisterExpert::GetDisplayName (const uint32_t inRegNum)
4640 {
4641  AJAAutoLock locker(&gRegExpertGuardMutex);
4642  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4643  if (pRegExpert)
4644  return pRegExpert->RegNameToString(inRegNum);
4645 
4646  ostringstream oss; oss << "Reg ";
4647  if (inRegNum <= kRegNumRegisters)
4648  oss << DEC(inRegNum);
4649  else if (inRegNum <= 0x0000FFFF)
4650  oss << xHEX0N(inRegNum,4);
4651  else
4652  oss << xHEX0N(inRegNum,8);
4653  return oss.str();
4654 }
4655 
4656 string CNTV2RegisterExpert::GetDisplayValue (const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID)
4657 {
4658  AJAAutoLock locker(&gRegExpertGuardMutex);
4659  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4660  return pRegExpert ? pRegExpert->RegValueToString(inRegNum, inRegValue, inDeviceID) : string();
4661 }
4662 
4663 bool CNTV2RegisterExpert::IsRegisterInClass (const uint32_t inRegNum, const string & inClassName)
4664 {
4665  AJAAutoLock locker(&gRegExpertGuardMutex);
4666  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4667  return pRegExpert ? pRegExpert->IsRegInClass(inRegNum, inClassName) : false;
4668 }
4669 
4670 NTV2StringSet CNTV2RegisterExpert::GetAllRegisterClasses (void)
4671 {
4672  AJAAutoLock locker(&gRegExpertGuardMutex);
4673  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4674  return pRegExpert ? pRegExpert->GetAllRegisterClasses() : NTV2StringSet();
4675 }
4676 
4677 NTV2StringSet CNTV2RegisterExpert::GetRegisterClasses (const uint32_t inRegNum, const bool inRemovePrefix)
4678 {
4679  AJAAutoLock locker(&gRegExpertGuardMutex);
4680  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4681  return pRegExpert ? pRegExpert->GetRegisterClasses(inRegNum, inRemovePrefix) : NTV2StringSet();
4682 }
4683 
4684 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForClass (const string & inClassName)
4685 {
4686  AJAAutoLock locker(&gRegExpertGuardMutex);
4687  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4688  return pRegExpert ? pRegExpert->GetRegistersForClass(inClassName) : NTV2RegNumSet();
4689 }
4690 
4691 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForChannel (const NTV2Channel inChannel)
4692 {
4693  AJAAutoLock locker(&gRegExpertGuardMutex);
4694  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4695  return NTV2_IS_VALID_CHANNEL(inChannel) ? (pRegExpert ? pRegExpert->GetRegistersForClass(gChlClasses[inChannel]):NTV2RegNumSet()) : NTV2RegNumSet();
4696 }
4697 
4698 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersForDevice (const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude)
4699 {
4700  AJAAutoLock locker(&gRegExpertGuardMutex);
4701  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4702  return pRegExpert ? pRegExpert->GetRegistersForDevice(inDeviceID, inOtherRegsToInclude) : NTV2RegNumSet();
4703 }
4704 
4705 NTV2RegNumSet CNTV2RegisterExpert::GetRegistersWithName (const string & inName, const int inSearchStyle)
4706 {
4707  AJAAutoLock locker(&gRegExpertGuardMutex);
4708  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4709  return pRegExpert ? pRegExpert->GetRegistersWithName(inName, inSearchStyle) : NTV2RegNumSet();
4710 }
4711 
4712 NTV2InputCrosspointID CNTV2RegisterExpert::GetInputCrosspointID (const uint32_t inXptRegNum, const uint32_t inMaskIndex)
4713 {
4714  AJAAutoLock locker(&gRegExpertGuardMutex);
4715  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4716  return pRegExpert ? pRegExpert->GetInputCrosspointID(inXptRegNum, inMaskIndex) : NTV2_INPUT_CROSSPOINT_INVALID;
4717 }
4718 
4719 bool CNTV2RegisterExpert::GetCrosspointSelectGroupRegisterInfo (const NTV2InputCrosspointID inInputXpt, uint32_t & outXptRegNum, uint32_t & outMaskIndex)
4720 {
4721  AJAAutoLock locker(&gRegExpertGuardMutex);
4722  RegisterExpertPtr pRegExpert(RegisterExpert::GetInstance());
4723  return pRegExpert ? pRegExpert->GetXptRegNumAndMaskIndex(inInputXpt, outXptRegNum, outMaskIndex) : false;
4724 }
kRegSDIOut6VPIDB
@ kRegSDIOut6VPIDB
Definition: ntv2publicinterface.h:572
kRegDMA1NextDescHigh
@ kRegDMA1NextDescHigh
Definition: ntv2publicinterface.h:208
kVRegServicesModeFinal
@ kVRegServicesModeFinal
Definition: ntv2virtualregisters.h:494
kRegSDIInput3GStatus
@ kRegSDIInput3GStatus
Definition: ntv2publicinterface.h:355
kVRegTxc_2EncodeBitDepth1
@ kVRegTxc_2EncodeBitDepth1
Definition: ntv2virtualregisters.h:429
NTV2DeviceGetNumLTCInputs
UWord NTV2DeviceGetNumLTCInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11290
regAncExtFID
@ regAncExtFID
Definition: ntv2publicinterface.h:5181
CNTV2RegisterExpert::GetCrosspointSelectGroupRegisterInfo
static bool GetCrosspointSelectGroupRegisterInfo(const NTV2InputCrosspointID inInputXpt, uint32_t &outXptRegNum, uint32_t &outMaskIndex)
Answers with the crosspoint select register and mask information for a given widget input.
Definition: ntv2registerexpert.cpp:4719
kRegMaskLEDGreenControl
@ kRegMaskLEDGreenControl
Definition: ntv2publicinterface.h:2238
kVRegTxc_2EncodeStreamType2
@ kVRegTxc_2EncodeStreamType2
Definition: ntv2virtualregisters.h:445
regNTV4FS_RasterOffsetRed
@ regNTV4FS_RasterOffsetRed
Definition: ntv2registerexpert.cpp:75
NTV2DeviceCanDoCustomAux
bool NTV2DeviceCanDoCustomAux(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2225
regAncExtField2AnalogCFilter
@ regAncExtField2AnalogCFilter
Definition: ntv2publicinterface.h:5193
kRegGlobalControlCh3
@ kRegGlobalControlCh3
Definition: ntv2publicinterface.h:528
kRegShiftLUTSelect
@ kRegShiftLUTSelect
Definition: ntv2publicinterface.h:2456
kVRegMonAncField1Offset
@ kVRegMonAncField1Offset
Monitor Anc Field1 byte offset from end of frame buffer (IoIP only, GUMP)
Definition: ntv2virtualregisters.h:331
kVRegVideoFormatCh4
@ kVRegVideoFormatCh4
Definition: ntv2virtualregisters.h:349
kRegHDMIV2VSyncDurationAndBackPorchField1
@ kRegHDMIV2VSyncDurationAndBackPorchField1
Definition: ntv2publicinterface.h:511
kRegSDIOut4Control
@ kRegSDIOut4Control
Definition: ntv2publicinterface.h:290
kRegMaskBOBGPIIn3InterruptControl
@ kRegMaskBOBGPIIn3InterruptControl
Definition: ntv2publicinterface.h:2225
kRegGlobalControlCh5
@ kRegGlobalControlCh5
Definition: ntv2publicinterface.h:530
regAncExtTotalFrameLines
@ regAncExtTotalFrameLines
Definition: ntv2publicinterface.h:5180
kVRegAnalogAudioIOConfiguration
@ kVRegAnalogAudioIOConfiguration
Definition: ntv2virtualregisters.h:486
kRegSDIIn8VPIDB
@ kRegSDIIn8VPIDB
Definition: ntv2publicinterface.h:590
kVRegClearAllSubscriptions
@ kVRegClearAllSubscriptions
Definition: ntv2virtualregisters.h:64
kRegSDIWatchdogTimeout
@ kRegSDIWatchdogTimeout
Definition: ntv2publicinterface.h:440
kVRegProgressivePicture
@ kVRegProgressivePicture
Definition: ntv2virtualregisters.h:222
NTV2_XptDualLinkIn3DSInput
@ NTV2_XptDualLinkIn3DSInput
Definition: ntv2enums.h:2789
kRegHDMIV2VerticalMeasurementsField0
@ kRegHDMIV2VerticalMeasurementsField0
Definition: ntv2publicinterface.h:519
kRegXptSelectGroup32
@ kRegXptSelectGroup32
Definition: ntv2publicinterface.h:684
kRegHDMIHDRControl
@ kRegHDMIHDRControl
Definition: ntv2publicinterface.h:471
NTV2DeviceCanDo12GSDI
bool NTV2DeviceCanDo12GSDI(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:385
kVRegTxcSfp1RemotePort3
@ kVRegTxcSfp1RemotePort3
Definition: ntv2virtualregisters.h:399
kRegSDIOut2VPIDB
@ kRegSDIOut2VPIDB
Definition: ntv2publicinterface.h:360
NTV2_XptMixer4BGKeyInput
@ NTV2_XptMixer4BGKeyInput
Definition: ntv2enums.h:2820
kRegCh2OutputFrame
@ kRegCh2OutputFrame
Definition: ntv2publicinterface.h:109
kRegCh7Control
@ kRegCh7Control
Definition: ntv2publicinterface.h:545
kVRegHDMIInAviInfo2
@ kVRegHDMIInAviInfo2
Definition: ntv2virtualregisters.h:616
kVRegNTV2VPIDTransferCharacteristics7
@ kVRegNTV2VPIDTransferCharacteristics7
Definition: ntv2virtualregisters.h:523
NTV2_XptMixer3FGVidInput
@ NTV2_XptMixer3FGVidInput
Definition: ntv2enums.h:2819
kRegMaskLUTSelect
@ kRegMaskLUTSelect
Definition: ntv2publicinterface.h:1372
kRegCh8Control
@ kRegCh8Control
Definition: ntv2publicinterface.h:550
regAncInsPayloadIDControl
@ regAncInsPayloadIDControl
Definition: ntv2publicinterface.h:5215
regNTV4FS_RasterOffsetBlue
@ regNTV4FS_RasterOffsetBlue
Definition: ntv2registerexpert.cpp:74
kRegCS6Coefficients1_2
@ kRegCS6Coefficients1_2
Definition: ntv2publicinterface.h:628
kLHIRegMaskHDMIOutFPS
@ kLHIRegMaskHDMIOutFPS
Definition: ntv2publicinterface.h:1523
REiNOTE
#define REiNOTE(__x__)
Definition: ntv2registerexpert.cpp:38
kVRegETTDiagLastSerialTimestamp
@ kVRegETTDiagLastSerialTimestamp
Definition: ntv2virtualregisters.h:249
NTV2_XptHDMIOutInput
@ NTV2_XptHDMIOutInput
Definition: ntv2enums.h:2824
kRegXptSelectGroup25
@ kRegXptSelectGroup25
Definition: ntv2publicinterface.h:560
kRegXptSelectGroup13
@ kRegXptSelectGroup13
Definition: ntv2publicinterface.h:386
kVRegServicesForceInit
@ kVRegServicesForceInit
Definition: ntv2virtualregisters.h:493
kRegFlatMatteValue
@ kRegFlatMatteValue
Definition: ntv2publicinterface.h:115
kVRegDmaHardwareRateC2H4
@ kVRegDmaHardwareRateC2H4
Definition: ntv2virtualregisters.h:605
kRegShiftInputStatusFPS
@ kRegShiftInputStatusFPS
Definition: ntv2publicinterface.h:2631
regAncExtIgnorePacketReg_13_14_15_16
@ regAncExtIgnorePacketReg_13_14_15_16
Definition: ntv2publicinterface.h:5186
NTV2_Xpt425Mux1AInput
@ NTV2_Xpt425Mux1AInput
Definition: ntv2enums.h:2833
kVRegHdrMasterLumMaxCh1
@ kVRegHdrMasterLumMaxCh1
Definition: ntv2virtualregisters.h:546
kRegShiftHDRStaticMetadataDescriptorID
@ kRegShiftHDRStaticMetadataDescriptorID
Definition: ntv2publicinterface.h:3199
kVRegHDMIInDrmBluePrimary1
@ kVRegHDMIInDrmBluePrimary1
Definition: ntv2virtualregisters.h:611
kVRegRxcSfp2DestIp2
@ kVRegRxcSfp2DestIp2
Definition: ntv2virtualregisters.h:389
gLivingInstances
static uint32_t gLivingInstances(0)
kVRegSyncChannels
@ kVRegSyncChannels
Definition: ntv2virtualregisters.h:89
kRegCMW14835Out
@ kRegCMW14835Out
Definition: ntv2publicinterface.h:1081
kVRegTimeStampLastOutput3VerticalLo
@ kVRegTimeStampLastOutput3VerticalLo
Definition: ntv2virtualregisters.h:283
kVRegLastAJA
@ kVRegLastAJA
The last AJA virtual register slot.
Definition: ntv2virtualregisters.h:629
kRegXptSelectGroup22
@ kRegXptSelectGroup22
Definition: ntv2publicinterface.h:556
kRegShiftHDMIHDRWhitePointY
@ kRegShiftHDMIHDRWhitePointY
Definition: ntv2publicinterface.h:3189
kVReg4kOutputTransportSelection
@ kVReg4kOutputTransportSelection
Definition: ntv2virtualregisters.h:340
kRegClass_Virtual
#define kRegClass_Virtual
Definition: ntv2registerexpert.h:70
kRegEnhancedCSC1CoeffB2
@ kRegEnhancedCSC1CoeffB2
Definition: ntv2publicinterface.h:862
kVRegHdrBlueYCh1
@ kVRegHdrBlueYCh1
Definition: ntv2virtualregisters.h:541
kRegMaskAudioMixerChannelSelect
@ kRegMaskAudioMixerChannelSelect
Definition: ntv2publicinterface.h:2143
NTV2_XptDualLinkOut7Input
@ NTV2_XptDualLinkOut7Input
Definition: ntv2enums.h:2806
regAuxExtPacketMask0
@ regAuxExtPacketMask0
Definition: ntv2publicinterface.h:5287
kRegEnhancedCSC1OutOffsetC
@ kRegEnhancedCSC1OutOffsetC
Definition: ntv2publicinterface.h:867
kRegXptSelectGroup33
@ kRegXptSelectGroup33
Definition: ntv2publicinterface.h:685
kRegHDMIHDRWhitePoint
@ kRegHDMIHDRWhitePoint
Definition: ntv2publicinterface.h:468
kVRegRxcSfp1SourceIp1
@ kVRegRxcSfp1SourceIp1
Definition: ntv2virtualregisters.h:366
kVRegAudioMonitorChannelSelect
@ kVRegAudioMonitorChannelSelect
Definition: ntv2virtualregisters.h:468
kRegLTC6EmbeddedBits0_31
@ kRegLTC6EmbeddedBits0_31
Definition: ntv2publicinterface.h:576
kVRegProcAmpStandardDefHue
@ kVRegProcAmpStandardDefHue
Definition: ntv2virtualregisters.h:200
kRegMaskPWMFanTachPeriodStatus
@ kRegMaskPWMFanTachPeriodStatus
Definition: ntv2publicinterface.h:2211
kVRegTxc_2EncodeAudio1Pid1
@ kVRegTxc_2EncodeAudio1Pid1
Definition: ntv2virtualregisters.h:437
kRegXptSelectGroup6
@ kRegXptSelectGroup6
Definition: ntv2publicinterface.h:257
kRegCS3Coefficients9_10
@ kRegCS3Coefficients9_10
Definition: ntv2publicinterface.h:419
NTV2BitfileHeaderParser::GetDesignID
static ULWord GetDesignID(const ULWord userID)
Definition: ntv2bitfile.h:54
kRegHDMIV2i2c2Control
@ kRegHDMIV2i2c2Control
Definition: ntv2publicinterface.h:521
kVRegRxc_2DecodeAudioNumber1
@ kVRegRxc_2DecodeAudioNumber1
Definition: ntv2virtualregisters.h:420
kRegAud5Delay
@ kRegAud5Delay
Definition: ntv2publicinterface.h:668
kRegMaskChannelDisable
@ kRegMaskChannelDisable
Definition: ntv2publicinterface.h:1234
regAncExtField1Status
@ regAncExtField1Status
Definition: ntv2publicinterface.h:5177
kRegRXSDI8Status
@ kRegRXSDI8Status
Definition: ntv2publicinterface.h:765
kRegOutputTimingControlch6
@ kRegOutputTimingControlch6
Definition: ntv2publicinterface.h:654
kRegRP188InOut3Bits32_63_2
@ kRegRP188InOut3Bits32_63_2
Definition: ntv2publicinterface.h:330
kRegShiftInputStatusStd
@ kRegShiftInputStatusStd
Definition: ntv2publicinterface.h:2629
RegisterExpert::PrintLabelValuePairs
static ostream & PrintLabelValuePairs(ostream &oss, const AJALabelValuePairs &inLabelValuePairs)
Definition: ntv2registerexpert.cpp:1739
NTV2DeviceGetNumHDMIVideoInputs
UWord NTV2DeviceGetNumHDMIVideoInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11017
kVRegChannelCrosspointFirst
@ kVRegChannelCrosspointFirst
Definition: ntv2virtualregisters.h:320
kVReg2022_7NetworkPathDiff
@ kVReg2022_7NetworkPathDiff
Definition: ntv2virtualregisters.h:452
CNTV2RegisterExpert::GetRegistersForDevice
static NTV2RegNumSet GetRegistersForDevice(const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude=0)
Definition: ntv2registerexpert.cpp:4698
kRegAud4Delay
@ kRegAud4Delay
Definition: ntv2publicinterface.h:432
kVRegUseProgressive
@ kVRegUseProgressive
Definition: ntv2virtualregisters.h:298
NTV2FrameGeometryToString
std::string NTV2FrameGeometryToString(const NTV2FrameGeometry inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7197
sNTV4FrameStoreRegNames
static const std::string sNTV4FrameStoreRegNames[]
Definition: ntv2registerexpert.cpp:82
regAncInsFrameLines
@ regAncInsFrameLines
Definition: ntv2publicinterface.h:5213
kRegAud1OutputLastAddr
@ kRegAud1OutputLastAddr
Definition: ntv2publicinterface.h:129
kVRegDmaSerialize
@ kVRegDmaSerialize
Definition: ntv2virtualregisters.h:87
kRegRP188InOut3DBB
@ kRegRP188InOut3DBB
Definition: ntv2publicinterface.h:391
kRegEnhancedCSC1CoeffA1
@ kRegEnhancedCSC1CoeffA1
Definition: ntv2publicinterface.h:858
kRegAud7Delay
@ kRegAud7Delay
Definition: ntv2publicinterface.h:670
kRegMaskAud6PlayCapMode
@ kRegMaskAud6PlayCapMode
Definition: ntv2publicinterface.h:1186
kVRegUserInTransfer
@ kVRegUserInTransfer
Definition: ntv2virtualregisters.h:555
kVRegProcAmpHighDefSaturationCb
@ kVRegProcAmpHighDefSaturationCb
Definition: ntv2virtualregisters.h:208
kVRegTxcSfp2LocalPort3
@ kVRegTxcSfp2LocalPort3
Definition: ntv2virtualregisters.h:400
kVRegNTV2VPIDColorimetry5
@ kVRegNTV2VPIDColorimetry5
Definition: ntv2virtualregisters.h:516
kRegMaskHDMIInV2VideoStd
@ kRegMaskHDMIInV2VideoStd
Definition: ntv2publicinterface.h:1543
kRegBoardID
@ kRegBoardID
Definition: ntv2publicinterface.h:153
kRegMixer1Coefficient
@ kRegMixer1Coefficient
Definition: ntv2publicinterface.h:113
kRegMaskBOBGPIOut2Data
@ kRegMaskBOBGPIOut2Data
Definition: ntv2publicinterface.h:2229
kK2RegMaskConverterInRate
@ kK2RegMaskConverterInRate
Definition: ntv2publicinterface.h:1614
NTV2_XptSDIOut4InputDS2
@ NTV2_XptSDIOut4InputDS2
Definition: ntv2enums.h:2775
kRegMaskLED
@ kRegMaskLED
Definition: ntv2publicinterface.h:1167
kRegAudioMixerAux1GainCh2
@ kRegAudioMixerAux1GainCh2
Definition: ntv2publicinterface.h:800
kVRegHDMIOutProtocolMode
@ kVRegHDMIOutProtocolMode
Definition: ntv2virtualregisters.h:140
kRegRP188InOut6Bits32_63_2
@ kRegRP188InOut6Bits32_63_2
Definition: ntv2publicinterface.h:336
kVRegRxcSfp2Vlan2
@ kVRegRxcSfp2Vlan2
Definition: ntv2virtualregisters.h:392
kRegXptSelectGroup14
@ kRegXptSelectGroup14
Definition: ntv2publicinterface.h:387
kRegDMA4HostAddrHigh
@ kRegDMA4HostAddrHigh
Definition: ntv2publicinterface.h:213
regAncInsRtpSSRC
@ regAncInsRtpSSRC
Definition: ntv2publicinterface.h:5223
kRegShiftAudioMixerOutputChannelsMute
@ kRegShiftAudioMixerOutputChannelsMute
Definition: ntv2publicinterface.h:3205
kRegCS8Coefficients9_10
@ kRegCS8Coefficients9_10
Definition: ntv2publicinterface.h:644
kVRegRxcSfp2RxMatch1
@ kVRegRxcSfp2RxMatch1
Definition: ntv2virtualregisters.h:371
kRegMaskBOBGPIIn2Data
@ kRegMaskBOBGPIIn2Data
Definition: ntv2publicinterface.h:2219
kRegEnhancedCSC1KeyClipOffset
@ kRegEnhancedCSC1KeyClipOffset
Definition: ntv2publicinterface.h:869
kVRegSubnetEth1
@ kVRegSubnetEth1
Definition: ntv2virtualregisters.h:361
kRegRP188InOut2Bits0_31
@ kRegRP188InOut2Bits0_31
Definition: ntv2publicinterface.h:168
kRegCS5Coefficients9_10
@ kRegCS5Coefficients9_10
Definition: ntv2publicinterface.h:492
kRegCh6OutputFrame
@ kRegCh6OutputFrame
Definition: ntv2publicinterface.h:541
kVRegSubnetEth0
@ kVRegSubnetEth0
Definition: ntv2virtualregisters.h:357
kVRegUseThermostat
@ kVRegUseThermostat
Definition: ntv2virtualregisters.h:342
NTV2DeviceHasNTV4FrameStores
bool NTV2DeviceHasNTV4FrameStores(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7069
kVRegTimeStampLastOutputVerticalLo
@ kVRegTimeStampLastOutputVerticalLo
Definition: ntv2virtualregisters.h:78
kVRegNTV2VPIDRGBRange4
@ kVRegNTV2VPIDRGBRange4
Definition: ntv2virtualregisters.h:578
kVRegProcAmpEndStandardDefRange
@ kVRegProcAmpEndStandardDefRange
Definition: ntv2virtualregisters.h:203
kRegCS5Coefficients3_4
@ kRegCS5Coefficients3_4
Definition: ntv2publicinterface.h:489
kRegMRQ3Control
@ kRegMRQ3Control
Definition: ntv2publicinterface.h:1034
kVRegHdrInGreenXCh1
@ kVRegHdrInGreenXCh1
Definition: ntv2virtualregisters.h:561
NTV2_XptDualLinkIn2DSInput
@ NTV2_XptDualLinkIn2DSInput
Definition: ntv2enums.h:2787
kVRegChannel2UserBufferLevel
@ kVRegChannel2UserBufferLevel
Definition: ntv2virtualregisters.h:217
kRegClass_HDR
#define kRegClass_HDR
Definition: ntv2registerexpert.h:55
NTV2_XptMixer2BGKeyInput
@ NTV2_XptMixer2BGKeyInput
Definition: ntv2enums.h:2812
kRegClass_Info
#define kRegClass_Info
Definition: ntv2registerexpert.h:57
kVRegAudioCapMixerSourceAux2Enable
@ kVRegAudioCapMixerSourceAux2Enable
Definition: ntv2virtualregisters.h:478
kRegRP188InOut1Bits0_31
@ kRegRP188InOut1Bits0_31
Definition: ntv2publicinterface.h:133
kVRegHdrInRedYCh1
@ kVRegHdrInRedYCh1
Definition: ntv2virtualregisters.h:566
kRegDMA2XferCount
@ kRegDMA2XferCount
Definition: ntv2publicinterface.h:141
kRegSDIIn6VPIDB
@ kRegSDIIn6VPIDB
Definition: ntv2publicinterface.h:570
kRegRXSDI4Status
@ kRegRXSDI4Status
Definition: ntv2publicinterface.h:729
kRegAudioMixerAux1InputLevels
@ kRegAudioMixerAux1InputLevels
Definition: ntv2publicinterface.h:805
kRegRP188InOut7Bits32_63
@ kRegRP188InOut7Bits32_63
Definition: ntv2publicinterface.h:584
kRegShiftHDMIHDRGreenPrimaryX
@ kRegShiftHDMIHDRGreenPrimaryX
Definition: ntv2publicinterface.h:3182
kVRegDSKMode
@ kVRegDSKMode
Definition: ntv2virtualregisters.h:117
kRegInvalidValidXptROMRegister
@ kRegInvalidValidXptROMRegister
Definition: ntv2publicinterface.h:848
kVRegAnalogOutputSelect
@ kVRegAnalogOutputSelect
Definition: ntv2virtualregisters.h:45
kRegMaskLUT5Select
@ kRegMaskLUT5Select
Definition: ntv2publicinterface.h:1371
kVRegVANCMode
@ kVRegVANCMode
Definition: ntv2virtualregisters.h:114
kVRegIpConfigStreamRefresh
@ kVRegIpConfigStreamRefresh
Definition: ntv2virtualregisters.h:188
kVRegChannel1UserBufferLevel
@ kVRegChannel1UserBufferLevel
Definition: ntv2virtualregisters.h:216
kVRegTxc_2EncodeUllMode1
@ kVRegTxc_2EncodeUllMode1
Definition: ntv2virtualregisters.h:428
NTV2_XptMixer2FGKeyInput
@ NTV2_XptMixer2FGKeyInput
Definition: ntv2enums.h:2814
kRegShiftHDMISampling
@ kRegShiftHDMISampling
Definition: ntv2publicinterface.h:2608
kVRegDigitalOutput1Select
@ kVRegDigitalOutput1Select
Definition: ntv2virtualregisters.h:43
kRegCS3Coefficients5_6
@ kRegCS3Coefficients5_6
Definition: ntv2publicinterface.h:417
NTV2_XptLUT7Input
@ NTV2_XptLUT7Input
Definition: ntv2enums.h:2762
NTV2_XptSDIOut3InputDS2
@ NTV2_XptSDIOut3InputDS2
Definition: ntv2enums.h:2773
NTV2StringSet
std::set< std::string > NTV2StringSet
Definition: ntv2utils.h:1146
kVRegHDMIOutStatus1
@ kVRegHDMIOutStatus1
Definition: ntv2virtualregisters.h:625
kRegDMA2NextDesc
@ kRegDMA2NextDesc
Definition: ntv2publicinterface.h:142
kRegCh5InputFrame
@ kRegCh5InputFrame
Definition: ntv2publicinterface.h:537
kRegMask425FB56
@ kRegMask425FB56
Definition: ntv2publicinterface.h:1199
kRegSDIIn7VPIDA
@ kRegSDIIn7VPIDA
Definition: ntv2publicinterface.h:579
kVRegDmaTransferRateH2C1
@ kVRegDmaTransferRateH2C1
Definition: ntv2virtualregisters.h:594
kRegAud2Delay
@ kRegAud2Delay
Definition: ntv2publicinterface.h:192
kVRegResetCycleCount
@ kVRegResetCycleCount
Definition: ntv2virtualregisters.h:297
regNTV4FS_Status
@ regNTV4FS_Status
Definition: ntv2registerexpert.cpp:69
kVRegHdrInColorimetryCh1
@ kVRegHdrInColorimetryCh1
Definition: ntv2virtualregisters.h:558
kRegClass_NULL
#define kRegClass_NULL
Definition: ntv2registerexpert.h:38
kRegMaskHDMIHDRBluePrimaryY
@ kRegMaskHDMIHDRBluePrimaryY
Definition: ntv2publicinterface.h:2124
kRegColorCorrectionLUTOddShift
#define kRegColorCorrectionLUTOddShift
Definition: ntv2publicinterface.h:4167
kRegCS6Coefficients3_4
@ kRegCS6Coefficients3_4
Definition: ntv2publicinterface.h:629
kVRegHDMIOutAudioChannels
@ kVRegHDMIOutAudioChannels
Definition: ntv2virtualregisters.h:464
kVRegAcquireReferenceCounter
@ kVRegAcquireReferenceCounter
Definition: ntv2virtualregisters.h:311
kRegHDMIV2HorizontalMeasurements
@ kRegHDMIV2HorizontalMeasurements
Definition: ntv2publicinterface.h:516
kRegMaskIsDNXIV
@ kRegMaskIsDNXIV
Definition: ntv2publicinterface.h:1196
kVRegAudioMixerSourceMainEnable
@ kVRegAudioMixerSourceMainEnable
Definition: ntv2virtualregisters.h:470
kVRegApplicationPID
@ kVRegApplicationPID
Definition: ntv2virtualregisters.h:183
kRegMaskAud8PlayCapMode
@ kRegMaskAud8PlayCapMode
Definition: ntv2publicinterface.h:1188
NTV2_XptCSC7VidInput
@ NTV2_XptCSC7VidInput
Definition: ntv2enums.h:2752
kRegOutputTimingControlch7
@ kRegOutputTimingControlch7
Definition: ntv2publicinterface.h:655
kRegInput78Status
@ kRegInput78Status
Definition: ntv2publicinterface.h:626
NTV2DeviceCanDoEnhancedCSC
bool NTV2DeviceCanDoEnhancedCSC(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2593
kRegMaskHDMIHDREnable
@ kRegMaskHDMIHDREnable
Definition: ntv2publicinterface.h:2136
kVRegIPAddrEth1
@ kVRegIPAddrEth1
Definition: ntv2virtualregisters.h:360
kVRegInput2UserBufferLevel
@ kVRegInput2UserBufferLevel
Definition: ntv2virtualregisters.h:219
kRegShiftCCOutputBankSelect
@ kRegShiftCCOutputBankSelect
Definition: ntv2publicinterface.h:2451
NTV2Channel
NTV2Channel
These enum values are mostly used to identify a specific widget_framestore. They're also commonly use...
Definition: ntv2enums.h:1334
kRegShiftAudioMixerChannelSelect
@ kRegShiftAudioMixerChannelSelect
Definition: ntv2publicinterface.h:3204
kRegAudioMixerAux1GainCh1
@ kRegAudioMixerAux1GainCh1
Definition: ntv2publicinterface.h:796
kVRegAnalogInStandard
@ kVRegAnalogInStandard
Definition: ntv2virtualregisters.h:179
NTV2_XptCSC5KeyInput
@ NTV2_XptCSC5KeyInput
Definition: ntv2enums.h:2749
kRegNumRegisters
@ kRegNumRegisters
Definition: ntv2publicinterface.h:691
kVRegNTV2VPIDLuminance1
@ kVRegNTV2VPIDLuminance1
Definition: ntv2virtualregisters.h:498
kVRegTimeCodeIn8Delay
@ kVRegTimeCodeIn8Delay
Definition: ntv2virtualregisters.h:106
kVRegNumberAudioMappingRegisters
@ kVRegNumberAudioMappingRegisters
Definition: ntv2virtualregisters.h:85
kRegMaskHDMIHDRRedPrimaryX
@ kRegMaskHDMIHDRRedPrimaryX
Definition: ntv2publicinterface.h:2125
regAncExtIgnorePacketReg_9_10_11_12
@ regAncExtIgnorePacketReg_9_10_11_12
Definition: ntv2publicinterface.h:5185
kRegCS3Coefficients7_8
@ kRegCS3Coefficients7_8
Definition: ntv2publicinterface.h:418
kRegCS5Coefficients7_8
@ kRegCS5Coefficients7_8
Definition: ntv2publicinterface.h:491
kVRegFanControl
@ kVRegFanControl
Definition: ntv2virtualregisters.h:58
NTV2_XptDualLinkIn1Input
@ NTV2_XptDualLinkIn1Input
Definition: ntv2enums.h:2784
AJARefPtr
I am a reference-counted pointer template class. I am intended to be a proxy for an underlying object...
Definition: ajarefptr.h:89
kVRegBitFileDownload
@ kVRegBitFileDownload
Definition: ntv2virtualregisters.h:61
NTV2_XptSDIOut5InputDS2
@ NTV2_XptSDIOut5InputDS2
Definition: ntv2enums.h:2777
kRegLTC5EmbeddedBits0_31
@ kRegLTC5EmbeddedBits0_31
Definition: ntv2publicinterface.h:483
aja::join
std::string join(const std::vector< std::string > &parts, const std::string &delim)
Definition: common.cpp:468
kRegAud6InputLastAddr
@ kRegAud6InputLastAddr
Definition: ntv2publicinterface.h:609
kK2RegMaskConverterInStandard
@ kK2RegMaskConverterInStandard
Definition: ntv2publicinterface.h:1613
kVRegFlashState
@ kVRegFlashState
Definition: ntv2virtualregisters.h:302
kVRegHDMIInDrmRedPrimary1
@ kVRegHDMIInDrmRedPrimary1
Definition: ntv2virtualregisters.h:612
kVRegTimelapseEnable
@ kVRegTimelapseEnable
Definition: ntv2virtualregisters.h:172
kRegLTC2EmbeddedBits0_31
@ kRegLTC2EmbeddedBits0_31
Definition: ntv2publicinterface.h:375
sShifts
static const ULWord sShifts[]
Definition: ntv2regroute.cpp:27
VIRTUALREG_START
#define VIRTUALREG_START
Definition: ntv2virtualregisters.h:12
kRegShiftAudioMixerAux2InputEnable
@ kRegShiftAudioMixerAux2InputEnable
Definition: ntv2publicinterface.h:3224
NTV2_ASSERT
#define NTV2_ASSERT(_expr_)
Definition: ajatypes.h:508
kRegBOBGPIInData
@ kRegBOBGPIInData
Definition: ntv2publicinterface.h:1059
kVRegTimelapseCaptureValue
@ kVRegTimelapseCaptureValue
Definition: ntv2virtualregisters.h:173
gChlClasses
static const string gChlClasses[]
Definition: ntv2registerexpert.cpp:46
kVRegHdrInGreenYCh1
@ kVRegHdrInGreenYCh1
Definition: ntv2virtualregisters.h:562
NTV2_XptCSC4VidInput
@ NTV2_XptCSC4VidInput
Definition: ntv2enums.h:2746
kRegAud8OutputLastAddr
@ kRegAud8OutputLastAddr
Definition: ntv2publicinterface.h:618
kRegSDIWatchdogKick1
@ kRegSDIWatchdogKick1
Definition: ntv2publicinterface.h:441
kRegCh3PCIAccessFrame
@ kRegCh3PCIAccessFrame
Definition: ntv2publicinterface.h:412
kRegCS2Coefficients9_10
@ kRegCS2Coefficients9_10
Definition: ntv2publicinterface.h:269
RegisterExpert::Print
ostream & Print(ostream &inOutStream) const
Definition: ntv2registerexpert.cpp:2074
kRegShiftFrameRate
@ kRegShiftFrameRate
Definition: ntv2publicinterface.h:2245
kRegMixer4Coefficient
@ kRegMixer4Coefficient
Definition: ntv2publicinterface.h:663
kVRegUserTransfer
@ kVRegUserTransfer
Definition: ntv2virtualregisters.h:532
NTV2_FIRST_INPUT_CROSSPOINT
@ NTV2_FIRST_INPUT_CROSSPOINT
Definition: ntv2enums.h:2723
kVRegHdrInRedXCh1
@ kVRegHdrInRedXCh1
Definition: ntv2virtualregisters.h:565
kRegXptSelectGroup5
@ kRegXptSelectGroup5
Definition: ntv2publicinterface.h:256
kRegRP188InOut6Bits0_31
@ kRegRP188InOut6Bits0_31
Definition: ntv2publicinterface.h:573
kVRegTxc_2EncodeBitDepth2
@ kVRegTxc_2EncodeBitDepth2
Definition: ntv2virtualregisters.h:441
kRegClass_LUT
#define kRegClass_LUT
Definition: ntv2registerexpert.h:60
NTV2DownConvertModeToString
std::string NTV2DownConvertModeToString(const NTV2DownConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6652
kRegAudioMixerMutes
@ kRegAudioMixerMutes
Definition: ntv2publicinterface.h:799
kRegEnhancedCSC1InOffset2
@ kRegEnhancedCSC1InOffset2
Definition: ntv2publicinterface.h:856
kRegAud8Control
@ kRegAud8Control
Definition: ntv2publicinterface.h:616
DEVICE_ID_IOX3
@ DEVICE_ID_IOX3
See IoX3.
Definition: ntv2enums.h:41
kRegMaskHDMIOutAudioSource
@ kRegMaskHDMIOutAudioSource
Definition: ntv2publicinterface.h:1889
kVRegAnalogInputType
@ kVRegAnalogInputType
Definition: ntv2virtualregisters.h:138
NTV2_XptMixer3BGKeyInput
@ NTV2_XptMixer3BGKeyInput
Definition: ntv2enums.h:2816
kVRegAcquireLinuxReferenceCount
@ kVRegAcquireLinuxReferenceCount
Definition: ntv2virtualregisters.h:262
kRegColorCorrectionLUTEvenShift
#define kRegColorCorrectionLUTEvenShift
Definition: ntv2publicinterface.h:4168
NTV2_XptMultiLinkOut1Input
@ NTV2_XptMultiLinkOut1Input
New in SDK 16.0.
Definition: ntv2enums.h:2764
kK2RegMaskEnableConverter
@ kK2RegMaskEnableConverter
Definition: ntv2publicinterface.h:1619
kRegMaskHDMIHDRGreenPrimaryX
@ kRegMaskHDMIHDRGreenPrimaryX
Definition: ntv2publicinterface.h:2121
kRegMaskHDMIHDRMaxMasteringLuminance
@ kRegMaskHDMIHDRMaxMasteringLuminance
Definition: ntv2publicinterface.h:2129
kVRegTimeStampLastInput8VerticalLo
@ kVRegTimeStampLastInput8VerticalLo
Definition: ntv2virtualregisters.h:277
kVRegSerialSuspended
@ kVRegSerialSuspended
Definition: ntv2virtualregisters.h:247
kK2RegMaskUpConvertMode
@ kK2RegMaskUpConvertMode
Definition: ntv2publicinterface.h:1611
kVRegNTV2VPIDColorimetry7
@ kVRegNTV2VPIDColorimetry7
Definition: ntv2virtualregisters.h:524
regNTV4FS_RasterVideoFill_YCb_GB
@ regNTV4FS_RasterVideoFill_YCb_GB
Definition: ntv2registerexpert.cpp:66
NTV2_XptDualLinkIn8Input
@ NTV2_XptDualLinkIn8Input
Definition: ntv2enums.h:2798
kRegMRSupport
@ kRegMRSupport
Definition: ntv2publicinterface.h:1037
kVRegSDIInput2Stereo3DMode
@ kVRegSDIInput2Stereo3DMode
Definition: ntv2virtualregisters.h:131
sNull
static const string sNull
Definition: ntv2registerexpert.cpp:49
kVRegAudioMixerSourceAux2Gain
@ kVRegAudioMixerSourceAux2Gain
Definition: ntv2virtualregisters.h:475
NTV2_XptDualLinkIn5DSInput
@ NTV2_XptDualLinkIn5DSInput
Definition: ntv2enums.h:2793
kVRegLatencyTimerValue
@ kVRegLatencyTimerValue
Definition: ntv2virtualregisters.h:244
kVRegProcAmpHighDefContrast
@ kVRegProcAmpHighDefContrast
Definition: ntv2virtualregisters.h:207
kRegShiftHDMIHDRMaxContentLightLevel
@ kRegShiftHDMIHDRMaxContentLightLevel
Definition: ntv2publicinterface.h:3192
kVRegSDIOutput2ColorSpaceMode
@ kVRegSDIOutput2ColorSpaceMode
Definition: ntv2virtualregisters.h:170
kRegCS6Coefficients5_6
@ kRegCS6Coefficients5_6
Definition: ntv2publicinterface.h:630
kVRegHdmiHdrOutChanged
@ kVRegHdmiHdrOutChanged
Definition: ntv2virtualregisters.h:487
kVRegNTV2VPIDColorimetry4
@ kVRegNTV2VPIDColorimetry4
Definition: ntv2virtualregisters.h:512
kRegDMA4LocalAddr
@ kRegDMA4LocalAddr
Definition: ntv2publicinterface.h:148
kVRegNTV2VPIDTransferCharacteristics3
@ kVRegNTV2VPIDTransferCharacteristics3
Definition: ntv2virtualregisters.h:507
regAuxExtField1EndAddress
@ regAuxExtField1EndAddress
Definition: ntv2publicinterface.h:5277
RegisterExpert::DisposeInstance
static bool DisposeInstance(void)
Definition: ntv2registerexpert.cpp:4609
kRegRXSDI5Status
@ kRegRXSDI5Status
Definition: ntv2publicinterface.h:738
kRegAudDetect2
@ kRegAudDetect2
Definition: ntv2publicinterface.h:405
NTV2_XptFrameBuffer3DS2Input
@ NTV2_XptFrameBuffer3DS2Input
Definition: ntv2enums.h:2729
kColorCorrectionLUTOffset_Green
#define kColorCorrectionLUTOffset_Green
Definition: ntv2publicinterface.h:4173
kVRegNTV2VPIDTransferCharacteristics8
@ kVRegNTV2VPIDTransferCharacteristics8
Definition: ntv2virtualregisters.h:527
kRegHDMIHDRGreenPrimary
@ kRegHDMIHDRGreenPrimary
Definition: ntv2publicinterface.h:465
kRegHDMIV2HActive
@ kRegHDMIV2HActive
Definition: ntv2publicinterface.h:510
kRegOutputTimingControlch3
@ kRegOutputTimingControlch3
Definition: ntv2publicinterface.h:651
kRegSDIOut3VPIDB
@ kRegSDIOut3VPIDB
Definition: ntv2publicinterface.h:395
kRegMaskAnalogIOControl_58
@ kRegMaskAnalogIOControl_58
Definition: ntv2publicinterface.h:1211
NTV2_XptLUT3Input
@ NTV2_XptLUT3Input
Definition: ntv2enums.h:2758
kRegAud1Counter
@ kRegAud1Counter
Definition: ntv2publicinterface.h:131
kVRegDriverType
@ kVRegDriverType
Definition: ntv2virtualregisters.h:38
regAncExtField1EndAddress
@ regAncExtField1EndAddress
Definition: ntv2publicinterface.h:5172
regAncExtTotalStatus
@ regAncExtTotalStatus
Definition: ntv2publicinterface.h:5176
kVRegAudioCapMixerSourceAux2Gain
@ kVRegAudioCapMixerSourceAux2Gain
Definition: ntv2virtualregisters.h:481
kVRegSDIOutput1Stereo3DMode
@ kVRegSDIOutput1Stereo3DMode
Definition: ntv2virtualregisters.h:148
ntv2endian.h
Defines a number of handy byte-swapping macros.
kVRegIsDefaultDevice
@ kVRegIsDefaultDevice
Definition: ntv2virtualregisters.h:166
regNTV4FS_RasterROIFillAlpha
@ regNTV4FS_RasterROIFillAlpha
Definition: ntv2registerexpert.cpp:68
kRegShiftLUT5Select
@ kRegShiftLUT5Select
Definition: ntv2publicinterface.h:2455
kVRegCaptureReferenceSelect
@ kVRegCaptureReferenceSelect
Definition: ntv2virtualregisters.h:122
NTV2DeviceGetLUTVersion
ULWord NTV2DeviceGetLUTVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8912
kRegMaskAudioMixerPresent
@ kRegMaskAudioMixerPresent
Definition: ntv2publicinterface.h:1195
kRegSDIIn5VPIDA
@ kRegSDIIn5VPIDA
Definition: ntv2publicinterface.h:566
kRegXptSelectGroup30
@ kRegXptSelectGroup30
Definition: ntv2publicinterface.h:557
EnabDisab
#define EnabDisab(__x__)
Definition: ntv2registerexpert.h:28
kRegMaskVidProcBGMatteEnable
@ kRegMaskVidProcBGMatteEnable
Definition: ntv2publicinterface.h:1271
kVRegThermalSamplingRate
@ kVRegThermalSamplingRate
Definition: ntv2virtualregisters.h:343
kRegClass_Channel5
#define kRegClass_Channel5
Definition: ntv2registerexpert.h:48
kRegMaskAudioMixerAux1InputEnable
@ kRegMaskAudioMixerAux1InputEnable
Definition: ntv2publicinterface.h:2162
kRegMaskGeometry
@ kRegMaskGeometry
Definition: ntv2publicinterface.h:1162
kVRegBA1MemorySize
@ kVRegBA1MemorySize
Definition: ntv2virtualregisters.h:257
kRegRP188InOut4Bits0_31
@ kRegRP188InOut4Bits0_31
Definition: ntv2publicinterface.h:397
kK2RegShiftDownConvertMode
@ kK2RegShiftDownConvertMode
Definition: ntv2publicinterface.h:2689
regAuxExtTotalFrameLines
@ regAuxExtTotalFrameLines
Definition: ntv2publicinterface.h:5285
kVRegMacKernelModePingLevel
@ kVRegMacKernelModePingLevel
Definition: ntv2virtualregisters.h:243
kRegSDIIn2VPIDA
@ kRegSDIIn2VPIDA
Definition: ntv2publicinterface.h:361
kRegXptSelectGroup8
@ kRegXptSelectGroup8
Definition: ntv2publicinterface.h:284
kRegCS2Coefficients5_6
@ kRegCS2Coefficients5_6
Definition: ntv2publicinterface.h:267
kVRegStrictTiming
@ kVRegStrictTiming
Definition: ntv2virtualregisters.h:36
kRegCS4Coefficients9_10
@ kRegCS4Coefficients9_10
Definition: ntv2publicinterface.h:425
ThruDeviceOrBypassed
#define ThruDeviceOrBypassed(__x__)
Definition: ntv2registerexpert.h:34
kVRegDualStreamTransportType
@ kVRegDualStreamTransportType
Definition: ntv2virtualregisters.h:115
kVRegTxcSfp1RemotePort4
@ kVRegTxcSfp1RemotePort4
Definition: ntv2virtualregisters.h:407
kRegLEDSDI1Control
@ kRegLEDSDI1Control
Definition: ntv2publicinterface.h:1071
kRegMaskAud7PlayCapMode
@ kRegMaskAud7PlayCapMode
Definition: ntv2publicinterface.h:1187
sMasks
static const ULWord sMasks[]
Definition: ntv2regroute.cpp:26
kRegMaskSmpte372Enable
@ kRegMaskSmpte372Enable
Definition: ntv2publicinterface.h:1166
kRegEnhancedCSC1KeyMode
@ kRegEnhancedCSC1KeyMode
Definition: ntv2publicinterface.h:868
kRegHDMIHDRBluePrimary
@ kRegHDMIHDRBluePrimary
Definition: ntv2publicinterface.h:466
kRegXptSelectGroup34
@ kRegXptSelectGroup34
Definition: ntv2publicinterface.h:686
kRegGlobalControlCh4
@ kRegGlobalControlCh4
Definition: ntv2publicinterface.h:529
kVReg2022_7Enable
@ kVReg2022_7Enable
Definition: ntv2virtualregisters.h:451
CNTV2RegisterExpert::IsRegisterInClass
static bool IsRegisterInClass(const uint32_t inRegNum, const std::string &inClassName)
Definition: ntv2registerexpert.cpp:4663
kRegMaskBOBGPIIn4InterruptControl
@ kRegMaskBOBGPIIn4InterruptControl
Definition: ntv2publicinterface.h:2226
NTV2DeviceID
NTV2DeviceID
Identifies a specific AJA NTV2 device model number. The NTV2DeviceID is actually the PROM part number...
Definition: ntv2enums.h:20
kVRegTimeStampLastInput3VerticalHi
@ kVRegTimeStampLastInput3VerticalHi
Definition: ntv2virtualregisters.h:268
NTV2_Xpt3DLUT1Input
@ NTV2_Xpt3DLUT1Input
New in SDK 16.0.
Definition: ntv2enums.h:2842
regAncExtField1AnalogCFilter
@ regAncExtField1AnalogCFilter
Definition: ntv2publicinterface.h:5192
DEC0N
#define DEC0N(__x__, __n__)
Definition: ntv2publicinterface.h:5608
kVRegNTV2VPIDColorimetry2
@ kVRegNTV2VPIDColorimetry2
Definition: ntv2virtualregisters.h:504
NTV2_Xpt4KDCQ2Input
@ NTV2_Xpt4KDCQ2Input
Definition: ntv2enums.h:2830
kVRegRxcSfp2SourceIp1
@ kVRegRxcSfp2SourceIp1
Definition: ntv2virtualregisters.h:372
kColorCorrectionLUTOffset_Blue
#define kColorCorrectionLUTOffset_Blue
Definition: ntv2publicinterface.h:4174
kVRegSDIInput1FormatSelect
@ kVRegSDIInput1FormatSelect
Definition: ntv2virtualregisters.h:126
kRegMaskRP188ModeCh5
@ kRegMaskRP188ModeCh5
Definition: ntv2publicinterface.h:1203
kRegClass_SDIError
#define kRegClass_SDIError
Definition: ntv2registerexpert.h:65
kVRegRelativeVideoPlaybackDelay
@ kVRegRelativeVideoPlaybackDelay
Definition: ntv2virtualregisters.h:33
kRegMaskBOBAnalogLevelControl
@ kRegMaskBOBAnalogLevelControl
Definition: ntv2publicinterface.h:2234
kRegAud3SourceSelect
@ kRegAud3SourceSelect
Definition: ntv2publicinterface.h:403
kRegMask425FB12
@ kRegMask425FB12
Definition: ntv2publicinterface.h:1197
kRegMaskElectroOpticalTransferFunction
@ kRegMaskElectroOpticalTransferFunction
Definition: ntv2publicinterface.h:2137
kVRegDefaultInput
@ kVRegDefaultInput
Definition: ntv2virtualregisters.h:233
kRegAudioOutputSourceMap
@ kRegAudioOutputSourceMap
Definition: ntv2publicinterface.h:313
kRegClass_Channel2
#define kRegClass_Channel2
Definition: ntv2registerexpert.h:45
NTV2_WIDGET_INVALID
@ NTV2_WIDGET_INVALID
Definition: ntv2enums.h:2999
regAuxExtField2StartAddress
@ regAuxExtField2StartAddress
Definition: ntv2publicinterface.h:5278
kRegEnhancedCSC1Mode
@ kRegEnhancedCSC1Mode
Definition: ntv2publicinterface.h:854
kRegRP188InOut5DBB
@ kRegRP188InOut5DBB
Definition: ntv2publicinterface.h:479
kRegHDMIV2i2c2Data
@ kRegHDMIV2i2c2Data
Definition: ntv2publicinterface.h:522
NTV2_XptMixer3FGKeyInput
@ NTV2_XptMixer3FGKeyInput
Definition: ntv2enums.h:2818
kRegMaskBOBADAV801DIRLocked
@ kRegMaskBOBADAV801DIRLocked
Definition: ntv2publicinterface.h:2216
regAncExtIgnorePacketReg_5_6_7_8
@ regAncExtIgnorePacketReg_5_6_7_8
Definition: ntv2publicinterface.h:5184
kRegGlobalControlCh7
@ kRegGlobalControlCh7
Definition: ntv2publicinterface.h:532
kRegClass_Interrupt
#define kRegClass_Interrupt
Definition: ntv2registerexpert.h:58
kRegMaskBOBGPIIn1Data
@ kRegMaskBOBGPIIn1Data
Definition: ntv2publicinterface.h:2218
kRegShiftCC5OutputBankSelect
@ kRegShiftCC5OutputBankSelect
Definition: ntv2publicinterface.h:2454
kRegRP188InOut3Bits0_31
@ kRegRP188InOut3Bits0_31
Definition: ntv2publicinterface.h:392
kK2RegMaskDownConvertMode
@ kK2RegMaskDownConvertMode
Definition: ntv2publicinterface.h:1612
kRegMaskPWMFanStatus
@ kRegMaskPWMFanStatus
Definition: ntv2publicinterface.h:2212
regAncExtFieldCutoffLine
@ regAncExtFieldCutoffLine
Definition: ntv2publicinterface.h:5175
NTV2_XptSDIOut7Input
@ NTV2_XptSDIOut7Input
Definition: ntv2enums.h:2780
kVRegTimeStampLastInput7VerticalHi
@ kVRegTimeStampLastInput7VerticalHi
Definition: ntv2virtualregisters.h:276
kVRegTxc_2EncodeAudioChannels1
@ kVRegTxc_2EncodeAudioChannels1
Definition: ntv2virtualregisters.h:432
kRegDMA4XferCount
@ kRegDMA4XferCount
Definition: ntv2publicinterface.h:149
kVRegFlashProgramKey
@ kVRegFlashProgramKey
Definition: ntv2virtualregisters.h:35
kVRegProcAmpStandardDefSaturation
@ kVRegProcAmpStandardDefSaturation
Definition: ntv2virtualregisters.h:199
NTV2_Xpt4KDCQ4Input
@ NTV2_Xpt4KDCQ4Input
Definition: ntv2enums.h:2832
kVRegDmaHardwareRateH2C3
@ kVRegDmaHardwareRateH2C3
Definition: ntv2virtualregisters.h:603
kRegCh8OutputFrame
@ kRegCh8OutputFrame
Definition: ntv2publicinterface.h:551
kRegSDIIn7VPIDB
@ kRegSDIIn7VPIDB
Definition: ntv2publicinterface.h:580
kVRegTxc_2EncodeVideoPid1
@ kVRegTxc_2EncodeVideoPid1
Definition: ntv2virtualregisters.h:435
regNTV4FS_RasterOffsetAlpha
@ regNTV4FS_RasterOffsetAlpha
Definition: ntv2registerexpert.cpp:76
regNTV4FS_FIRST
@ regNTV4FS_FIRST
Definition: ntv2registerexpert.cpp:53
kVRegChannelCrosspointLast
@ kVRegChannelCrosspointLast
Definition: ntv2virtualregisters.h:327
kRegMaskCC5OutputBankSelect
@ kRegMaskCC5OutputBankSelect
Definition: ntv2publicinterface.h:1370
kRegCS4Coefficients3_4
@ kRegCS4Coefficients3_4
Definition: ntv2publicinterface.h:422
kRegMaskQuadQuadMode
@ kRegMaskQuadQuadMode
Definition: ntv2publicinterface.h:1212
kVRegTxc_2EncodeProgramPid1
@ kVRegTxc_2EncodeProgramPid1
Definition: ntv2virtualregisters.h:434
kVRegHDMIOutColorSpaceModeStatus
@ kVRegHDMIOutColorSpaceModeStatus
Definition: ntv2virtualregisters.h:164
kRegMaskCC4OutputBankSelect
@ kRegMaskCC4OutputBankSelect
Definition: ntv2publicinterface.h:1374
kRegRXSDI1Status
@ kRegRXSDI1Status
Definition: ntv2publicinterface.h:702
kRegAudioMixerAux2GainCh1
@ kRegAudioMixerAux2GainCh1
Definition: ntv2publicinterface.h:797
kVRegTxc_2EncodeProgramPid2
@ kVRegTxc_2EncodeProgramPid2
Definition: ntv2virtualregisters.h:446
kVRegDisableAutoVPID
@ kVRegDisableAutoVPID
Definition: ntv2virtualregisters.h:489
NTV2DeviceGetNumCSCs
UWord NTV2DeviceGetNumCSCs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:10277
kVRegProcAmpSDRegsInitialized
@ kVRegProcAmpSDRegsInitialized
Definition: ntv2virtualregisters.h:196
kVRegTimeCodeCh5Delay
@ kVRegTimeCodeCh5Delay
Definition: ntv2virtualregisters.h:99
kVRegInputChangedCount
@ kVRegInputChangedCount
Definition: ntv2virtualregisters.h:190
NTV2_XptHDMIOutQ3Input
@ NTV2_XptHDMIOutQ3Input
Definition: ntv2enums.h:2827
kVRegRxcSfp1DestIp1
@ kVRegRxcSfp1DestIp1
Definition: ntv2virtualregisters.h:367
kVRegSDIOutput2RGBRange
@ kVRegSDIOutput2RGBRange
Definition: ntv2virtualregisters.h:147
kRegAud7InputLastAddr
@ kRegAud7InputLastAddr
Definition: ntv2publicinterface.h:614
regNTV4FS_InputSourceSelect
@ regNTV4FS_InputSourceSelect
Definition: ntv2registerexpert.cpp:77
kVRegSyncChannel
@ kVRegSyncChannel
Definition: ntv2virtualregisters.h:88
NTV2_XptSDIOut2InputDS2
@ NTV2_XptSDIOut2InputDS2
Definition: ntv2enums.h:2771
kRegShiftCC5HostAccessBankSelect
@ kRegShiftCC5HostAccessBankSelect
Definition: ntv2publicinterface.h:2453
kRegDMA3NextDescHigh
@ kRegDMA3NextDescHigh
Definition: ntv2publicinterface.h:212
kRegVidProc3Control
@ kRegVidProc3Control
Definition: ntv2publicinterface.h:658
NTV2_XptFrameBuffer4Input
@ NTV2_XptFrameBuffer4Input
Definition: ntv2enums.h:2730
kRegEnhancedCSC1KeyGain
@ kRegEnhancedCSC1KeyGain
Definition: ntv2publicinterface.h:870
kRegMaskQuadQuadSquaresMode
@ kRegMaskQuadQuadSquaresMode
Definition: ntv2publicinterface.h:1214
kVRegMacUserModePingLevel
@ kVRegMacUserModePingLevel
Definition: ntv2virtualregisters.h:242
kVRegRxcSfp1RxMatch2
@ kVRegRxcSfp1RxMatch2
Definition: ntv2virtualregisters.h:381
kRegHDMIV2HSyncDurationAndBackPorch
@ kRegHDMIV2HSyncDurationAndBackPorch
Definition: ntv2publicinterface.h:509
kVRegRxcSfp2SourceIp2
@ kVRegRxcSfp2SourceIp2
Definition: ntv2virtualregisters.h:388
kVRegTimeStampLastOutput3VerticalHi
@ kVRegTimeStampLastOutput3VerticalHi
Definition: ntv2virtualregisters.h:284
NTV2_XptSDIOut8InputDS2
@ NTV2_XptSDIOut8InputDS2
Definition: ntv2enums.h:2783
NTV2InputXptID
enum NTV2InputCrosspointID NTV2InputXptID
kRegAudioMixerMainOutputLevelsPair0
@ kRegAudioMixerMainOutputLevelsPair0
Definition: ntv2publicinterface.h:816
NTV2_XptFrameBuffer3Input
@ NTV2_XptFrameBuffer3Input
Definition: ntv2enums.h:2728
kRegClass_WriteOnly
#define kRegClass_WriteOnly
Definition: ntv2registerexpert.h:72
NTV2PixelFormat
NTV2FrameBufferFormat NTV2PixelFormat
An alias for NTV2FrameBufferFormat.
Definition: ntv2enums.h:251
kRegMaskCC5HostAccessBankSelect
@ kRegMaskCC5HostAccessBankSelect
Definition: ntv2publicinterface.h:1369
kRegLTC7EmbeddedBits0_31
@ kRegLTC7EmbeddedBits0_31
Definition: ntv2publicinterface.h:586
NTV2_XptDualLinkOut5Input
@ NTV2_XptDualLinkOut5Input
Definition: ntv2enums.h:2804
kRegAud1Delay
@ kRegAud1Delay
Definition: ntv2publicinterface.h:122
kRegXptSelectGroup3
@ kRegXptSelectGroup3
Definition: ntv2publicinterface.h:254
kK2RegMaskIsoConvertMode
@ kK2RegMaskIsoConvertMode
Definition: ntv2publicinterface.h:1617
NTV2_XptSDIOut4Input
@ NTV2_XptSDIOut4Input
Definition: ntv2enums.h:2774
kRegAudioMixerMainOutputLevelsPair6
@ kRegAudioMixerMainOutputLevelsPair6
Definition: ntv2publicinterface.h:822
kRegAud7OutputLastAddr
@ kRegAud7OutputLastAddr
Definition: ntv2publicinterface.h:613
NTV2_XptMixer4BGVidInput
@ NTV2_XptMixer4BGVidInput
Definition: ntv2enums.h:2821
regNTV4FS_LineLengthPitch
@ regNTV4FS_LineLengthPitch
Definition: ntv2registerexpert.cpp:54
kRegXptSelectGroup27
@ kRegXptSelectGroup27
Definition: ntv2publicinterface.h:562
ntv2debug.h
kVRegRGB10Range
@ kVRegRGB10Range
Definition: ntv2virtualregisters.h:56
kRegMaskFramePulseEnable
@ kRegMaskFramePulseEnable
Definition: ntv2publicinterface.h:1216
kRegMaskCCOutputBankSelect
@ kRegMaskCCOutputBankSelect
Definition: ntv2publicinterface.h:1367
NTV2StringSetConstIter
NTV2StringSet::const_iterator NTV2StringSetConstIter
Definition: ntv2utils.h:1147
kRegLTC2AnalogBits32_63
@ kRegLTC2AnalogBits32_63
Definition: ntv2publicinterface.h:378
NTV2_XptCSC1VidInput
@ NTV2_XptCSC1VidInput
Definition: ntv2enums.h:2740
kRegAud8InputLastAddr
@ kRegAud8InputLastAddr
Definition: ntv2publicinterface.h:619
CNTV2RegisterExpert::Allocate
static bool Allocate(void)
Explicitly allocates the Register Expert singleton.
Definition: ntv2registerexpert.cpp:4618
NTV2_Xpt425Mux3AInput
@ NTV2_Xpt425Mux3AInput
Definition: ntv2enums.h:2837
kRegShiftHDMIHDRGreenPrimaryY
@ kRegShiftHDMIHDRGreenPrimaryY
Definition: ntv2publicinterface.h:3183
CNTV2RegisterExpert::GetRegistersWithName
static NTV2RegNumSet GetRegistersWithName(const std::string &inName, const int inSearchStyle=EXACTMATCH)
Definition: ntv2registerexpert.cpp:4705
kRegClass_NTV4FrameStore
#define kRegClass_NTV4FrameStore
Definition: ntv2registerexpert.h:74
kVRegGlobalAudioPlaybackMode
@ kVRegGlobalAudioPlaybackMode
Definition: ntv2virtualregisters.h:34
kRegRP188InOut4Bits32_63
@ kRegRP188InOut4Bits32_63
Definition: ntv2publicinterface.h:398
kRegAudioMixerMainInputLevelsPair1
@ kRegAudioMixerMainInputLevelsPair1
Definition: ntv2publicinterface.h:808
kRegLEDClockDivide
@ kRegLEDClockDivide
Definition: ntv2publicinterface.h:1068
kVRegLUT4Type
@ kVRegLUT4Type
Definition: ntv2virtualregisters.h:225
kVRegHDMIInDrmLightLevel2
@ kVRegHDMIInDrmLightLevel2
Definition: ntv2virtualregisters.h:623
kRegClass_VPID
#define kRegClass_VPID
Definition: ntv2registerexpert.h:71
kRegLEDReserved2
@ kRegLEDReserved2
Definition: ntv2publicinterface.h:1069
CNTV2RegisterExpert::GetRegistersForChannel
static NTV2RegNumSet GetRegistersForChannel(const NTV2Channel inChannel)
Definition: ntv2registerexpert.cpp:4691
NTV2_XptCSC4KeyInput
@ NTV2_XptCSC4KeyInput
Definition: ntv2enums.h:2747
NTV2_XptCSC6KeyInput
@ NTV2_XptCSC6KeyInput
Definition: ntv2enums.h:2751
kVRegDmaHardwareRateC2H3
@ kVRegDmaHardwareRateC2H3
Definition: ntv2virtualregisters.h:601
regAncInsPixelDelay
@ regAncInsPixelDelay
Definition: ntv2publicinterface.h:5210
CNTV2RegisterExpert::IsAllocated
static bool IsAllocated(void)
Definition: ntv2registerexpert.cpp:4625
kVRegSecondaryFormatSelect
@ kVRegSecondaryFormatSelect
Definition: ntv2virtualregisters.h:42
kVRegDmaHardwareRateC2H1
@ kVRegDmaHardwareRateC2H1
Definition: ntv2virtualregisters.h:593
kRegAudioMixerMainInputLevelsPair5
@ kRegAudioMixerMainInputLevelsPair5
Definition: ntv2publicinterface.h:812
kVRegDTVersionDurian
@ kVRegDTVersionDurian
Definition: ntv2virtualregisters.h:74
kVRegHDMIInDrmInfo1
@ kVRegHDMIInDrmInfo1
Definition: ntv2virtualregisters.h:609
nlohmann::json_abiNLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON_v3_11_NLOHMANN_JSON_VERSION_PATCH::detail::void
j template void())
Definition: json.hpp:4893
kVRegDTAudioMux1
@ kVRegDTAudioMux1
Definition: ntv2virtualregisters.h:70
NTV2_XptFrameBuffer7DS2Input
@ NTV2_XptFrameBuffer7DS2Input
Definition: ntv2enums.h:2737
kRegCh2PCIAccessFrame
@ kRegCh2PCIAccessFrame
Definition: ntv2publicinterface.h:108
kRegSDIOut4VPIDB
@ kRegSDIOut4VPIDB
Definition: ntv2publicinterface.h:400
kRegSysmonVccIntDieTemp
@ kRegSysmonVccIntDieTemp
Definition: ntv2publicinterface.h:233
kVRegDefaultVideoOutMode
@ kVRegDefaultVideoOutMode
Definition: ntv2virtualregisters.h:234
NTV2_XptCSC3KeyInput
@ NTV2_XptCSC3KeyInput
Definition: ntv2enums.h:2745
kVRegHDMIInDrmBluePrimary2
@ kVRegHDMIInDrmBluePrimary2
Definition: ntv2virtualregisters.h:619
NTV2HDMIOutputStatus
Reports HDMI output status information.
Definition: ntv2publicinterface.h:6937
regNTV4FS_ROIF2VHOffsets
@ regNTV4FS_ROIF2VHOffsets
Definition: ntv2registerexpert.cpp:59
NTV2DeviceCanDo425Mux
bool NTV2DeviceCanDo425Mux(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:753
kVRegHdrInTransferCh1
@ kVRegHdrInTransferCh1
Definition: ntv2virtualregisters.h:559
kRegXptSelectGroup28
@ kRegXptSelectGroup28
Definition: ntv2publicinterface.h:563
kRegShiftFrameRateHiBit
@ kRegShiftFrameRateHiBit
Definition: ntv2publicinterface.h:2246
kVRegAudioMixerOutputEnable
@ kVRegAudioMixerOutputEnable
Definition: ntv2virtualregisters.h:587
regAuxExtField1StartAddress
@ regAuxExtField1StartAddress
Definition: ntv2publicinterface.h:5276
NTV2_Xpt425Mux2BInput
@ NTV2_Xpt425Mux2BInput
Definition: ntv2enums.h:2836
kVRegRxcPlayoutDelay1
@ kVRegRxcPlayoutDelay1
Definition: ntv2virtualregisters.h:378
kVRegHDMIInDrmMasteringLuminence1
@ kVRegHDMIInDrmMasteringLuminence1
Definition: ntv2virtualregisters.h:614
kRegClass_Channel1
#define kRegClass_Channel1
Definition: ntv2registerexpert.h:44
NTV2FrameRate
NTV2FrameRate
Identifies a particular video frame rate.
Definition: ntv2enums.h:399
kVRegFlashSize
@ kVRegFlashSize
Definition: ntv2virtualregisters.h:300
kVRegNTV2VPIDTransferCharacteristics2
@ kVRegNTV2VPIDTransferCharacteristics2
Definition: ntv2virtualregisters.h:503
kVRegNTV2VPIDColorimetry
@ kVRegNTV2VPIDColorimetry
Definition: ntv2virtualregisters.h:500
NTV2_IS_VALID_InputCrosspointID
#define NTV2_IS_VALID_InputCrosspointID(__s__)
Definition: ntv2enums.h:2869
kVRegHDRInOverrideState
@ kVRegHDRInOverrideState
Definition: ntv2virtualregisters.h:573
kIncludeOtherRegs_VRegs
#define kIncludeOtherRegs_VRegs
Definition: ntv2registerexpert.h:78
kK2RegMaskConverterOutRate
@ kK2RegMaskConverterOutRate
Definition: ntv2publicinterface.h:1610
NTV2AudioChannelQuadToString
std::string NTV2AudioChannelQuadToString(const NTV2Audio4ChannelSelect inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6490
kVRegNTV2VPIDRGBRange1
@ kVRegNTV2VPIDRGBRange1
Definition: ntv2virtualregisters.h:575
NTV2_XptLUT2Input
@ NTV2_XptLUT2Input
Definition: ntv2enums.h:2757
kVRegMonAncField2Offset
@ kVRegMonAncField2Offset
Monitor Anc Field2 byte offset from end of frame buffer (IoIP only, GUMP)
Definition: ntv2virtualregisters.h:332
kRegLTC6EmbeddedBits32_63
@ kRegLTC6EmbeddedBits32_63
Definition: ntv2publicinterface.h:577
kRegDMA4NextDescHigh
@ kRegDMA4NextDescHigh
Definition: ntv2publicinterface.h:214
NTV2_XptDualLinkIn7DSInput
@ NTV2_XptDualLinkIn7DSInput
Definition: ntv2enums.h:2797
NTV2_XptFrameBuffer6Input
@ NTV2_XptFrameBuffer6Input
Definition: ntv2enums.h:2734
kVRegUseQTTimecode
@ kVRegUseQTTimecode
Definition: ntv2virtualregisters.h:160
NTV2_Xpt4KDCQ3Input
@ NTV2_Xpt4KDCQ3Input
Definition: ntv2enums.h:2831
NTV2_XptDualLinkIn3Input
@ NTV2_XptDualLinkIn3Input
Definition: ntv2enums.h:2788
kVRegDmaHardwareRateH2C1
@ kVRegDmaHardwareRateH2C1
Definition: ntv2virtualregisters.h:595
kRegShiftHDMIHDRWhitePointX
@ kRegShiftHDMIHDRWhitePointX
Definition: ntv2publicinterface.h:3188
kRegAud5Control
@ kRegAud5Control
Definition: ntv2publicinterface.h:601
kRegMaskHDMIHDRNonContantLuminance
@ kRegMaskHDMIHDRNonContantLuminance
Definition: ntv2publicinterface.h:2134
kVRegHDMIInDrmGreenPrimary1
@ kVRegHDMIInDrmGreenPrimary1
Definition: ntv2virtualregisters.h:610
NTV2RegNumSet
NTV2RegisterNumberSet NTV2RegNumSet
A set of distinct NTV2RegisterNumbers.
Definition: ntv2publicinterface.h:7415
ntv2signalrouter.h
Declares CNTV2SignalRouter class.
RegisterExpert::GetRegistersWithName
NTV2RegNumSet GetRegistersWithName(const string &inName, const int inMatchStyle=EXACTMATCH) const
Definition: ntv2registerexpert.cpp:2016
kVRegProcAmpHighDefHue
@ kVRegProcAmpHighDefHue
Definition: ntv2virtualregisters.h:210
kRegAud3InputLastAddr
@ kRegAud3InputLastAddr
Definition: ntv2publicinterface.h:407
kVRegAncField2Offset
@ kVRegAncField2Offset
Anc Field2 byte offset from end of frame buffer (GUMP on all boards except RTP for SMPTE2022/IP)
Definition: ntv2virtualregisters.h:336
kVRegAudioGainDisable
@ kVRegAudioGainDisable
Definition: ntv2virtualregisters.h:152
kVRegHdrTransferCh1
@ kVRegHdrTransferCh1
Definition: ntv2virtualregisters.h:536
kRegAudioMixerAux2GainCh2
@ kRegAudioMixerAux2GainCh2
Definition: ntv2publicinterface.h:801
NTV2BitfileHeaderParser::GetDesignVersion
static ULWord GetDesignVersion(const ULWord userID)
Definition: ntv2bitfile.h:55
NTV2DeviceGetNumSerialPorts
UWord NTV2DeviceGetNumSerialPorts(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11927
kVRegHDMIInDrmGreenPrimary2
@ kVRegHDMIInDrmGreenPrimary2
Definition: ntv2virtualregisters.h:618
kRegEnhancedCSC1CoeffC2
@ kRegEnhancedCSC1CoeffC2
Definition: ntv2publicinterface.h:865
kRegSDIIn6VPIDA
@ kRegSDIIn6VPIDA
Definition: ntv2publicinterface.h:569
regNTV4FS_REGISTER_COUNT
@ regNTV4FS_REGISTER_COUNT
Definition: ntv2registerexpert.cpp:79
kRegAud5InputLastAddr
@ kRegAud5InputLastAddr
Definition: ntv2publicinterface.h:604
kRegSDIOut6VPIDA
@ kRegSDIOut6VPIDA
Definition: ntv2publicinterface.h:571
kVRegKIPDecCfgError
@ kVRegKIPDecCfgError
Definition: ntv2virtualregisters.h:457
kRegRP188InOut6Bits32_63
@ kRegRP188InOut6Bits32_63
Definition: ntv2publicinterface.h:574
NTV2_XptMixer4FGVidInput
@ NTV2_XptMixer4FGVidInput
Definition: ntv2enums.h:2823
kRegCh3Control
@ kRegCh3Control
Definition: ntv2publicinterface.h:380
gRegExpertGuardMutex
static AJALock gRegExpertGuardMutex
Definition: ntv2registerexpert.cpp:4598
NTV2_XptDualLinkIn7Input
@ NTV2_XptDualLinkIn7Input
Definition: ntv2enums.h:2796
kVRegTestPatternChoice
@ kVRegTestPatternChoice
Definition: ntv2virtualregisters.h:230
kVRegAudioOutputToneSelect
@ kVRegAudioOutputToneSelect
Definition: ntv2virtualregisters.h:626
kVRegReleaseApplication
@ kVRegReleaseApplication
Definition: ntv2virtualregisters.h:185
kRegMaskSDIRelayPosition34
@ kRegMaskSDIRelayPosition34
Definition: ntv2publicinterface.h:2018
kRegAud8Delay
@ kRegAud8Delay
Definition: ntv2publicinterface.h:671
NTV2DriverVersionDecode_Point
#define NTV2DriverVersionDecode_Point(__vers__)
Definition: ntv2publicinterface.h:5377
regNTV4FS_ROIF1VHOffsets
@ regNTV4FS_ROIF1VHOffsets
Definition: ntv2registerexpert.cpp:58
kRegClass_Mixer
#define kRegClass_Mixer
Definition: ntv2registerexpert.h:61
kRegMaskBOBAnalogInputSelect
@ kRegMaskBOBAnalogInputSelect
Definition: ntv2publicinterface.h:2235
kVRegTimeStampLastOutput2VerticalHi
@ kVRegTimeStampLastOutput2VerticalHi
Definition: ntv2virtualregisters.h:281
kRegMaskSDIWatchdogEnable12
@ kRegMaskSDIWatchdogEnable12
Definition: ntv2publicinterface.h:2015
kRegOutputTimingControlch5
@ kRegOutputTimingControlch5
Definition: ntv2publicinterface.h:653
NTV2_XptLUT1Input
@ NTV2_XptLUT1Input
Definition: ntv2enums.h:2756
regAncExt_LAST
@ regAncExt_LAST
Definition: ntv2publicinterface.h:5200
kRegCS8Coefficients7_8
@ kRegCS8Coefficients7_8
Definition: ntv2publicinterface.h:643
regNTV4FS_F2ActiveLines
@ regNTV4FS_F2ActiveLines
Definition: ntv2registerexpert.cpp:63
kVRegNTV2VPIDRGBRange2
@ kVRegNTV2VPIDRGBRange2
Definition: ntv2virtualregisters.h:576
NTV2DeviceGetHDMIVersion
ULWord NTV2DeviceGetHDMIVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8821
kRegCh2Control
@ kRegCh2Control
Definition: ntv2publicinterface.h:107
kVRegHdrInBlueYCh1
@ kVRegHdrInBlueYCh1
Definition: ntv2virtualregisters.h:564
kRegHDMIOutControl
@ kRegHDMIOutControl
Definition: ntv2publicinterface.h:240
regAuxExtPacketMask1
@ regAuxExtPacketMask1
Definition: ntv2publicinterface.h:5289
kVRegAdvancedIndexing
@ kVRegAdvancedIndexing
Definition: ntv2virtualregisters.h:266
kRegLTC3EmbeddedBits0_31
@ kRegLTC3EmbeddedBits0_31
Definition: ntv2publicinterface.h:446
kVRegTimeCodeCh2Delay
@ kVRegTimeCodeCh2Delay
Definition: ntv2virtualregisters.h:92
kRegMaskHDMIHDRDolbyVisionEnable
@ kRegMaskHDMIHDRDolbyVisionEnable
Definition: ntv2publicinterface.h:2135
kVRegRxcSfp1Vlan2
@ kVRegRxcSfp1Vlan2
Definition: ntv2virtualregisters.h:386
kRegClass_Timecode
#define kRegClass_Timecode
Definition: ntv2registerexpert.h:67
NTV2DeviceGetUFCVersion
ULWord NTV2DeviceGetUFCVersion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12564
kVRegMailBoxAbort
@ kVRegMailBoxAbort
Definition: ntv2virtualregisters.h:414
PresNotPres
#define PresNotPres(__x__)
Definition: ntv2registerexpert.h:33
kRegMaskVUMeterSelect
@ kRegMaskVUMeterSelect
Definition: ntv2publicinterface.h:1215
kVRegRxcSfp2DestPort2
@ kVRegRxcSfp2DestPort2
Definition: ntv2virtualregisters.h:391
kVRegEFTNeedsUpdating
@ kVRegEFTNeedsUpdating
Definition: ntv2virtualregisters.h:308
kVRegTimeStampLastOutput8VerticalLo
@ kVRegTimeStampLastOutput8VerticalLo
Definition: ntv2virtualregisters.h:295
kVRegTimeStampLastOutput6VerticalLo
@ kVRegTimeStampLastOutput6VerticalLo
Definition: ntv2virtualregisters.h:291
kRegHDMIHDRMasteringLuminence
@ kRegHDMIHDRMasteringLuminence
Definition: ntv2publicinterface.h:469
kVRegAudioInputDelay
@ kVRegAudioInputDelay
Definition: ntv2virtualregisters.h:157
kRegRXSDIFreeRunningClockHigh
@ kRegRXSDIFreeRunningClockHigh
Definition: ntv2publicinterface.h:775
kVRegLUT2Type
@ kVRegLUT2Type
Definition: ntv2virtualregisters.h:223
kVRegUserColorimetry
@ kVRegUserColorimetry
Definition: ntv2virtualregisters.h:531
kVRegAudioCapMixerSourceAux1Enable
@ kVRegAudioCapMixerSourceAux1Enable
Definition: ntv2virtualregisters.h:477
kVRegNTV2VPIDColorimetry6
@ kVRegNTV2VPIDColorimetry6
Definition: ntv2virtualregisters.h:520
kVRegNTV2VPIDLuminance5
@ kVRegNTV2VPIDLuminance5
Definition: ntv2virtualregisters.h:517
kRegCS2Coefficients1_2
@ kRegCS2Coefficients1_2
Definition: ntv2publicinterface.h:265
kRegGlobalControlCh8
@ kRegGlobalControlCh8
Definition: ntv2publicinterface.h:533
kVRegRxcSfp2DestIp1
@ kVRegRxcSfp2DestIp1
Definition: ntv2virtualregisters.h:373
kRegMaskBOBGPIIn2InterruptControl
@ kRegMaskBOBGPIIn2InterruptControl
Definition: ntv2publicinterface.h:2224
kRegMaskSDIRelayControl34
@ kRegMaskSDIRelayControl34
Definition: ntv2publicinterface.h:2014
kVRegAudioSyncTolerance
@ kVRegAudioSyncTolerance
Definition: ntv2virtualregisters.h:86
OnOff
#define OnOff(__x__)
Definition: ntv2registerexpert.h:26
regAncInsField1StartAddr
@ regAncInsField1StartAddr
Definition: ntv2publicinterface.h:5208
kRegMaskAudioMixerInputLeftLevel
@ kRegMaskAudioMixerInputLeftLevel
Definition: ntv2publicinterface.h:2186
kVRegForceApplicationPID
@ kVRegForceApplicationPID
Definition: ntv2virtualregisters.h:186
kVRegVideoFormatCh8
@ kVRegVideoFormatCh8
Definition: ntv2virtualregisters.h:353
kRegMaskQuadMode
@ kRegMaskQuadMode
Definition: ntv2publicinterface.h:1180
kRegHDMIV2I2C1Data
@ kRegHDMIV2I2C1Data
Definition: ntv2publicinterface.h:507
kVRegNTV2VPIDLuminance3
@ kVRegNTV2VPIDLuminance3
Definition: ntv2virtualregisters.h:509
kVRegDSKAudioMode
@ kVRegDSKAudioMode
Definition: ntv2virtualregisters.h:119
aja::lower
std::string & lower(std::string &str)
Definition: common.cpp:436
kVRegRecallRegistersFromRegistry
@ kVRegRecallRegistersFromRegistry
Definition: ntv2virtualregisters.h:63
kVRegTimeCodeCh3Delay
@ kVRegTimeCodeCh3Delay
Definition: ntv2virtualregisters.h:95
NTV2DownConvertMode
NTV2DownConvertMode
Definition: ntv2enums.h:2217
kRegSDIOut3Control
@ kRegSDIOut3Control
Definition: ntv2publicinterface.h:289
kRegCS4Coefficients7_8
@ kRegCS4Coefficients7_8
Definition: ntv2publicinterface.h:424
kVRegEveryFrameTaskFilter
@ kVRegEveryFrameTaskFilter
Definition: ntv2virtualregisters.h:232
kRegAud6SourceSelect
@ kRegAud6SourceSelect
Definition: ntv2publicinterface.h:607
kRegCMWHDMIOut
@ kRegCMWHDMIOut
Definition: ntv2publicinterface.h:1084
NTV2_XptFrameBuffer7Input
@ NTV2_XptFrameBuffer7Input
Definition: ntv2enums.h:2736
kRegMaskHDRStaticMetadataDescriptorID
@ kRegMaskHDRStaticMetadataDescriptorID
Definition: ntv2publicinterface.h:2138
kVRegHDMIInRgbRange
@ kVRegHDMIInRgbRange
Definition: ntv2virtualregisters.h:135
kVRegHdmiHdrOutMode
@ kVRegHdmiHdrOutMode
Definition: ntv2virtualregisters.h:491
NTV2BitfileHeaderParser::GetBitfileID
static ULWord GetBitfileID(const ULWord userID)
Definition: ntv2bitfile.h:56
CNTV2RegisterExpert::GetRegisterClasses
static NTV2StringSet GetRegisterClasses(const uint32_t inRegNum, const bool inRemovePrefix=false)
Definition: ntv2registerexpert.cpp:4677
regAncInsIpChannel
@ regAncInsIpChannel
Definition: ntv2publicinterface.h:5224
kVRegNTV2VPIDLuminance2
@ kVRegNTV2VPIDLuminance2
Definition: ntv2virtualregisters.h:505
NTV2_XptFrameBuffer1Input
@ NTV2_XptFrameBuffer1Input
Definition: ntv2enums.h:2724
kRegSDIWatchdogKick2
@ kRegSDIWatchdogKick2
Definition: ntv2publicinterface.h:442
regAncExtField1AnalogYFilter
@ regAncExtField1AnalogYFilter
Definition: ntv2publicinterface.h:5190
kRegCh5OutputFrame
@ kRegCh5OutputFrame
Definition: ntv2publicinterface.h:536
kRegLEDHDMIInControl
@ kRegLEDHDMIInControl
Definition: ntv2publicinterface.h:1073
kVRegVideoOutPauseMode
@ kVRegVideoOutPauseMode
Definition: ntv2virtualregisters.h:51
kIncludeOtherRegs_XptROM
#define kIncludeOtherRegs_XptROM
Definition: ntv2registerexpert.h:79
RegisterExpert::GetXptRegNumAndMaskIndex
bool GetXptRegNumAndMaskIndex(const NTV2InputCrosspointID inInputXpt, uint32_t &outXptRegNum, uint32_t &outMaskIndex) const
Definition: ntv2registerexpert.cpp:2051
regNTV4FS_RasterSmpteFramePulse
@ regNTV4FS_RasterSmpteFramePulse
Definition: ntv2registerexpert.cpp:72
kRegAud4InputLastAddr
@ kRegAud4InputLastAddr
Definition: ntv2publicinterface.h:409
kVRegFrameBuffer2Stereo3DMode
@ kVRegFrameBuffer2Stereo3DMode
Definition: ntv2virtualregisters.h:151
kRegRP188InOut2Bits0_31_2
@ kRegRP188InOut2Bits0_31_2
Definition: ntv2publicinterface.h:327
kRegRP188InOut8Bits32_63
@ kRegRP188InOut8Bits32_63
Definition: ntv2publicinterface.h:594
kVRegRxcSfp1Vlan1
@ kVRegRxcSfp1Vlan1
Definition: ntv2virtualregisters.h:370
kVRegColorSpaceMode
@ kVRegColorSpaceMode
Definition: ntv2virtualregisters.h:53
NTV2_XptDualLinkIn2Input
@ NTV2_XptDualLinkIn2Input
Definition: ntv2enums.h:2786
NTV2Standard
NTV2Standard
Identifies a particular video standard.
Definition: ntv2enums.h:156
kVRegSDIInput2FormatSelect
@ kVRegSDIInput2FormatSelect
Definition: ntv2virtualregisters.h:127
kVRegTimeStampLastOutputVerticalHi
@ kVRegTimeStampLastOutputVerticalHi
Definition: ntv2virtualregisters.h:79
kK2RegShiftConverterInRate
@ kK2RegShiftConverterInRate
Definition: ntv2publicinterface.h:2691
regAuxExtField2Status
@ regAuxExtField2Status
Definition: ntv2publicinterface.h:5283
kRegVidProc4Control
@ kRegVidProc4Control
Definition: ntv2publicinterface.h:662
kVRegNTV2VPIDColorimetry8
@ kVRegNTV2VPIDColorimetry8
Definition: ntv2virtualregisters.h:528
kRegLTC8EmbeddedBits32_63
@ kRegLTC8EmbeddedBits32_63
Definition: ntv2publicinterface.h:597
kRegFS1ReferenceSelect
@ kRegFS1ReferenceSelect
Definition: ntv2publicinterface.h:201
lock.h
Declares the AJALock class.
kRegMaskFrameFormatHiBit
@ kRegMaskFrameFormatHiBit
Definition: ntv2publicinterface.h:1233
aja::replace
std::string & replace(std::string &str, const std::string &from, const std::string &to)
Definition: common.cpp:110
NTV2AudioChannelPairToString
std::string NTV2AudioChannelPairToString(const NTV2AudioChannelPair inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6478
CNTV2SignalRouter::GetRouteROMInfoFromReg
static bool GetRouteROMInfoFromReg(const ULWord inROMRegNum, const ULWord inROMRegValue, NTV2InputXptID &outInputXpt, NTV2OutputXptIDSet &outOutputXpts, const bool inAppendOutputXpts=false)
Answers with the NTV2InputXptID and NTV2OutputXptIDSet for the given ROM register value.
Definition: ntv2signalrouter.cpp:1029
ULWord
uint32_t ULWord
Definition: ajatypes.h:255
kRegXptSelectGroup2
@ kRegXptSelectGroup2
Definition: ntv2publicinterface.h:253
NTV2DriverVersionDecode_Major
#define NTV2DriverVersionDecode_Major(__vers__)
Definition: ntv2publicinterface.h:5375
NTV2_XptMultiLinkOut1InputDS2
@ NTV2_XptMultiLinkOut1InputDS2
New in SDK 16.0.
Definition: ntv2enums.h:2765
NTV2DeviceCanDoAudioMixer
bool NTV2DeviceCanDoAudioMixer(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:1673
kRegMaskHDMIHDRBluePrimaryX
@ kRegMaskHDMIHDRBluePrimaryX
Definition: ntv2publicinterface.h:2123
kRegShiftAudioMixerInputRightLevel
@ kRegShiftAudioMixerInputRightLevel
Definition: ntv2publicinterface.h:3248
regAncExtField2Status
@ regAncExtField2Status
Definition: ntv2publicinterface.h:5178
kRegRP188InOut5Bits32_63
@ kRegRP188InOut5Bits32_63
Definition: ntv2publicinterface.h:478
kRegRP188InOut2DBB
@ kRegRP188InOut2DBB
Definition: ntv2publicinterface.h:167
kVRegSDIOutput1RGBRange
@ kVRegSDIOutput1RGBRange
Definition: ntv2virtualregisters.h:125
kRegXptSelectGroup10
@ kRegXptSelectGroup10
Definition: ntv2publicinterface.h:374
kRegGlobalControlCh6
@ kRegGlobalControlCh6
Definition: ntv2publicinterface.h:531
kVRegDTFirmware
@ kVRegDTFirmware
Definition: ntv2virtualregisters.h:72
kRegSDIIn5VPIDB
@ kRegSDIIn5VPIDB
Definition: ntv2publicinterface.h:567
kRegMaskFrameSizeSetBySW
@ kRegMaskFrameSizeSetBySW
Definition: ntv2publicinterface.h:1251
NTV2_XptMixer1FGKeyInput
@ NTV2_XptMixer1FGKeyInput
Definition: ntv2enums.h:2810
kVRegVideoFormatCh2
@ kVRegVideoFormatCh2
Definition: ntv2virtualregisters.h:347
regNTV4FS_DisplayHorzPixelsPerLine
@ regNTV4FS_DisplayHorzPixelsPerLine
Definition: ntv2registerexpert.cpp:60
kRegMaskFrameFormat
@ kRegMaskFrameFormat
Definition: ntv2publicinterface.h:1231
kK2RegMaskConverterPulldown
@ kK2RegMaskConverterPulldown
Definition: ntv2publicinterface.h:1615
kVRegAvailable164
@ kVRegAvailable164
Definition: ntv2virtualregisters.h:161
kRegXptSelectGroup12
@ kRegXptSelectGroup12
Definition: ntv2publicinterface.h:316
kRegClass_Input
#define kRegClass_Input
Definition: ntv2registerexpert.h:56
kVRegHDMIInAviInfo1
@ kVRegHDMIInAviInfo1
Definition: ntv2virtualregisters.h:608
kVRegAncField1Offset
@ kVRegAncField1Offset
Anc Field1 byte offset from end of frame buffer (GUMP on all boards except RTP for SMPTE2022/IP)
Definition: ntv2virtualregisters.h:335
kRegMRQ1Control
@ kRegMRQ1Control
Definition: ntv2publicinterface.h:1032
CNTV2RegisterExpert::GetDisplayName
static std::string GetDisplayName(const uint32_t inRegNum)
Definition: ntv2registerexpert.cpp:4639
kVRegTimeStampLastOutput8VerticalHi
@ kVRegTimeStampLastOutput8VerticalHi
Definition: ntv2virtualregisters.h:313
NTV2ReferenceSource
NTV2ReferenceSource
These enum values identify a specific source for the device's (output) reference clock.
Definition: ntv2enums.h:1429
kRegMaskHDMIHDRMinMasteringLuminance
@ kRegMaskHDMIHDRMinMasteringLuminance
Definition: ntv2publicinterface.h:2130
kRegCh4InputFrame
@ kRegCh4InputFrame
Definition: ntv2publicinterface.h:385
NTV2BitfileHeaderParser::GetBitfileVersion
static ULWord GetBitfileVersion(const ULWord userID)
Definition: ntv2bitfile.h:57
NTV2EndianSwap32
#define NTV2EndianSwap32(__val__)
Definition: ntv2endian.h:19
kVRegRxcEnable2
@ kVRegRxcEnable2
Definition: ntv2virtualregisters.h:380
kVRegHDMIInDrmWhitePoint2
@ kVRegHDMIInDrmWhitePoint2
Definition: ntv2virtualregisters.h:621
kVRegSDIOutConfig
@ kVRegSDIOutConfig
Definition: ntv2virtualregisters.h:177
kVRegSoftwareUartFifo
@ kVRegSoftwareUartFifo
Definition: ntv2virtualregisters.h:90
regAncExtAnalogActiveLineLength
@ regAncExtAnalogActiveLineLength
Definition: ntv2publicinterface.h:5199
kVRegLTCOnRefInSelect
@ kVRegLTCOnRefInSelect
Definition: ntv2virtualregisters.h:153
kVRegTimeCodeCh7Delay
@ kVRegTimeCodeCh7Delay
Definition: ntv2virtualregisters.h:103
NTV2_XptSDIOut2Input
@ NTV2_XptSDIOut2Input
Definition: ntv2enums.h:2770
CNTV2VPID
A convenience class that simplifies encoding or decoding the 4-byte VPID payload that can be read or ...
Definition: ntv2vpid.h:23
NTV2DeviceHasBiDirectionalSDI
bool NTV2DeviceHasBiDirectionalSDI(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:6596
kRegAudioMixerMainOutputLevelsPair5
@ kRegAudioMixerMainOutputLevelsPair5
Definition: ntv2publicinterface.h:821
kRegRXSDI7Status
@ kRegRXSDI7Status
Definition: ntv2publicinterface.h:756
regAncExtIgnorePacketReg_17_18_19_20
@ regAncExtIgnorePacketReg_17_18_19_20
Definition: ntv2publicinterface.h:5187
kRegMaskAudioMixerLevelSampleCount
@ kRegMaskAudioMixerLevelSampleCount
Definition: ntv2publicinterface.h:2188
kRegCh4PCIAccessFrame
@ kRegCh4PCIAccessFrame
Definition: ntv2publicinterface.h:413
kRegHDMIV2I2C1Control
@ kRegHDMIV2I2C1Control
Definition: ntv2publicinterface.h:506
kRegMaskSaturationValue
@ kRegMaskSaturationValue
Definition: ntv2publicinterface.h:1366
kVRegHDMIOutputSelect
@ kVRegHDMIOutputSelect
Definition: ntv2virtualregisters.h:228
NTV2_XptIICT1Input
@ NTV2_XptIICT1Input
Definition: ntv2enums.h:2847
RegisterExpert::IsRegisterWriteOnly
bool IsRegisterWriteOnly(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1798
regNTV4FS_ROIF2StartAddr
@ regNTV4FS_ROIF2StartAddr
Definition: ntv2registerexpert.cpp:57
NTV2DeviceCanDoIDSwitch
bool NTV2DeviceCanDoIDSwitch(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:3512
kRegRP188InOut1Bits32_63
@ kRegRP188InOut1Bits32_63
Definition: ntv2publicinterface.h:134
kVRegDSKForegroundMode
@ kVRegDSKForegroundMode
Definition: ntv2virtualregisters.h:120
kRegAud1InputLastAddr
@ kRegAud1InputLastAddr
Definition: ntv2publicinterface.h:130
kRegClass_Channel6
#define kRegClass_Channel6
Definition: ntv2registerexpert.h:49
kRegAud3Control
@ kRegAud3Control
Definition: ntv2publicinterface.h:401
kVRegTimeStampLastInput1VerticalHi
@ kVRegTimeStampLastInput1VerticalHi
Definition: ntv2virtualregisters.h:81
kVRegKIPTxCfgError
@ kVRegKIPTxCfgError
Definition: ntv2virtualregisters.h:455
NTV2DeviceCanDoSDIErrorChecks
bool NTV2DeviceCanDoSDIErrorChecks(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:5126
kVRegTimeStampLastInput2VerticalHi
@ kVRegTimeStampLastInput2VerticalHi
Definition: ntv2virtualregisters.h:83
kRegClass_IP
#define kRegClass_IP
Definition: ntv2registerexpert.h:59
NTV2DeviceSoftwareCanChangeFrameBufferSize
bool NTV2DeviceSoftwareCanChangeFrameBufferSize(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:8365
NTV2DeviceIDToString
std::string NTV2DeviceIDToString(const NTV2DeviceID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:4673
kVRegLUT5Type
@ kVRegLUT5Type
Definition: ntv2virtualregisters.h:237
NTV2_XptWaterMarker1Input
@ NTV2_XptWaterMarker1Input
Definition: ntv2enums.h:2848
kRegSDIIn1VPIDA
@ kRegSDIIn1VPIDA
Definition: ntv2publicinterface.h:311
kRegShiftAudioMixerLevelSampleCount
@ kRegShiftAudioMixerLevelSampleCount
Definition: ntv2publicinterface.h:3249
kRegCh2InputFrame
@ kRegCh2InputFrame
Definition: ntv2publicinterface.h:110
kVRegNumDmaDriverBuffers
@ kVRegNumDmaDriverBuffers
Definition: ntv2virtualregisters.h:259
kRegHDMIV2VerticalMeasurementsField1
@ kRegHDMIV2VerticalMeasurementsField1
Definition: ntv2publicinterface.h:520
kRegMaskCCMode
@ kRegMaskCCMode
Definition: ntv2publicinterface.h:1368
kVRegTimecodeBurnInMode
@ kVRegTimecodeBurnInMode
Definition: ntv2virtualregisters.h:159
kVRegDebugLastFormat
@ kVRegDebugLastFormat
Definition: ntv2virtualregisters.h:109
regAuxExt_LAST
@ regAuxExt_LAST
Definition: ntv2publicinterface.h:5294
kRegMaskHDMIHDRWhitePointX
@ kRegMaskHDMIHDRWhitePointX
Definition: ntv2publicinterface.h:2127
kVRegTxc_2EncodeAudio1Pid2
@ kVRegTxc_2EncodeAudio1Pid2
Definition: ntv2virtualregisters.h:449
kRegDMA2NextDescHigh
@ kRegDMA2NextDescHigh
Definition: ntv2publicinterface.h:210
kVRegTimeStampLastOutput4VerticalHi
@ kVRegTimeStampLastOutput4VerticalHi
Definition: ntv2virtualregisters.h:286
kVRegProcAmpHighDefCbOffset
@ kVRegProcAmpHighDefCbOffset
Definition: ntv2virtualregisters.h:211
kRegCS8Coefficients1_2
@ kRegCS8Coefficients1_2
Definition: ntv2publicinterface.h:640
kRegMaskHDMIHDRRedPrimaryY
@ kRegMaskHDMIHDRRedPrimaryY
Definition: ntv2publicinterface.h:2126
kRegCMW1485Out
@ kRegCMW1485Out
Definition: ntv2publicinterface.h:1080
kVRegBA2MemorySize
@ kVRegBA2MemorySize
Definition: ntv2virtualregisters.h:261
kVRegFramesPerVertical
@ kVRegFramesPerVertical
Definition: ntv2virtualregisters.h:315
regAncInsRtpPayloadID
@ regAncInsRtpPayloadID
Definition: ntv2publicinterface.h:5222
kVRegSDIOutput2Stereo3DMode
@ kVRegSDIOutput2Stereo3DMode
Definition: ntv2virtualregisters.h:149
kVRegNTV2VPIDRGBRange5
@ kVRegNTV2VPIDRGBRange5
Definition: ntv2virtualregisters.h:579
kRegDMA4HostAddr
@ kRegDMA4HostAddr
Definition: ntv2publicinterface.h:147
kRegMaskHDMISampling
@ kRegMaskHDMISampling
Definition: ntv2publicinterface.h:1528
kRegIDSwitch
@ kRegIDSwitch
Definition: ntv2publicinterface.h:1047
kRegCh5PCIAccessFrame
@ kRegCh5PCIAccessFrame
Definition: ntv2publicinterface.h:538
kRegLTC7EmbeddedBits32_63
@ kRegLTC7EmbeddedBits32_63
Definition: ntv2publicinterface.h:587
regAncInsBlankField1CLines
@ regAncInsBlankField1CLines
Definition: ntv2publicinterface.h:5218
kRegMaskFrameRateHiBit
@ kRegMaskFrameRateHiBit
Definition: ntv2publicinterface.h:1161
NTV2IsoConvertModeToString
std::string NTV2IsoConvertModeToString(const NTV2IsoConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6677
kVRegUserDefinedDBB
@ kVRegUserDefinedDBB
Definition: ntv2virtualregisters.h:462
kRegMaskHDMIHDRGreenPrimaryY
@ kRegMaskHDMIHDRGreenPrimaryY
Definition: ntv2publicinterface.h:2122
regAncExtField2EndAddress
@ regAncExtField2EndAddress
Definition: ntv2publicinterface.h:5174
kVRegHdrInLuminanceCh1
@ kVRegHdrInLuminanceCh1
Definition: ntv2virtualregisters.h:560
kRegMaskAud1PlayCapMode
@ kRegMaskAud1PlayCapMode
Definition: ntv2publicinterface.h:1181
NTV2_XptConversionModInput
@ NTV2_XptConversionModInput
Definition: ntv2enums.h:2853
kVRegVideoFormatCh1
@ kVRegVideoFormatCh1
Definition: ntv2virtualregisters.h:346
kRegMaskVidProcVANCShift
@ kRegMaskVidProcVANCShift
Definition: ntv2publicinterface.h:1252
regAuxExtFillData
@ regAuxExtFillData
Definition: ntv2publicinterface.h:5293
kRegSDIIn1VPIDB
@ kRegSDIIn1VPIDB
Definition: ntv2publicinterface.h:312
kVRegSDIInput1RGBRange
@ kVRegSDIInput1RGBRange
Definition: ntv2virtualregisters.h:128
kRegGlobalControl2
@ kRegGlobalControl2
Definition: ntv2publicinterface.h:390
kRegClass_Channel3
#define kRegClass_Channel3
Definition: ntv2registerexpert.h:46
kVRegRxcSfp1DestIp2
@ kVRegRxcSfp1DestIp2
Definition: ntv2virtualregisters.h:383
NTV2_AudioChannel3_4
@ NTV2_AudioChannel3_4
This selects audio channels 3 and 4 (Group 1 channels 3 and 4)
Definition: ntv2enums.h:3090
NTV2StandardToString
std::string NTV2StandardToString(const NTV2Standard inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:6957
kVRegSaveRegistersToRegistry
@ kVRegSaveRegistersToRegistry
Definition: ntv2virtualregisters.h:62
NTV2InputCrosspointIDToString
std::string NTV2InputCrosspointIDToString(const NTV2InputCrosspointID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:5874
kVRegAnalogInBlackLevel
@ kVRegAnalogInBlackLevel
Definition: ntv2virtualregisters.h:137
kRegAudioDetect5678
@ kRegAudioDetect5678
Definition: ntv2publicinterface.h:621
kVRegAudioInputMapSelect
@ kVRegAudioInputMapSelect
Definition: ntv2virtualregisters.h:155
NTV2DeviceGetNumVideoInputs
UWord NTV2DeviceGetNumVideoInputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12200
NTV2DeviceGetNumHDMIVideoOutputs
UWord NTV2DeviceGetNumHDMIVideoOutputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11108
kRegLUTV2Control
@ kRegLUTV2Control
Definition: ntv2publicinterface.h:524
SuppNotsupp
#define SuppNotsupp(__x__)
Definition: ntv2registerexpert.h:32
kVRegAudioHeadphoneGain
@ kVRegAudioHeadphoneGain
Definition: ntv2virtualregisters.h:586
kRegAudioMixerInputSelects
@ kRegAudioMixerInputSelects
Definition: ntv2publicinterface.h:794
kVRegUnfilterAnc
@ kVRegUnfilterAnc
Definition: ntv2virtualregisters.h:124
kVRegProcAmpHighDefSaturationCr
@ kVRegProcAmpHighDefSaturationCr
Definition: ntv2virtualregisters.h:209
kVRegOutputTimecodeType
@ kVRegOutputTimecodeType
Definition: ntv2virtualregisters.h:181
NTV2AudioChannelPair
NTV2AudioChannelPair
Identifies a pair of audio channels.
Definition: ntv2enums.h:3087
kRegDMA3NextDesc
@ kRegDMA3NextDesc
Definition: ntv2publicinterface.h:146
kVRegProcAmpHDRegsInitialized
@ kVRegProcAmpHDRegsInitialized
Definition: ntv2virtualregisters.h:205
kRegEnhancedCSC1OutOffsetA_B
@ kRegEnhancedCSC1OutOffsetA_B
Definition: ntv2publicinterface.h:866
kRegXptSelectGroup26
@ kRegXptSelectGroup26
Definition: ntv2publicinterface.h:561
kRegGlobalControl3
@ kRegGlobalControl3
Definition: ntv2publicinterface.h:216
NTV2DeviceGetNumLUTs
UWord NTV2DeviceGetNumLUTs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:11563
kColorCorrectionLUTOffset_Red
#define kColorCorrectionLUTOffset_Red
Definition: ntv2publicinterface.h:4172
kRegMaskSmpte372Enable4
@ kRegMaskSmpte372Enable4
Definition: ntv2publicinterface.h:1190
kVRegDmaTransferRateC2H1
@ kVRegDmaTransferRateC2H1
Definition: ntv2virtualregisters.h:592
kRegRP188InOut7Bits0_31
@ kRegRP188InOut7Bits0_31
Definition: ntv2publicinterface.h:583
UWord
uint16_t UWord
Definition: ajatypes.h:253
kVRegTimeCodeIn2Delay
@ kVRegTimeCodeIn2Delay
Definition: ntv2virtualregisters.h:94
kRegDMA3HostAddr
@ kRegDMA3HostAddr
Definition: ntv2publicinterface.h:143
kRegAudioMixerMainInputLevelsPair7
@ kRegAudioMixerMainInputLevelsPair7
Definition: ntv2publicinterface.h:814
NTV2_Xpt4KDCQ1Input
@ NTV2_Xpt4KDCQ1Input
Definition: ntv2enums.h:2829
kK2RegShiftConverterOutStandard
@ kK2RegShiftConverterOutStandard
Definition: ntv2publicinterface.h:2686
kVRegMailBoxTimeoutNS
@ kVRegMailBoxTimeoutNS
Definition: ntv2virtualregisters.h:415
kVRegDTAudioMux2
@ kVRegDTAudioMux2
Definition: ntv2virtualregisters.h:71
kRegSDIOut5Control
@ kRegSDIOut5Control
Definition: ntv2publicinterface.h:473
kRegAud6OutputLastAddr
@ kRegAud6OutputLastAddr
Definition: ntv2publicinterface.h:608
regNTV4FS_ROIF1StartAddr
@ regNTV4FS_ROIF1StartAddr
Definition: ntv2registerexpert.cpp:56
kVRegProcAmpStandardDefContrast
@ kVRegProcAmpStandardDefContrast
Definition: ntv2virtualregisters.h:198
kVRegDesktopFrameBufferStatus
@ kVRegDesktopFrameBufferStatus
Definition: ntv2virtualregisters.h:168
kRegAud3OutputLastAddr
@ kRegAud3OutputLastAddr
Definition: ntv2publicinterface.h:406
kVRegAudioHeadphoneEnable
@ kVRegAudioHeadphoneEnable
Definition: ntv2virtualregisters.h:588
kRegHDMIV2VActiveField2
@ kRegHDMIV2VActiveField2
Definition: ntv2publicinterface.h:514
kRegDMA4NextDesc
@ kRegDMA4NextDesc
Definition: ntv2publicinterface.h:150
kRegRP188InOut6Bits0_31_2
@ kRegRP188InOut6Bits0_31_2
Definition: ntv2publicinterface.h:335
kRegDMA1HostAddr
@ kRegDMA1HostAddr
Definition: ntv2publicinterface.h:135
NTV2_XptCSC8VidInput
@ NTV2_XptCSC8VidInput
Definition: ntv2enums.h:2754
kRegMaskMRStandard
@ kRegMaskMRStandard
Definition: ntv2publicinterface.h:2197
kVRegIsoConvertEnable
@ kVRegIsoConvertEnable
Definition: ntv2virtualregisters.h:118
kVRegTimeCodeIn5Delay
@ kVRegTimeCodeIn5Delay
Definition: ntv2virtualregisters.h:100
NTV2_XptDualLinkOut4Input
@ NTV2_XptDualLinkOut4Input
Definition: ntv2enums.h:2803
kVRegRGB10Endian
@ kVRegRGB10Endian
Definition: ntv2virtualregisters.h:57
kRegHDMIInputControl
@ kRegHDMIInputControl
Definition: ntv2publicinterface.h:242
kVRegProcAmpStandardDefBrightness
@ kVRegProcAmpStandardDefBrightness
Definition: ntv2virtualregisters.h:197
kRegCS3Coefficients3_4
@ kRegCS3Coefficients3_4
Definition: ntv2publicinterface.h:416
kRegLTC4EmbeddedBits32_63
@ kRegLTC4EmbeddedBits32_63
Definition: ntv2publicinterface.h:450
kRegMaskStandard
@ kRegMaskStandard
Definition: ntv2publicinterface.h:1163
kRegSDIIn8VPIDA
@ kRegSDIIn8VPIDA
Definition: ntv2publicinterface.h:589
NTV2_XptCSC3VidInput
@ NTV2_XptCSC3VidInput
Definition: ntv2enums.h:2744
NTV2UpConvertMode
NTV2UpConvertMode
Definition: ntv2enums.h:2194
kK2RegMaskDeinterlaceMode
@ kK2RegMaskDeinterlaceMode
Definition: ntv2publicinterface.h:1618
ntv2utils.h
Declares numerous NTV2 utility functions.
kRegInputStatus2
@ kRegInputStatus2
Definition: ntv2publicinterface.h:411
NTV2_XptLUT8Input
@ NTV2_XptLUT8Input
Definition: ntv2enums.h:2763
kRegXptSelectGroup35
@ kRegXptSelectGroup35
Definition: ntv2publicinterface.h:687
kVRegFrameBufferGangCount
@ kVRegFrameBufferGangCount
Definition: ntv2virtualregisters.h:318
NTV2_XptFrameBuffer8DS2Input
@ NTV2_XptFrameBuffer8DS2Input
Definition: ntv2enums.h:2739
kRegXptSelectGroup21
@ kRegXptSelectGroup21
Definition: ntv2publicinterface.h:555
NTV2_XptMixer2FGVidInput
@ NTV2_XptMixer2FGVidInput
Definition: ntv2enums.h:2815
YesNo
#define YesNo(__x__)
Definition: ntv2registerexpert.h:25
NTV2DeviceCanDo3GLevelConversion
bool NTV2DeviceCanDo3GLevelConversion(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:661
kVRegFrameBuffer1RGBRange
@ kVRegFrameBuffer1RGBRange
Definition: ntv2virtualregisters.h:132
kRegLTC2EmbeddedBits32_63
@ kRegLTC2EmbeddedBits32_63
Definition: ntv2publicinterface.h:376
regAncExtIgnorePacketReg_1_2_3_4
@ regAncExtIgnorePacketReg_1_2_3_4
Definition: ntv2publicinterface.h:5182
kRegLEDReserved0
@ kRegLEDReserved0
Definition: ntv2publicinterface.h:1067
kRegXptSelectGroup7
@ kRegXptSelectGroup7
Definition: ntv2publicinterface.h:283
kRegDMA1NextDesc
@ kRegDMA1NextDesc
Definition: ntv2publicinterface.h:138
kNumNTV4FrameStoreRegisters
static const ULWord kNumNTV4FrameStoreRegisters(regNTV4FS_REGISTER_COUNT)
kRegMaskVidProcMode
@ kRegMaskVidProcMode
Definition: ntv2publicinterface.h:1274
DisabEnab
#define DisabEnab(__x__)
Definition: ntv2registerexpert.h:30
kVRegNTV2VPIDTransferCharacteristics6
@ kVRegNTV2VPIDTransferCharacteristics6
Definition: ntv2virtualregisters.h:519
kRegShiftHDMIHDRMaxMasteringLuminance
@ kRegShiftHDMIHDRMaxMasteringLuminance
Definition: ntv2publicinterface.h:3190
kVRegAcquireReferenceCount
@ kVRegAcquireReferenceCount
Definition: ntv2virtualregisters.h:66
kRegInput56Status
@ kRegInput56Status
Definition: ntv2publicinterface.h:625
NTV2IsoConvertMode
NTV2IsoConvertMode
Definition: ntv2enums.h:2228
NTV2InputCrosspointID
NTV2InputCrosspointID
Identifies a widget input that potentially can accept a signal emitted from another widget's output (...
Definition: ntv2enums.h:2721
kRegMaskFramePulseRefSelect
@ kRegMaskFramePulseRefSelect
Definition: ntv2publicinterface.h:1217
kRegMask425FB78
@ kRegMask425FB78
Definition: ntv2publicinterface.h:1200
kRegClass_Routing
#define kRegClass_Routing
Definition: ntv2registerexpert.h:64
kVRegFanSpeed
@ kVRegFanSpeed
Definition: ntv2virtualregisters.h:344
kRegMaskSDIWatchdogEnable34
@ kRegMaskSDIWatchdogEnable34
Definition: ntv2publicinterface.h:2016
NTV2_UNUSED
#define NTV2_UNUSED(__p__)
Definition: ajatypes.h:164
kRegCSCoefficients7_8
@ kRegCSCoefficients7_8
Definition: ntv2publicinterface.h:262
kRegCS2Coefficients3_4
@ kRegCS2Coefficients3_4
Definition: ntv2publicinterface.h:266
kRegMaskPWMFanSpeedControl
@ kRegMaskPWMFanSpeedControl
Definition: ntv2publicinterface.h:2209
kVRegTimeStampLastInput4VerticalHi
@ kVRegTimeStampLastInput4VerticalHi
Definition: ntv2virtualregisters.h:270
kVRegPCIDeviceID
@ kVRegPCIDeviceID
Definition: ntv2virtualregisters.h:304
kVRegVideoFormatCh3
@ kVRegVideoFormatCh3
Definition: ntv2virtualregisters.h:348
kVRegDmaHardwareRateC2H2
@ kVRegDmaHardwareRateC2H2
Definition: ntv2virtualregisters.h:597
kRegClass_CSC
#define kRegClass_CSC
Definition: ntv2registerexpert.h:52
kRegBitfileDate
@ kRegBitfileDate
Definition: ntv2publicinterface.h:193
kRegMaskRP188ModeCh7
@ kRegMaskRP188ModeCh7
Definition: ntv2publicinterface.h:1205
gInstanceTally
static uint32_t gInstanceTally(0)
kRegStatus2
@ kRegStatus2
Definition: ntv2publicinterface.h:388
kRegBOBStatus
@ kRegBOBStatus
Definition: ntv2publicinterface.h:1058
kRegHDMIV2VActiveField1
@ kRegHDMIV2VActiveField1
Definition: ntv2publicinterface.h:513
kVRegAnalogIoSelect
@ kVRegAnalogIoSelect
Definition: ntv2virtualregisters.h:192
NTV2OutputXptIDSet
std::set< NTV2OutputXptID > NTV2OutputXptIDSet
A collection of distinct NTV2OutputXptID values.
Definition: ntv2signalrouter.h:18
DEVICE_ID_KONA5_8K_MV_TX
@ DEVICE_ID_KONA5_8K_MV_TX
See KONA 5.
Definition: ntv2enums.h:65
kRegCMW27Out
@ kRegCMW27Out
Definition: ntv2publicinterface.h:1082
kRegClass_ReadOnly
#define kRegClass_ReadOnly
Definition: ntv2registerexpert.h:63
kRegCS3Coefficients1_2
@ kRegCS3Coefficients1_2
Definition: ntv2publicinterface.h:415
NTV2_XptSDIOut1InputDS2
@ NTV2_XptSDIOut1InputDS2
Definition: ntv2enums.h:2769
kVRegTimeCodeCh6Delay
@ kVRegTimeCodeCh6Delay
Definition: ntv2virtualregisters.h:101
NTV2DeviceGetNumFrameStores
UWord NTV2DeviceGetNumFrameStores(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:10732
kRegMask425FB34
@ kRegMask425FB34
Definition: ntv2publicinterface.h:1198
kVRegAudioOutputDelay
@ kVRegAudioOutputDelay
Definition: ntv2virtualregisters.h:171
kVRegHdrInBlueXCh1
@ kVRegHdrInBlueXCh1
Definition: ntv2virtualregisters.h:563
kVRegAudioMixerSourceMainGain
@ kVRegAudioMixerSourceMainGain
Definition: ntv2virtualregisters.h:473
kVRegHDMIOutStereoCodecSelect
@ kVRegHDMIOutStereoCodecSelect
Definition: ntv2virtualregisters.h:142
regAncInsFieldBytes
@ regAncInsFieldBytes
Definition: ntv2publicinterface.h:5206
kRegMaskMREnable
@ kRegMaskMREnable
Definition: ntv2publicinterface.h:2200
regAuxExtFieldVBLStartLine
@ regAuxExtFieldVBLStartLine
Definition: ntv2publicinterface.h:5284
NTV2RegisterNameString
const char * NTV2RegisterNameString(const ULWord inRegNum)
Definition: ntv2debug.cpp:1156
NTV2DeviceCanDoClockMonitor
bool NTV2DeviceCanDoClockMonitor(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2041
kVRegHdmiOutSubSample
@ kVRegHdmiOutSubSample
Definition: ntv2virtualregisters.h:143
kRegCS6Coefficients9_10
@ kRegCS6Coefficients9_10
Definition: ntv2publicinterface.h:632
kRegMaskQuadQuadMode2
@ kRegMaskQuadQuadMode2
Definition: ntv2publicinterface.h:1213
NTV2_XptFrameBuffer1DS2Input
@ NTV2_XptFrameBuffer1DS2Input
Definition: ntv2enums.h:2725
kRegMaskRefSource2
@ kRegMaskRefSource2
Definition: ntv2publicinterface.h:1178
kRegMaskMode
@ kRegMaskMode
Definition: ntv2publicinterface.h:1230
kVRegNTV2VPIDLuminance
@ kVRegNTV2VPIDLuminance
Definition: ntv2virtualregisters.h:501
NTV4FrameStoreRegs
NTV4FrameStoreRegs
Definition: ntv2registerexpert.cpp:51
NTV2_IS_VALID_HDR_PRIMARY
#define NTV2_IS_VALID_HDR_PRIMARY(__val__)
Definition: ntv2publicinterface.h:9917
kVRegNTV2VPIDLuminance6
@ kVRegNTV2VPIDLuminance6
Definition: ntv2virtualregisters.h:521
kRegMaskSDIRelayControl12
@ kRegMaskSDIRelayControl12
Definition: ntv2publicinterface.h:2013
NTV2WidgetID
NTV2WidgetID
Definition: ntv2enums.h:2878
kRegMaskHDMIHDRMaxContentLightLevel
@ kRegMaskHDMIHDRMaxContentLightLevel
Definition: ntv2publicinterface.h:2131
regAncInsPayloadID
@ regAncInsPayloadID
Definition: ntv2publicinterface.h:5216
kRegAud4Control
@ kRegAud4Control
Definition: ntv2publicinterface.h:402
kRegLTC3EmbeddedBits32_63
@ kRegLTC3EmbeddedBits32_63
Definition: ntv2publicinterface.h:447
kRegMaskAudioMixerMainInputEnable
@ kRegMaskAudioMixerMainInputEnable
Definition: ntv2publicinterface.h:2161
kVRegHdrBlueXCh1
@ kVRegHdrBlueXCh1
Definition: ntv2virtualregisters.h:540
kRegAud8SourceSelect
@ kRegAud8SourceSelect
Definition: ntv2publicinterface.h:617
kVRegTxcSfp1RemoteIp3
@ kVRegTxcSfp1RemoteIp3
Definition: ntv2virtualregisters.h:398
regNTV4FS_F1ActiveLines
@ regNTV4FS_F1ActiveLines
Definition: ntv2registerexpert.cpp:62
kVRegDmaTransferRateH2C4
@ kVRegDmaTransferRateH2C4
Definition: ntv2virtualregisters.h:606
kRegClass_Channel7
#define kRegClass_Channel7
Definition: ntv2registerexpert.h:50
regAncExtField1StartAddress
@ regAncExtField1StartAddress
Definition: ntv2publicinterface.h:5171
kVRegNTV2VPIDLuminance8
@ kVRegNTV2VPIDLuminance8
Definition: ntv2virtualregisters.h:529
kRegSDIOut8VPIDB
@ kRegSDIOut8VPIDB
Definition: ntv2publicinterface.h:592
kVRegRotaryGainOverrideEnable
@ kVRegRotaryGainOverrideEnable
Definition: ntv2virtualregisters.h:584
NTV2_Xpt425Mux3BInput
@ NTV2_Xpt425Mux3BInput
Definition: ntv2enums.h:2838
NTV2_XptHDMIOutQ1Input
@ NTV2_XptHDMIOutQ1Input
Definition: ntv2enums.h:2825
kRegSDIOut7VPIDB
@ kRegSDIOut7VPIDB
Definition: ntv2publicinterface.h:582
kRegAudioMixerMainInputLevelsPair0
@ kRegAudioMixerMainInputLevelsPair0
Definition: ntv2publicinterface.h:807
NTV2DeviceHasPWMFanControl
bool NTV2DeviceHasPWMFanControl(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7266
kRegDMAControl
@ kRegDMAControl
Definition: ntv2publicinterface.h:151
kVRegFrameBuffer1Stereo3DMode
@ kVRegFrameBuffer1Stereo3DMode
Definition: ntv2virtualregisters.h:133
kVRegUserInLuminance
@ kVRegUserInLuminance
Definition: ntv2virtualregisters.h:556
kRegSDIOut7Control
@ kRegSDIOut7Control
Definition: ntv2publicinterface.h:647
kRegAudioMixerMainOutputLevelsPair3
@ kRegAudioMixerMainOutputLevelsPair3
Definition: ntv2publicinterface.h:819
kRegOutputTimingControlch4
@ kRegOutputTimingControlch4
Definition: ntv2publicinterface.h:652
kVRegTxcSfp1RemoteIp4
@ kVRegTxcSfp1RemoteIp4
Definition: ntv2virtualregisters.h:406
RegisterExpertPtr
AJARefPtr< RegisterExpert > RegisterExpertPtr
Definition: ntv2registerexpert.cpp:109
kVRegMailBoxAcquire
@ kVRegMailBoxAcquire
Definition: ntv2virtualregisters.h:412
kVRegAnalogOutputType
@ kVRegAnalogOutputType
Definition: ntv2virtualregisters.h:46
kRegSDIWatchdogControlStatus
@ kRegSDIWatchdogControlStatus
Definition: ntv2publicinterface.h:439
kRegDMA3LocalAddr
@ kRegDMA3LocalAddr
Definition: ntv2publicinterface.h:144
kRegAud7Control
@ kRegAud7Control
Definition: ntv2publicinterface.h:611
kVRegSwizzle4kOutput
@ kVRegSwizzle4kOutput
Definition: ntv2virtualregisters.h:484
kVRegNTV2VPIDTransferCharacteristics
@ kVRegNTV2VPIDTransferCharacteristics
Definition: ntv2virtualregisters.h:499
kRegCS4Coefficients5_6
@ kRegCS4Coefficients5_6
Definition: ntv2publicinterface.h:423
kRegShiftHDMIHDRBluePrimaryY
@ kRegShiftHDMIHDRBluePrimaryY
Definition: ntv2publicinterface.h:3185
kRegAud4OutputLastAddr
@ kRegAud4OutputLastAddr
Definition: ntv2publicinterface.h:408
kVRegLUTType
@ kVRegLUTType
Definition: ntv2virtualregisters.h:55
kRegAud5OutputLastAddr
@ kRegAud5OutputLastAddr
Definition: ntv2publicinterface.h:603
kRegRP188InOut1DBB
@ kRegRP188InOut1DBB
Definition: ntv2publicinterface.h:132
kVRegRxcSfp1DestPort2
@ kVRegRxcSfp1DestPort2
Definition: ntv2virtualregisters.h:385
kVRegTxcEnable3
@ kVRegTxcEnable3
Definition: ntv2virtualregisters.h:396
kRegAud5SourceSelect
@ kRegAud5SourceSelect
Definition: ntv2publicinterface.h:602
kVRegTimelapseIntervalValue
@ kVRegTimelapseIntervalValue
Definition: ntv2virtualregisters.h:175
kRegShiftAudioMixerMainInputEnable
@ kRegShiftAudioMixerMainInputEnable
Definition: ntv2publicinterface.h:3222
kVRegSDIInput2RGBRange
@ kVRegSDIInput2RGBRange
Definition: ntv2virtualregisters.h:129
kVRegProcAmpHighDefBrightness
@ kVRegProcAmpHighDefBrightness
Definition: ntv2virtualregisters.h:206
NTV2StringList
std::vector< std::string > NTV2StringList
Definition: ntv2utils.h:1143
kRegFlatMatte3Value
@ kRegFlatMatte3Value
Definition: ntv2publicinterface.h:660
kRegClass_Channel4
#define kRegClass_Channel4
Definition: ntv2registerexpert.h:47
kVRegDTAudioMux0
@ kVRegDTAudioMux0
Definition: ntv2virtualregisters.h:69
kVRegAudioEncoderOutputEnable
@ kVRegAudioEncoderOutputEnable
Definition: ntv2virtualregisters.h:589
NTV2_XptLUT4Input
@ NTV2_XptLUT4Input
Definition: ntv2enums.h:2759
NTV2_XptBlack
@ NTV2_XptBlack
Definition: ntv2enums.h:2505
kVRegDmaTransferRateC2H4
@ kVRegDmaTransferRateC2H4
Definition: ntv2virtualregisters.h:604
kRegLEDHDMIOutControl
@ kRegLEDHDMIOutControl
Definition: ntv2publicinterface.h:1074
kRegSDIOut2Control
@ kRegSDIOut2Control
Definition: ntv2publicinterface.h:246
AJALock
Definition: lock.h:30
kRegAud1SourceSelect
@ kRegAud1SourceSelect
Definition: ntv2publicinterface.h:128
kVRegNTV2VPIDRGBRange3
@ kVRegNTV2VPIDRGBRange3
Definition: ntv2virtualregisters.h:577
NTV2_INPUT_CROSSPOINT_INVALID
@ NTV2_INPUT_CROSSPOINT_INVALID
Definition: ntv2enums.h:2858
kVRegNTV2VPIDTransferCharacteristics1
@ kVRegNTV2VPIDTransferCharacteristics1
Definition: ntv2virtualregisters.h:496
kRegSDIOut1VPIDA
@ kRegSDIOut1VPIDA
Definition: ntv2publicinterface.h:357
regNTV4FS_RasterOutputTimingPreset
@ regNTV4FS_RasterOutputTimingPreset
Definition: ntv2registerexpert.cpp:70
kRegLTCOutBits0_31
@ kRegLTCOutBits0_31
Definition: ntv2publicinterface.h:223
NTV2_XptFrameSync2Input
@ NTV2_XptFrameSync2Input
Definition: ntv2enums.h:2855
kVRegHDROverrideState
@ kVRegHDROverrideState
Definition: ntv2virtualregisters.h:550
NTV2_XptFrameBuffer4DS2Input
@ NTV2_XptFrameBuffer4DS2Input
Definition: ntv2enums.h:2731
kVRegNTV2VPIDLuminance7
@ kVRegNTV2VPIDLuminance7
Definition: ntv2virtualregisters.h:525
kRegDMA3HostAddrHigh
@ kRegDMA3HostAddrHigh
Definition: ntv2publicinterface.h:211
kVRegTimeStampLastInput5VerticalHi
@ kVRegTimeStampLastInput5VerticalHi
Definition: ntv2virtualregisters.h:272
AJA_NULL
#define AJA_NULL
Definition: ajatypes.h:199
kRegXptSelectGroup16
@ kRegXptSelectGroup16
Definition: ntv2publicinterface.h:429
kVRegPCIMaxReadRequestSize
@ kVRegPCIMaxReadRequestSize
Definition: ntv2virtualregisters.h:552
kRegConversionControl
@ kRegConversionControl
Definition: ntv2publicinterface.h:247
kVRegUseHDMI420Mode
@ kVRegUseHDMI420Mode
Definition: ntv2virtualregisters.h:459
kRegAud4SourceSelect
@ kRegAud4SourceSelect
Definition: ntv2publicinterface.h:404
kRegMaskAud2PlayCapMode
@ kRegMaskAud2PlayCapMode
Definition: ntv2publicinterface.h:1182
NTV2_IS_VALID_CHANNEL
#define NTV2_IS_VALID_CHANNEL(__x__)
Definition: ntv2enums.h:1348
kVRegTimeCodeCh4Delay
@ kVRegTimeCodeCh4Delay
Definition: ntv2virtualregisters.h:96
kRegAudioMixerMainOutputLevelsPair4
@ kRegAudioMixerMainOutputLevelsPair4
Definition: ntv2publicinterface.h:820
kRegMaskCC3OutputBankSelect
@ kRegMaskCC3OutputBankSelect
Definition: ntv2publicinterface.h:1373
kRegRP188InOut3Bits0_31_2
@ kRegRP188InOut3Bits0_31_2
Definition: ntv2publicinterface.h:329
kVRegHdrInMaxFALLCh1
@ kVRegHdrInMaxFALLCh1
Definition: ntv2virtualregisters.h:572
NTV2_XptSDIOut5Input
@ NTV2_XptSDIOut5Input
Definition: ntv2enums.h:2776
kRegSDIIn2VPIDB
@ kRegSDIIn2VPIDB
Definition: ntv2publicinterface.h:362
kVRegRP188SourceSelect
@ kVRegRP188SourceSelect
Definition: ntv2virtualregisters.h:162
kRegHDMIInputStatus
@ kRegHDMIInputStatus
Definition: ntv2publicinterface.h:241
kVRegAnalogOutBlackLevel
@ kVRegAnalogOutBlackLevel
Definition: ntv2virtualregisters.h:47
RegisterExpert::GetAllRegisterClasses
NTV2StringSet GetAllRegisterClasses(void) const
Definition: ntv2registerexpert.cpp:1801
kRegCh3OutputFrame
@ kRegCh3OutputFrame
Definition: ntv2publicinterface.h:381
regNTV4FS_RasterPixelSkip
@ regNTV4FS_RasterPixelSkip
Definition: ntv2registerexpert.cpp:65
kVRegTimeCodeIn6Delay
@ kVRegTimeCodeIn6Delay
Definition: ntv2virtualregisters.h:102
kRegMaskRP188ModeCh6
@ kRegMaskRP188ModeCh6
Definition: ntv2publicinterface.h:1204
kRegRP188InOut4Bits0_31_2
@ kRegRP188InOut4Bits0_31_2
Definition: ntv2publicinterface.h:331
AJALabelValuePairsConstIter
AJALabelValuePairs::const_iterator AJALabelValuePairsConstIter
Definition: info.h:70
kRegMRQ4Control
@ kRegMRQ4Control
Definition: ntv2publicinterface.h:1035
NTV2_AudioChannel5_6
@ NTV2_AudioChannel5_6
This selects audio channels 5 and 6 (Group 2 channels 1 and 2)
Definition: ntv2enums.h:3091
kRegDMA1XferCount
@ kRegDMA1XferCount
Definition: ntv2publicinterface.h:137
kRegMaskBOBAbsent
@ kRegMaskBOBAbsent
Definition: ntv2publicinterface.h:2214
NTV2OutputCrosspointID
NTV2OutputCrosspointID
Identifies a widget output, a signal source, that potentially can drive another widget's input (ident...
Definition: ntv2enums.h:2502
kVRegHDMIInDrmLightLevel1
@ kVRegHDMIInDrmLightLevel1
Definition: ntv2virtualregisters.h:615
kRegXptSelectGroup1
@ kRegXptSelectGroup1
Definition: ntv2publicinterface.h:252
kRegXptSelectGroup19
@ kRegXptSelectGroup19
Definition: ntv2publicinterface.h:500
kRegSDIOut6Control
@ kRegSDIOut6Control
Definition: ntv2publicinterface.h:646
kVRegTimeStampLastInput2VerticalLo
@ kVRegTimeStampLastInput2VerticalLo
Definition: ntv2virtualregisters.h:82
AJAAutoLock
Definition: lock.h:91
kRegStatus
@ kRegStatus
Definition: ntv2publicinterface.h:124
ntv2devicefeatures.hh
Declares NTV2DeviceCanDo... and NTV2DeviceGetNum... functions. This module is included at compile tim...
kRegCh7PCIAccessFrame
@ kRegCh7PCIAccessFrame
Definition: ntv2publicinterface.h:548
NTV2_XptDualLinkIn4Input
@ NTV2_XptDualLinkIn4Input
Definition: ntv2enums.h:2790
kRegVidProc1Control
@ kRegVidProc1Control
Definition: ntv2publicinterface.h:111
regAncExtField2AnalogYFilter
@ regAncExtField2AnalogYFilter
Definition: ntv2publicinterface.h:5191
kVRegHdrRedXCh1
@ kVRegHdrRedXCh1
Definition: ntv2virtualregisters.h:542
kRegAudioMixerMainInputLevelsPair6
@ kRegAudioMixerMainInputLevelsPair6
Definition: ntv2publicinterface.h:813
kVRegEnableBT2020
@ kVRegEnableBT2020
Definition: ntv2virtualregisters.h:490
kRegCSCoefficients3_4
@ kRegCSCoefficients3_4
Definition: ntv2publicinterface.h:260
kRegMaskSmpte372Enable6
@ kRegMaskSmpte372Enable6
Definition: ntv2publicinterface.h:1191
kRegSDI5678Input3GStatus
@ kRegSDI5678Input3GStatus
Definition: ntv2publicinterface.h:623
kVRegActiveVideoOutFilter
@ kVRegActiveVideoOutFilter
Definition: ntv2virtualregisters.h:154
regNTV4FS_RasterVideoFill_Cr_AR
@ regNTV4FS_RasterVideoFill_Cr_AR
Definition: ntv2registerexpert.cpp:67
kRegMask2MFrameSupport
@ kRegMask2MFrameSupport
Definition: ntv2publicinterface.h:1194
kRegSDIOut5VPIDA
@ kRegSDIOut5VPIDA
Definition: ntv2publicinterface.h:474
kVRegMacUserModeDebugLevel
@ kVRegMacUserModeDebugLevel
Definition: ntv2virtualregisters.h:240
kRegDMA1HostAddrHigh
@ kRegDMA1HostAddrHigh
Definition: ntv2publicinterface.h:207
kVRegTimeStampLastOutput2VerticalLo
@ kVRegTimeStampLastOutput2VerticalLo
Definition: ntv2virtualregisters.h:280
NTV2_XptSDIOut8Input
@ NTV2_XptSDIOut8Input
Definition: ntv2enums.h:2782
kRegAudioMixerMainInputLevelsPair2
@ kRegAudioMixerMainInputLevelsPair2
Definition: ntv2publicinterface.h:809
kVRegInputSelect
@ kVRegInputSelect
Definition: ntv2virtualregisters.h:41
NTV2_XptLUT5Input
@ NTV2_XptLUT5Input
Definition: ntv2enums.h:2760
kRegCSCoefficients1_2
@ kRegCSCoefficients1_2
Definition: ntv2publicinterface.h:259
kRegAudioMixerChannelSelect
@ kRegAudioMixerChannelSelect
Definition: ntv2publicinterface.h:798
kVRegAudioMixerSourceAux2Enable
@ kVRegAudioMixerSourceAux2Enable
Definition: ntv2virtualregisters.h:472
kVRegSuspendSystemAudio
@ kVRegSuspendSystemAudio
Definition: ntv2virtualregisters.h:310
kVRegRGBRangeConverterLUTType
@ kVRegRGBRangeConverterLUTType
Definition: ntv2virtualregisters.h:229
kRegCMWControl
@ kRegCMWControl
Definition: ntv2publicinterface.h:1079
kRegCPLDVersion
@ kRegCPLDVersion
Definition: ntv2publicinterface.h:166
kRegOutputTimingControlch2
@ kRegOutputTimingControlch2
Definition: ntv2publicinterface.h:650
kRegXptSelectGroup17
@ kRegXptSelectGroup17
Definition: ntv2publicinterface.h:427
kRegMaskAud3PlayCapMode
@ kRegMaskAud3PlayCapMode
Definition: ntv2publicinterface.h:1183
kRegCS7Coefficients7_8
@ kRegCS7Coefficients7_8
Definition: ntv2publicinterface.h:637
kRegLTC8EmbeddedBits0_31
@ kRegLTC8EmbeddedBits0_31
Definition: ntv2publicinterface.h:596
kVRegHdrMaxCLLCh1
@ kVRegHdrMaxCLLCh1
Definition: ntv2virtualregisters.h:548
ntv2bitfile.h
Declares the CNTV2Bitfile class.
kRegMROutControl
@ kRegMROutControl
Definition: ntv2publicinterface.h:1036
kVRegAudioMixerOverrideState
@ kVRegAudioMixerOverrideState
Definition: ntv2virtualregisters.h:469
regAuxExtControl
@ regAuxExtControl
Definition: ntv2publicinterface.h:5275
kRegEnhancedCSC1InOffset0_1
@ kRegEnhancedCSC1InOffset0_1
Definition: ntv2publicinterface.h:855
RegisterExpert::IsRegisterReadOnly
bool IsRegisterReadOnly(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1799
fDEC
#define fDEC(__x__, __w__, __p__)
Definition: ntv2publicinterface.h:5640
kRegMaskRP188ModeCh2
@ kRegMaskRP188ModeCh2
Definition: ntv2publicinterface.h:1174
regAncInsBlankCStartLine
@ regAncInsBlankCStartLine
Definition: ntv2publicinterface.h:5217
kRegAud1Control
@ kRegAud1Control
Definition: ntv2publicinterface.h:127
kVRegProcAmpStandardDefCbOffset
@ kVRegProcAmpStandardDefCbOffset
Definition: ntv2virtualregisters.h:201
NTV2_XptCSC8KeyInput
@ NTV2_XptCSC8KeyInput
Definition: ntv2enums.h:2755
kVRegRxcSfp2SourcePort1
@ kVRegRxcSfp2SourcePort1
Definition: ntv2virtualregisters.h:374
kK2RegShiftConverterOutRate
@ kK2RegShiftConverterOutRate
Definition: ntv2publicinterface.h:2687
NTV2_XptMixer1FGVidInput
@ NTV2_XptMixer1FGVidInput
Definition: ntv2enums.h:2811
kRegDMA3XferCount
@ kRegDMA3XferCount
Definition: ntv2publicinterface.h:145
kVRegNTV2VPIDLuminance4
@ kVRegNTV2VPIDLuminance4
Definition: ntv2virtualregisters.h:513
AJAAtomic::Increment
static int32_t Increment(int32_t volatile *pTarget)
Definition: atomic.cpp:82
kVRegStartupStatusFlags
@ kVRegStartupStatusFlags
Definition: ntv2virtualregisters.h:251
kVRegTxcEnable4
@ kVRegTxcEnable4
Definition: ntv2virtualregisters.h:404
OddEven
#define OddEven(__x__)
Definition: ntv2registerexpert.h:29
kVRegKIPRxCfgError
@ kVRegKIPRxCfgError
Definition: ntv2virtualregisters.h:454
CNTV2RegisterExpert::GetRegistersForClass
static NTV2RegNumSet GetRegistersForClass(const std::string &inClassName)
Definition: ntv2registerexpert.cpp:4684
CNTV2SignalRouter::GetWidgetForOutput
static bool GetWidgetForOutput(const NTV2OutputXptID inOutputXpt, NTV2WidgetID &outWidgetID, const NTV2DeviceID inDeviceID=DEVICE_ID_NOTFOUND)
Returns the widget that "owns" the specified output crosspoint.
Definition: ntv2signalrouter.cpp:426
kRegPWMFanControl
@ kRegPWMFanControl
Definition: ntv2publicinterface.h:1052
NTV2_XptFrameBuffer8Input
@ NTV2_XptFrameBuffer8Input
Definition: ntv2enums.h:2738
kVRegNTV2VPIDColorimetry3
@ kVRegNTV2VPIDColorimetry3
Definition: ntv2virtualregisters.h:508
ntv2vpid.h
Declares the CNTV2VPID class. See SMPTE 352 standard for details.
regNTV4FS_DisplayFID
@ regNTV4FS_DisplayFID
Definition: ntv2registerexpert.cpp:61
kRegHDMIV2VSyncDurationAndBackPorchField2
@ kRegHDMIV2VSyncDurationAndBackPorchField2
Definition: ntv2publicinterface.h:512
NTV2_XptMixer4FGKeyInput
@ NTV2_XptMixer4FGKeyInput
Definition: ntv2enums.h:2822
kVRegFlashStatus
@ kVRegFlashStatus
Definition: ntv2virtualregisters.h:301
kVRegGammaMode
@ kVRegGammaMode
Definition: ntv2virtualregisters.h:54
kRegShiftCC4OutputBankSelect
@ kRegShiftCC4OutputBankSelect
Definition: ntv2publicinterface.h:2458
RegisterExpert::GetRegistersForDevice
NTV2RegNumSet GetRegistersForDevice(const NTV2DeviceID inDeviceID, const int inOtherRegsToInclude) const
Definition: ntv2registerexpert.cpp:1838
NTV2_AudioChannel7_8
@ NTV2_AudioChannel7_8
This selects audio channels 7 and 8 (Group 2 channels 3 and 4)
Definition: ntv2enums.h:3092
kVRegDebug1
@ kVRegDebug1
Definition: ntv2virtualregisters.h:108
kRegRXSDIFreeRunningClockLow
@ kRegRXSDIFreeRunningClockLow
Definition: ntv2publicinterface.h:774
kVRegFirstOEM
@ kVRegFirstOEM
The first virtual register slot available for general use.
Definition: ntv2virtualregisters.h:630
kRegRP188InOut2Bits32_63
@ kRegRP188InOut2Bits32_63
Definition: ntv2publicinterface.h:169
NTV2DeviceHasSDIRelays
bool NTV2DeviceHasSDIRelays(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7542
kVRegTxcSfp2RemotePort3
@ kVRegTxcSfp2RemotePort3
Definition: ntv2virtualregisters.h:402
kVRegTxc_2EncodeStreamType1
@ kVRegTxc_2EncodeStreamType1
Definition: ntv2virtualregisters.h:433
NTV2_XptFrameSync1Input
@ NTV2_XptFrameSync1Input
Definition: ntv2enums.h:2856
kVRegTimeStampLastOutput7VerticalLo
@ kVRegTimeStampLastOutput7VerticalLo
Definition: ntv2virtualregisters.h:293
NTV2RegisterNumber
NTV2RegisterNumber
Definition: ntv2publicinterface.h:100
kRegSDIInput3GStatus2
@ kRegSDIInput3GStatus2
Definition: ntv2publicinterface.h:410
DEC
#define DEC(__x__)
Definition: ntv2publicinterface.h:5606
kVRegHdrMaxFALLCh1
@ kVRegHdrMaxFALLCh1
Definition: ntv2virtualregisters.h:549
NTV2_XptDualLinkIn6DSInput
@ NTV2_XptDualLinkIn6DSInput
Definition: ntv2enums.h:2795
NTV2_XptFrameBuffer2Input
@ NTV2_XptFrameBuffer2Input
Definition: ntv2enums.h:2726
kRegSDIOut1Control
@ kRegSDIOut1Control
Definition: ntv2publicinterface.h:244
kRegSDIOut3VPIDA
@ kRegSDIOut3VPIDA
Definition: ntv2publicinterface.h:394
kRegRP188InOut5Bits32_63_2
@ kRegRP188InOut5Bits32_63_2
Definition: ntv2publicinterface.h:334
NTV2DeviceIDString
const char * NTV2DeviceIDString(const NTV2DeviceID id)
Definition: ntv2debug.cpp:15
regAncInsField2StartAddr
@ regAncInsField2StartAddr
Definition: ntv2publicinterface.h:5209
regAuxExtPacketMask3
@ regAuxExtPacketMask3
Definition: ntv2publicinterface.h:5291
kRegShiftFramePulseRefSelect
@ kRegShiftFramePulseRefSelect
Definition: ntv2publicinterface.h:2300
NTV2DeviceHasXilinxDMA
bool NTV2DeviceHasXilinxDMA(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:7816
regNTV4FS_RasterControl
@ regNTV4FS_RasterControl
Definition: ntv2registerexpert.cpp:64
NTV2_XptDualLinkIn8DSInput
@ NTV2_XptDualLinkIn8DSInput
Definition: ntv2enums.h:2799
NTV2OutputXptIDSetConstIter
NTV2OutputXptIDSet::const_iterator NTV2OutputXptIDSetConstIter
A const iterator for iterating over an NTV2OutputXptIDSet.
Definition: ntv2signalrouter.h:19
kRegMaskIndependentMode
@ kRegMaskIndependentMode
Definition: ntv2publicinterface.h:1193
kK2RegMaskUCPassLine21
@ kK2RegMaskUCPassLine21
Definition: ntv2publicinterface.h:1616
common.h
Private include file for all ajabase sources.
kRegHDMIV2VideoSetup
@ kRegHDMIV2VideoSetup
Definition: ntv2publicinterface.h:508
RegisterExpert::GetRegistersForClass
NTV2RegNumSet GetRegistersForClass(const string &inClassName) const
Definition: ntv2registerexpert.cpp:1828
NTV2UpConvertModeToString
std::string NTV2UpConvertModeToString(const NTV2UpConvertMode inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:6638
NTV2_XptMixer1BGVidInput
@ NTV2_XptMixer1BGVidInput
Definition: ntv2enums.h:2809
kVRegTimeStampLastInput5VerticalLo
@ kVRegTimeStampLastInput5VerticalLo
Definition: ntv2virtualregisters.h:271
kVRegDmaTransferRateH2C2
@ kVRegDmaTransferRateH2C2
Definition: ntv2virtualregisters.h:598
kVRegTimeStampLastOutput5VerticalLo
@ kVRegTimeStampLastOutput5VerticalLo
Definition: ntv2virtualregisters.h:288
kVRegDeviceOnline
@ kVRegDeviceOnline
Definition: ntv2virtualregisters.h:165
kVRegTimeCodeIn1Delay
@ kVRegTimeCodeIn1Delay
Definition: ntv2virtualregisters.h:93
kRegMaskBOBGPIIn4Data
@ kRegMaskBOBGPIIn4Data
Definition: ntv2publicinterface.h:2221
kRegHDMIHDRRedPrimary
@ kRegHDMIHDRRedPrimary
Definition: ntv2publicinterface.h:467
NTV2DriverVersionDecode_Minor
#define NTV2DriverVersionDecode_Minor(__vers__)
Definition: ntv2publicinterface.h:5376
kVRegTimeStampLastOutput5VerticalHi
@ kVRegTimeStampLastOutput5VerticalHi
Definition: ntv2virtualregisters.h:290
kRegRXSDI6Status
@ kRegRXSDI6Status
Definition: ntv2publicinterface.h:747
kRegMaskLEDBlueControl
@ kRegMaskLEDBlueControl
Definition: ntv2publicinterface.h:2237
kVRegZeroHostAncPostCapture
@ kVRegZeroHostAncPostCapture
Definition: ntv2virtualregisters.h:466
kRegPCMControl4321
@ kRegPCMControl4321
Definition: ntv2publicinterface.h:673
kRegEnhancedCSC1CoeffA0
@ kRegEnhancedCSC1CoeffA0
Definition: ntv2publicinterface.h:857
kVRegVideoFormatCh6
@ kVRegVideoFormatCh6
Definition: ntv2virtualregisters.h:351
kRegXptSelectGroup36
@ kRegXptSelectGroup36
Definition: ntv2publicinterface.h:294
kRegShiftHDMIInV2VideoStd
@ kRegShiftHDMIInV2VideoStd
Definition: ntv2publicinterface.h:2621
kVRegBA0MemorySize
@ kVRegBA0MemorySize
Definition: ntv2virtualregisters.h:256
kVRegHDMIOutRgbRange
@ kVRegHDMIOutRgbRange
Definition: ntv2virtualregisters.h:136
REiDBG
#define REiDBG(__x__)
Definition: ntv2registerexpert.cpp:40
kRegRXSDI2Status
@ kRegRXSDI2Status
Definition: ntv2publicinterface.h:711
kNTV4FrameStoreFirstRegNum
static const ULWord kNTV4FrameStoreFirstRegNum(0x0000D000/sizeof(ULWord))
regAncInsLinePixels
@ regAncInsLinePixels
Definition: ntv2publicinterface.h:5212
kVRegTxc_2EncodePcrPid1
@ kVRegTxc_2EncodePcrPid1
Definition: ntv2virtualregisters.h:436
NTV2_XptMixer3BGVidInput
@ NTV2_XptMixer3BGVidInput
Definition: ntv2enums.h:2817
kRegClass_Anc
#define kRegClass_Anc
Definition: ntv2registerexpert.h:41
kRegAudioMixerAux2InputLevels
@ kRegAudioMixerAux2InputLevels
Definition: ntv2publicinterface.h:806
kVRegHDMIOutStereoSelect
@ kVRegHDMIOutStereoSelect
Definition: ntv2virtualregisters.h:141
kRegClass_Channel8
#define kRegClass_Channel8
Definition: ntv2registerexpert.h:51
kVRegTimeStampLastInput6VerticalLo
@ kVRegTimeStampLastInput6VerticalLo
Definition: ntv2virtualregisters.h:273
HEX0N
#define HEX0N(__x__, __n__)
Definition: debug.cpp:1175
kRegCh6Control
@ kRegCh6Control
Definition: ntv2publicinterface.h:540
kVRegTimeStampLastInput1VerticalLo
@ kVRegTimeStampLastInput1VerticalLo
Definition: ntv2virtualregisters.h:80
kVRegDmaTransferRateC2H3
@ kVRegDmaTransferRateC2H3
Definition: ntv2virtualregisters.h:600
kVRegTimeStampLastOutput4VerticalLo
@ kVRegTimeStampLastOutput4VerticalLo
Definition: ntv2virtualregisters.h:285
kVRegFrameBuffer2RGBRange
@ kVRegFrameBuffer2RGBRange
Definition: ntv2virtualregisters.h:150
kVRegDigitalOutput4Select
@ kVRegDigitalOutput4Select
Definition: ntv2virtualregisters.h:227
kRegShiftHDMIHDRRedPrimaryY
@ kRegShiftHDMIHDRRedPrimaryY
Definition: ntv2publicinterface.h:3187
kK2RegShiftUCAutoLine21
@ kK2RegShiftUCAutoLine21
Definition: ntv2publicinterface.h:2694
NTV2FrameBufferFormatToString
std::string NTV2FrameBufferFormatToString(const NTV2FrameBufferFormat inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:6983
kVRegNTV2VPIDRGBRange6
@ kVRegNTV2VPIDRGBRange6
Definition: ntv2virtualregisters.h:580
NTV2_XptCSC7KeyInput
@ NTV2_XptCSC7KeyInput
Definition: ntv2enums.h:2753
NTV2RegisterWriteMode
NTV2RegisterWriteMode
These values are used to determine when certain register writes actually take effect....
Definition: ntv2enums.h:1654
kRegLTCInBits0_31
@ kRegLTCInBits0_31
Definition: ntv2publicinterface.h:225
kRegRP188InOut5Bits0_31_2
@ kRegRP188InOut5Bits0_31_2
Definition: ntv2publicinterface.h:333
kVRegSDIInput2ColorSpaceMode
@ kVRegSDIInput2ColorSpaceMode
Definition: ntv2virtualregisters.h:146
kVRegDMADriverBufferPhysicalAddress
@ kVRegDMADriverBufferPhysicalAddress
Definition: ntv2virtualregisters.h:260
kRegRP188InOut4DBB
@ kRegRP188InOut4DBB
Definition: ntv2publicinterface.h:396
kVRegAudioCapMixerSourceMainEnable
@ kVRegAudioCapMixerSourceMainEnable
Definition: ntv2virtualregisters.h:476
regAncExtAnalogStartLine
@ regAncExtAnalogStartLine
Definition: ntv2publicinterface.h:5189
kRegRXSDI3Status
@ kRegRXSDI3Status
Definition: ntv2publicinterface.h:720
kRegSDIOut1VPIDB
@ kRegSDIOut1VPIDB
Definition: ntv2publicinterface.h:358
LOGGING_MAPPINGS
#define LOGGING_MAPPINGS
Definition: ntv2registerexpert.cpp:33
kVRegHDMIInDrmMasteringLuminence2
@ kVRegHDMIInDrmMasteringLuminence2
Definition: ntv2virtualregisters.h:622
kVRegTxc_2EncodeVideoFormat1
@ kVRegTxc_2EncodeVideoFormat1
Definition: ntv2virtualregisters.h:427
kVRegUserInColorimetry
@ kVRegUserInColorimetry
Definition: ntv2virtualregisters.h:554
NTV2_XptCompressionModInput
@ NTV2_XptCompressionModInput
Definition: ntv2enums.h:2852
NTV2_XptDualLinkOut3Input
@ NTV2_XptDualLinkOut3Input
Definition: ntv2enums.h:2802
kVRegAudioCapMixerSourceMainGain
@ kVRegAudioCapMixerSourceMainGain
Definition: ntv2virtualregisters.h:479
CNTV2RegisterExpert::GetAllRegisterClasses
static NTV2StringSet GetAllRegisterClasses(void)
Definition: ntv2registerexpert.cpp:4670
CNTV2RegisterExpert::Deallocate
static bool Deallocate(void)
Explicitly deallocates the Register Expert singleton.
Definition: ntv2registerexpert.cpp:4632
kRegMaskVidProcBGControl
@ kRegMaskVidProcBGControl
Definition: ntv2publicinterface.h:1273
kRegMaskRefSource
@ kRegMaskRefSource
Definition: ntv2publicinterface.h:1164
kVRegHdrLuminanceCh1
@ kVRegHdrLuminanceCh1
Definition: ntv2virtualregisters.h:537
kRegXptSelectGroup9
@ kRegXptSelectGroup9
Definition: ntv2publicinterface.h:373
kRegCh4Control
@ kRegCh4Control
Definition: ntv2publicinterface.h:383
DEF_REGNAME
#define DEF_REGNAME(_num_)
Definition: ntv2registerexpert.cpp:42
NTV2DeviceCanDoHDMIHDROut
bool NTV2DeviceCanDoHDMIHDROut(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2960
kRegRP188InOut7Bits32_63_2
@ kRegRP188InOut7Bits32_63_2
Definition: ntv2publicinterface.h:338
kRegRP188InOut7Bits0_31_2
@ kRegRP188InOut7Bits0_31_2
Definition: ntv2publicinterface.h:337
NTV2DeviceHasBracketLED
bool NTV2DeviceHasBracketLED(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:6688
kVRegTxcSfp2RemotePort4
@ kVRegTxcSfp2RemotePort4
Definition: ntv2virtualregisters.h:410
kVRegHdrRedYCh1
@ kVRegHdrRedYCh1
Definition: ntv2virtualregisters.h:543
kRegCh1OutputFrame
@ kRegCh1OutputFrame
Definition: ntv2publicinterface.h:105
kVRegQuicktimeUsingBoard
@ kVRegQuicktimeUsingBoard
Definition: ntv2virtualregisters.h:182
kVRegAudioEncoderHeadphoneEnable
@ kVRegAudioEncoderHeadphoneEnable
Definition: ntv2virtualregisters.h:590
kRegInputStatus
@ kRegInputStatus
Definition: ntv2publicinterface.h:125
std
Definition: json.hpp:5362
kVRegGatewayEth0
@ kVRegGatewayEth0
Definition: ntv2virtualregisters.h:358
kRegRP188InOut8Bits0_31_2
@ kRegRP188InOut8Bits0_31_2
Definition: ntv2publicinterface.h:339
kRegCS7Coefficients5_6
@ kRegCS7Coefficients5_6
Definition: ntv2publicinterface.h:636
NTV2DeviceCanDoBreakoutBoard
bool NTV2DeviceCanDoBreakoutBoard(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:1765
regAncInsBlankField2CLines
@ regAncInsBlankField2CLines
Definition: ntv2publicinterface.h:5219
kRegVidIntControl2
@ kRegVidIntControl2
Definition: ntv2publicinterface.h:389
kRegSplitControl
@ kRegSplitControl
Definition: ntv2publicinterface.h:114
kRegCMW12288Out
@ kRegCMW12288Out
Definition: ntv2publicinterface.h:1083
kRegBOBGPIInterruptControl
@ kRegBOBGPIInterruptControl
Definition: ntv2publicinterface.h:1060
NTV2_XptFrameBuffer5DS2Input
@ NTV2_XptFrameBuffer5DS2Input
Definition: ntv2enums.h:2733
kRegCS2Coefficients7_8
@ kRegCS2Coefficients7_8
Definition: ntv2publicinterface.h:268
kRegFirstValidXptROMRegister
@ kRegFirstValidXptROMRegister
Definition: ntv2publicinterface.h:845
kRegXptSelectGroup24
@ kRegXptSelectGroup24
Definition: ntv2publicinterface.h:559
kRegSDIIn3VPIDB
@ kRegSDIIn3VPIDB
Definition: ntv2publicinterface.h:435
kVRegRxcSfp1DestPort1
@ kVRegRxcSfp1DestPort1
Definition: ntv2virtualregisters.h:369
kVRegKIPNetCfgError
@ kVRegKIPNetCfgError
Definition: ntv2virtualregisters.h:458
kRegFlatMatte4Value
@ kRegFlatMatte4Value
Definition: ntv2publicinterface.h:664
kVRegRxc_2DecodeProgramNumber1
@ kVRegRxc_2DecodeProgramNumber1
Definition: ntv2virtualregisters.h:418
kRegMaskSDIWatchdogStatus
@ kRegMaskSDIWatchdogStatus
Definition: ntv2publicinterface.h:2019
kVRegAudioMixerSourceAux1Gain
@ kVRegAudioMixerSourceAux1Gain
Definition: ntv2virtualregisters.h:474
NTV2_XptDualLinkIn5Input
@ NTV2_XptDualLinkIn5Input
Definition: ntv2enums.h:2792
kRegAud2InputLastAddr
@ kRegAud2InputLastAddr
Definition: ntv2publicinterface.h:366
regNTV4FS_RasterOddLineStartAddress
@ regNTV4FS_RasterOddLineStartAddress
Definition: ntv2registerexpert.cpp:73
kVRegHDMIInDrmWhitePoint1
@ kVRegHDMIInDrmWhitePoint1
Definition: ntv2virtualregisters.h:613
kRegMaskDitherOn8BitInput
@ kRegMaskDitherOn8BitInput
Definition: ntv2publicinterface.h:1241
kRegSDIOut4VPIDA
@ kRegSDIOut4VPIDA
Definition: ntv2publicinterface.h:399
kVRegRxcSfp2Vlan1
@ kVRegRxcSfp2Vlan1
Definition: ntv2virtualregisters.h:376
kVRegReleaseLinuxReferenceCount
@ kVRegReleaseLinuxReferenceCount
Definition: ntv2virtualregisters.h:263
gpRegExpert
static RegisterExpertPtr gpRegExpert
Definition: ntv2registerexpert.cpp:4597
NTV2_XptSDIOut6Input
@ NTV2_XptSDIOut6Input
Definition: ntv2enums.h:2778
kVRegTimeCodeCh1Delay
@ kVRegTimeCodeCh1Delay
Definition: ntv2virtualregisters.h:91
kVRegDigitalOutput2Select
@ kVRegDigitalOutput2Select
Definition: ntv2virtualregisters.h:44
kRegClass_HDMI
#define kRegClass_HDMI
Definition: ntv2registerexpert.h:54
kVRegAudioCapMixerSourceAux1Gain
@ kVRegAudioCapMixerSourceAux1Gain
Definition: ntv2virtualregisters.h:480
NTV2_XptMixer2BGVidInput
@ NTV2_XptMixer2BGVidInput
Definition: ntv2enums.h:2813
NTV2RegisterWriteModeToString
std::string NTV2RegisterWriteModeToString(const NTV2RegisterWriteMode inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7330
kVRegNTV2VPIDColorimetry1
@ kVRegNTV2VPIDColorimetry1
Definition: ntv2virtualregisters.h:497
kRegXptSelectGroup29
@ kRegXptSelectGroup29
Definition: ntv2publicinterface.h:564
kRegGlobalControlCh2
@ kRegGlobalControlCh2
Definition: ntv2publicinterface.h:527
kRegXptSelectGroup20
@ kRegXptSelectGroup20
Definition: ntv2publicinterface.h:502
kK2RegShiftIsoConvertMode
@ kK2RegShiftIsoConvertMode
Definition: ntv2publicinterface.h:2695
kRegCh7InputFrame
@ kRegCh7InputFrame
Definition: ntv2publicinterface.h:547
kRegRP188InOut1Bits32_63_2
@ kRegRP188InOut1Bits32_63_2
Definition: ntv2publicinterface.h:326
kRegXptSelectGroup4
@ kRegXptSelectGroup4
Definition: ntv2publicinterface.h:255
kRegClass_XptROM
#define kRegClass_XptROM
Definition: ntv2registerexpert.h:73
kVRegKIPEncCfgError
@ kVRegKIPEncCfgError
Definition: ntv2virtualregisters.h:456
kRegMaskHDMIHDRWhitePointY
@ kRegMaskHDMIHDRWhitePointY
Definition: ntv2publicinterface.h:2128
kRegMaskAnalogIOControl_14
@ kRegMaskAnalogIOControl_14
Definition: ntv2publicinterface.h:1210
kVRegETTDiagLastSerialTimecode
@ kVRegETTDiagLastSerialTimecode
Definition: ntv2virtualregisters.h:250
kRegVidProc2Control
@ kRegVidProc2Control
Definition: ntv2publicinterface.h:370
kVRegRxcSfp2DestPort1
@ kVRegRxcSfp2DestPort1
Definition: ntv2virtualregisters.h:375
NTV2_XptDualLinkIn6Input
@ NTV2_XptDualLinkIn6Input
Definition: ntv2enums.h:2794
kRegMaskFrameRate
@ kRegMaskFrameRate
Definition: ntv2publicinterface.h:1160
kRegCS8Coefficients5_6
@ kRegCS8Coefficients5_6
Definition: ntv2publicinterface.h:642
regAncIns_LAST
@ regAncIns_LAST
Definition: ntv2publicinterface.h:5225
regNTV4FS_ROIVHSize
@ regNTV4FS_ROIVHSize
Definition: ntv2registerexpert.cpp:55
kRegCh1ControlExtended
@ kRegCh1ControlExtended
Definition: ntv2publicinterface.h:285
regAncExtControl
@ regAncExtControl
Definition: ntv2publicinterface.h:5170
kRegShiftCCMode
@ kRegShiftCCMode
Definition: ntv2publicinterface.h:2452
kRegRP188InOut1Bits0_31_2
@ kRegRP188InOut1Bits0_31_2
Definition: ntv2publicinterface.h:325
kRegAudioMixerMainOutputLevelsPair1
@ kRegAudioMixerMainOutputLevelsPair1
Definition: ntv2publicinterface.h:817
RegisterExpert::RegNameToString
string RegNameToString(const uint32_t inRegNum) const
Definition: ntv2registerexpert.cpp:1759
kRegSDIIn4VPIDA
@ kRegSDIIn4VPIDA
Definition: ntv2publicinterface.h:436
kVRegTxc_2EncodeUllMode2
@ kVRegTxc_2EncodeUllMode2
Definition: ntv2virtualregisters.h:440
kRegMaskFrameOrientation
@ kRegMaskFrameOrientation
Definition: ntv2publicinterface.h:1236
kRegCh6PCIAccessFrame
@ kRegCh6PCIAccessFrame
Definition: ntv2publicinterface.h:543
kRegHDMIV2VideoStatus
@ kRegHDMIV2VideoStatus
Definition: ntv2publicinterface.h:515
NTV2_XptDualLinkOut6Input
@ NTV2_XptDualLinkOut6Input
Definition: ntv2enums.h:2805
kVRegXilinxProgramming
@ kVRegXilinxProgramming
Definition: ntv2virtualregisters.h:248
kRegShiftAudioMixerInputLeftLevel
@ kRegShiftAudioMixerInputLeftLevel
Definition: ntv2publicinterface.h:3247
kRegClass_Output
#define kRegClass_Output
Definition: ntv2registerexpert.h:62
NTV2FrameGeometry
NTV2FrameGeometry
Identifies a particular video frame geometry.
Definition: ntv2enums.h:339
NTV2_XptDualLinkOut2Input
@ NTV2_XptDualLinkOut2Input
Definition: ntv2enums.h:2801
kRegRP188InOut2Bits32_63_2
@ kRegRP188InOut2Bits32_63_2
Definition: ntv2publicinterface.h:328
kRegEnhancedCSC1CoeffA2
@ kRegEnhancedCSC1CoeffA2
Definition: ntv2publicinterface.h:859
kRegAud6Control
@ kRegAud6Control
Definition: ntv2publicinterface.h:606
kVRegTimeStampLastOutput6VerticalHi
@ kVRegTimeStampLastOutput6VerticalHi
Definition: ntv2virtualregisters.h:292
kVRegForceApplicationCode
@ kVRegForceApplicationCode
Definition: ntv2virtualregisters.h:187
kVRegTimeStampLastInput4VerticalLo
@ kVRegTimeStampLastInput4VerticalLo
Definition: ntv2virtualregisters.h:269
kRegLEDReserved3
@ kRegLEDReserved3
Definition: ntv2publicinterface.h:1070
kRegCSCoefficients5_6
@ kRegCSCoefficients5_6
Definition: ntv2publicinterface.h:261
kVRegTxc_2EncodeMbps2
@ kVRegTxc_2EncodeMbps2
Definition: ntv2virtualregisters.h:443
kVRegSDIInput1Stereo3DMode
@ kVRegSDIInput1Stereo3DMode
Definition: ntv2virtualregisters.h:130
kRegAudioMixerMainOutputLevelsPair7
@ kRegAudioMixerMainOutputLevelsPair7
Definition: ntv2publicinterface.h:823
kRegMaskRP188ModeCh3
@ kRegMaskRP188ModeCh3
Definition: ntv2publicinterface.h:1201
kVRegTimeCodeIn3Delay
@ kVRegTimeCodeIn3Delay
Definition: ntv2virtualregisters.h:97
kVRegRxc_2DecodeSelectionMode2
@ kVRegRxc_2DecodeSelectionMode2
Definition: ntv2virtualregisters.h:422
kRegCS6Coefficients7_8
@ kRegCS6Coefficients7_8
Definition: ntv2publicinterface.h:631
kRegCh8PCIAccessFrame
@ kRegCh8PCIAccessFrame
Definition: ntv2publicinterface.h:553
kVRegTxcSfp1LocalPort3
@ kVRegTxcSfp1LocalPort3
Definition: ntv2virtualregisters.h:397
kRegBOBGPIOutData
@ kRegBOBGPIOutData
Definition: ntv2publicinterface.h:1061
NTV2_XptDualLinkIn4DSInput
@ NTV2_XptDualLinkIn4DSInput
Definition: ntv2enums.h:2791
true
#define true
Definition: ntv2devicefeatures.h:26
kVRegHdrWhiteYCh1
@ kVRegHdrWhiteYCh1
Definition: ntv2virtualregisters.h:545
NTV2_XptFrameBuffer6DS2Input
@ NTV2_XptFrameBuffer6DS2Input
Definition: ntv2enums.h:2735
kRegXptSelectGroup15
@ kRegXptSelectGroup15
Definition: ntv2publicinterface.h:428
NTV2_XptHDMIOutQ4Input
@ NTV2_XptHDMIOutQ4Input
Definition: ntv2enums.h:2828
kVRegTestPatternFormat
@ kVRegTestPatternFormat
Definition: ntv2virtualregisters.h:231
kVRegTxc_2EncodePcrPid2
@ kVRegTxc_2EncodePcrPid2
Definition: ntv2virtualregisters.h:448
kK2RegMaskFrameSize
@ kK2RegMaskFrameSize
Definition: ntv2publicinterface.h:1244
kVRegTxcSfp2RemoteIp3
@ kVRegTxcSfp2RemoteIp3
Definition: ntv2virtualregisters.h:401
RegisterExpert::IsRegInClass
bool IsRegInClass(const uint32_t inRegNum, const string &inClassName) const
Definition: ntv2registerexpert.cpp:1789
NTV2_XptOEInput
@ NTV2_XptOEInput
Definition: ntv2enums.h:2851
kRegCh1Control
@ kRegCh1Control
Definition: ntv2publicinterface.h:103
kRegMaskBOBGPIIn1InterruptControl
@ kRegMaskBOBGPIIn1InterruptControl
Definition: ntv2publicinterface.h:2223
kRegMRQ2Control
@ kRegMRQ2Control
Definition: ntv2publicinterface.h:1033
NTV2_Xpt425Mux4BInput
@ NTV2_Xpt425Mux4BInput
Definition: ntv2enums.h:2840
RegisterExpert
Definition: ntv2registerexpert.cpp:122
kVRegDisplayReferenceSelect
@ kVRegDisplayReferenceSelect
Definition: ntv2virtualregisters.h:113
kRegMaskAudioMixerOutputChannelsMute
@ kRegMaskAudioMixerOutputChannelsMute
Definition: ntv2publicinterface.h:2144
kRegShiftHDMIHDRMinMasteringLuminance
@ kRegShiftHDMIHDRMinMasteringLuminance
Definition: ntv2publicinterface.h:3191
kRegBOBAudioControl
@ kRegBOBAudioControl
Definition: ntv2publicinterface.h:1062
kVRegRxc_2DecodeProgramNumber2
@ kVRegRxc_2DecodeProgramNumber2
Definition: ntv2virtualregisters.h:423
kRegMaskHDMIHDRMaxFrameAverageLightLevel
@ kRegMaskHDMIHDRMaxFrameAverageLightLevel
Definition: ntv2publicinterface.h:2132
NTV2Audio4ChannelSelect
NTV2Audio4ChannelSelect
Identifies a contiguous, adjacent group of four audio channels.
Definition: ntv2enums.h:3227
kRegMixer2Coefficient
@ kRegMixer2Coefficient
Definition: ntv2publicinterface.h:371
kVRegTxcSfp2LocalPort4
@ kVRegTxcSfp2LocalPort4
Definition: ntv2virtualregisters.h:408
kRegClass_Audio
#define kRegClass_Audio
Definition: ntv2registerexpert.h:42
kVRegTimeStampLastInput7VerticalLo
@ kVRegTimeStampLastInput7VerticalLo
Definition: ntv2virtualregisters.h:275
kLHIRegShiftHDMIOutFPS
@ kLHIRegShiftHDMIOutFPS
Definition: ntv2publicinterface.h:2604
kRegCh7OutputFrame
@ kRegCh7OutputFrame
Definition: ntv2publicinterface.h:546
kRegMaskLEDRedControl
@ kRegMaskLEDRedControl
Definition: ntv2publicinterface.h:2239
kVRegAudioMixerSourceAux1Enable
@ kVRegAudioMixerSourceAux1Enable
Definition: ntv2virtualregisters.h:471
kVRegDmaHardwareRateH2C2
@ kVRegDmaHardwareRateH2C2
Definition: ntv2virtualregisters.h:599
kRegMaskMonitorSource
@ kRegMaskMonitorSource
Definition: ntv2publicinterface.h:1888
kVRegHdrGreenXCh1
@ kVRegHdrGreenXCh1
Definition: ntv2virtualregisters.h:538
kVRegTxc_2EncodeAudioChannels2
@ kVRegTxc_2EncodeAudioChannels2
Definition: ntv2virtualregisters.h:444
kRegCS8Coefficients3_4
@ kRegCS8Coefficients3_4
Definition: ntv2publicinterface.h:641
kRegMaskAud4PlayCapMode
@ kRegMaskAud4PlayCapMode
Definition: ntv2publicinterface.h:1184
kRegMaskHDMIOutV2VideoStd
@ kRegMaskHDMIOutV2VideoStd
Definition: ntv2publicinterface.h:1519
kRegCh2ControlExtended
@ kRegCh2ControlExtended
Definition: ntv2publicinterface.h:286
kVRegFollowInputFormat
@ kVRegFollowInputFormat
Definition: ntv2virtualregisters.h:333
RegisterExpert::GetRegisterClasses
NTV2StringSet GetRegisterClasses(const uint32_t inRegNum, const bool inRemovePrefix) const
Definition: ntv2registerexpert.cpp:1811
kVRegTimeStampLastInput6VerticalHi
@ kVRegTimeStampLastInput6VerticalHi
Definition: ntv2virtualregisters.h:274
kRegCh4OutputFrame
@ kRegCh4OutputFrame
Definition: ntv2publicinterface.h:384
kVRegTxc_2EncodeChromaSubSamp1
@ kVRegTxc_2EncodeChromaSubSamp1
Definition: ntv2virtualregisters.h:430
kVRegHDMIInDrmInfo2
@ kVRegHDMIInDrmInfo2
Definition: ntv2virtualregisters.h:617
kRegPWMFanStatus
@ kRegPWMFanStatus
Definition: ntv2publicinterface.h:1053
kVRegDmaTransferRateC2H2
@ kVRegDmaTransferRateC2H2
Definition: ntv2virtualregisters.h:596
kVRegRxc_2DecodeProgramPID2
@ kVRegRxc_2DecodeProgramPID2
Definition: ntv2virtualregisters.h:424
NTV2_XptFrameBuffer5Input
@ NTV2_XptFrameBuffer5Input
Definition: ntv2enums.h:2732
NTV2_XptHDMIOutQ2Input
@ NTV2_XptHDMIOutQ2Input
Definition: ntv2enums.h:2826
kVRegRxcEnable1
@ kVRegRxcEnable1
Definition: ntv2virtualregisters.h:364
kVRegHdrInMaxCLLCh1
@ kVRegHdrInMaxCLLCh1
Definition: ntv2virtualregisters.h:571
kRegLEDSDI2Control
@ kRegLEDSDI2Control
Definition: ntv2publicinterface.h:1072
kVRegHDMIInDrmRedPrimary2
@ kVRegHDMIInDrmRedPrimary2
Definition: ntv2virtualregisters.h:620
kRegVidIntControl
@ kRegVidIntControl
Definition: ntv2publicinterface.h:123
NTV2DeviceGetMaxRegisterNumber
ULWord NTV2DeviceGetMaxRegisterNumber(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:9094
kVRegNTV2VPIDTransferCharacteristics4
@ kVRegNTV2VPIDTransferCharacteristics4
Definition: ntv2virtualregisters.h:511
kRegLTC4EmbeddedBits0_31
@ kRegLTC4EmbeddedBits0_31
Definition: ntv2publicinterface.h:449
kVRegDmaTransferRateH2C3
@ kVRegDmaTransferRateH2C3
Definition: ntv2virtualregisters.h:602
kVRegOutputTimecodeOffset
@ kVRegOutputTimecodeOffset
Definition: ntv2virtualregisters.h:180
kVRegRxcSfp2SourcePort2
@ kVRegRxcSfp2SourcePort2
Definition: ntv2virtualregisters.h:390
kRegDMA1LocalAddr
@ kRegDMA1LocalAddr
Definition: ntv2publicinterface.h:136
kVRegServicesInitialized
@ kVRegServicesInitialized
Definition: ntv2virtualregisters.h:316
NTV2_Xpt425Mux4AInput
@ NTV2_Xpt425Mux4AInput
Definition: ntv2enums.h:2839
kRegEnhancedCSC1CoeffB1
@ kRegEnhancedCSC1CoeffB1
Definition: ntv2publicinterface.h:861
SetNotset
#define SetNotset(__x__)
Definition: ntv2registerexpert.h:27
kRegHDMIV2HBlankingMeasurements
@ kRegHDMIV2HBlankingMeasurements
Definition: ntv2publicinterface.h:517
regAuxExtFID
@ regAuxExtFID
Definition: ntv2publicinterface.h:5286
kRegMaskBOBGPIOut4Data
@ kRegMaskBOBGPIOut4Data
Definition: ntv2publicinterface.h:2231
kVRegMacKernelModeDebugLevel
@ kVRegMacKernelModeDebugLevel
Definition: ntv2virtualregisters.h:241
kVRegAgentCheck
@ kVRegAgentCheck
Definition: ntv2virtualregisters.h:337
kRegMaskSmpte372Enable8
@ kRegMaskSmpte372Enable8
Definition: ntv2publicinterface.h:1192
kRegXptSelectGroup11
@ kRegXptSelectGroup11
Definition: ntv2publicinterface.h:314
kRegRP188InOut5Bits0_31
@ kRegRP188InOut5Bits0_31
Definition: ntv2publicinterface.h:477
kVRegDmaHardwareRateH2C4
@ kVRegDmaHardwareRateH2C4
Definition: ntv2virtualregisters.h:607
kRegClass_Aux
#define kRegClass_Aux
Definition: ntv2registerexpert.h:43
kRegAud2OutputLastAddr
@ kRegAud2OutputLastAddr
Definition: ntv2publicinterface.h:365
kVRegRxcSsrc1
@ kVRegRxcSsrc1
Definition: ntv2virtualregisters.h:377
kRegRP188InOut8Bits32_63_2
@ kRegRP188InOut8Bits32_63_2
Definition: ntv2publicinterface.h:340
kVRegInputSelectUser
@ kVRegInputSelectUser
Definition: ntv2virtualregisters.h:48
NTV2OutputXptID
enum NTV2OutputCrosspointID NTV2OutputXptID
kRegCS4Coefficients1_2
@ kRegCS4Coefficients1_2
Definition: ntv2publicinterface.h:421
regAuxExtPacketMask2
@ regAuxExtPacketMask2
Definition: ntv2publicinterface.h:5290
kRegMaskVidProcSyncFail
@ kRegMaskVidProcSyncFail
Definition: ntv2publicinterface.h:1276
kVRegDSKForegroundFade
@ kVRegDSKForegroundFade
Definition: ntv2virtualregisters.h:121
NTV2DeviceGetNumVideoOutputs
UWord NTV2DeviceGetNumVideoOutputs(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:12291
kRegFirmwareUserID
@ kRegFirmwareUserID
Definition: ntv2publicinterface.h:318
kRegShiftHDMIHDRMaxFrameAverageLightLevel
@ kRegShiftHDMIHDRMaxFrameAverageLightLevel
Definition: ntv2publicinterface.h:3193
kRegSDITransmitControl
@ kRegSDITransmitControl
Definition: ntv2publicinterface.h:379
kVRegDynFirmwareUpdateCounts
@ kVRegDynFirmwareUpdateCounts
Definition: ntv2virtualregisters.h:627
kRegAud2SourceSelect
@ kRegAud2SourceSelect
Definition: ntv2publicinterface.h:364
regAncInsFieldIDLines
@ regAncInsFieldIDLines
Definition: ntv2publicinterface.h:5214
kVRegBaseFirmwareDeviceID
@ kVRegBaseFirmwareDeviceID
Definition: ntv2virtualregisters.h:624
NTV2_XptSDIOut7InputDS2
@ NTV2_XptSDIOut7InputDS2
Definition: ntv2enums.h:2781
NTV2DeviceCanDoCustomAnc
bool NTV2DeviceCanDoCustomAnc(const NTV2DeviceID inDeviceID)
Definition: ntv2devicefeatures.hpp:2133
RegisterExpert::~RegisterExpert
~RegisterExpert()
Definition: ntv2registerexpert.cpp:170
kVRegAudioMixerOutputGain
@ kVRegAudioMixerOutputGain
Definition: ntv2virtualregisters.h:585
kRegCh1InputFrame
@ kRegCh1InputFrame
Definition: ntv2publicinterface.h:106
kRegDMA2HostAddrHigh
@ kRegDMA2HostAddrHigh
Definition: ntv2publicinterface.h:209
kVRegNTV2VPIDRGBRange7
@ kVRegNTV2VPIDRGBRange7
Definition: ntv2virtualregisters.h:581
kVRegZeroDeviceAncPostCapture
@ kVRegZeroDeviceAncPostCapture
Definition: ntv2virtualregisters.h:467
kVRegUartRxFifoSize
@ kVRegUartRxFifoSize
Definition: ntv2virtualregisters.h:306
kVRegTimeCodeIn4Delay
@ kVRegTimeCodeIn4Delay
Definition: ntv2virtualregisters.h:98
NTV2_XptWaterMarker2Input
@ NTV2_XptWaterMarker2Input
Definition: ntv2enums.h:2849
kVRegTxcSfp1LocalPort4
@ kVRegTxcSfp1LocalPort4
Definition: ntv2virtualregisters.h:405
kRegCanDoStatus
@ kRegCanDoStatus
Definition: ntv2publicinterface.h:170
NTV2DriverVersionDecode_Build
#define NTV2DriverVersionDecode_Build(__vers__)
Definition: ntv2publicinterface.h:5378
regAncInsFieldBytesHigh
@ regAncInsFieldBytesHigh
Definition: ntv2publicinterface.h:5220
DEF_REG
#define DEF_REG(_num_, _dec_, _rw_, _c1_, _c2_, _c3_)
Definition: ntv2registerexpert.cpp:43
kRegLTCOutBits32_63
@ kRegLTCOutBits32_63
Definition: ntv2publicinterface.h:224
kVRegTimelapseIntervalUnits
@ kVRegTimelapseIntervalUnits
Definition: ntv2virtualregisters.h:176
kVRegNTV2VPIDTransferCharacteristics5
@ kVRegNTV2VPIDTransferCharacteristics5
Definition: ntv2virtualregisters.h:515
kRegSDIOut8VPIDA
@ kRegSDIOut8VPIDA
Definition: ntv2publicinterface.h:591
kVRegTimeCodeCh8Delay
@ kVRegTimeCodeCh8Delay
Definition: ntv2virtualregisters.h:105
kVRegEnableQueuedDMAs
@ kVRegEnableQueuedDMAs
Definition: ntv2virtualregisters.h:253
kVRegQTCodecModeDebug
@ kVRegQTCodecModeDebug
Definition: ntv2virtualregisters.h:163
kRegClass_DMA
#define kRegClass_DMA
Definition: ntv2registerexpert.h:53
kRegSDIOut5VPIDB
@ kRegSDIOut5VPIDB
Definition: ntv2publicinterface.h:475
kRegEnhancedCSC1CoeffC0
@ kRegEnhancedCSC1CoeffC0
Definition: ntv2publicinterface.h:863
kRegMaskBOBADAV801Reset
@ kRegMaskBOBADAV801Reset
Definition: ntv2publicinterface.h:2233
kVRegHdrWhiteXCh1
@ kVRegHdrWhiteXCh1
Definition: ntv2virtualregisters.h:544
kRegRP188InOut7DBB
@ kRegRP188InOut7DBB
Definition: ntv2publicinterface.h:585
kVRegPulldownPattern
@ kVRegPulldownPattern
Definition: ntv2virtualregisters.h:52
kRegClass_AES
#define kRegClass_AES
Definition: ntv2registerexpert.h:39
regAncInsActiveStart
@ regAncInsActiveStart
Definition: ntv2publicinterface.h:5211
kRegAudioMixerMainInputLevelsPair3
@ kRegAudioMixerMainInputLevelsPair3
Definition: ntv2publicinterface.h:810
kVRegGatewayEth1
@ kVRegGatewayEth1
Definition: ntv2virtualregisters.h:362
kVRegHdrInWhiteYCh1
@ kVRegHdrInWhiteYCh1
Definition: ntv2virtualregisters.h:568
kVRegTxc_2EncodeVideoFormat2
@ kVRegTxc_2EncodeVideoFormat2
Definition: ntv2virtualregisters.h:439
kVRegTimelapseCaptureUnits
@ kVRegTimelapseCaptureUnits
Definition: ntv2virtualregisters.h:174
kRegCh5Control
@ kRegCh5Control
Definition: ntv2publicinterface.h:535
kVRegTimeStampMode
@ kVRegTimeStampMode
Definition: ntv2virtualregisters.h:77
kRegMaskBOBADAV801UpdateStatus
@ kRegMaskBOBADAV801UpdateStatus
Definition: ntv2publicinterface.h:2215
kRegCh1ColorCorrectionControl
@ kRegCh1ColorCorrectionControl
Definition: ntv2publicinterface.h:171
kVRegHdrInMasterLumMinCh1
@ kVRegHdrInMasterLumMinCh1
Definition: ntv2virtualregisters.h:570
kRegShiftElectroOpticalTransferFunction
@ kRegShiftElectroOpticalTransferFunction
Definition: ntv2publicinterface.h:3198
NTV2OutputCrosspointIDToString
std::string NTV2OutputCrosspointIDToString(const NTV2OutputCrosspointID inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:6017
kVRegRxcPlayoutDelay2
@ kVRegRxcPlayoutDelay2
Definition: ntv2virtualregisters.h:394
kRegDMA2LocalAddr
@ kRegDMA2LocalAddr
Definition: ntv2publicinterface.h:140
RegisterExpert::GetInstance
static RegisterExpertPtr GetInstance(const bool inCreateIfNecessary=true)
Definition: ntv2registerexpert.cpp:4601
kRegEnhancedCSC1CoeffC1
@ kRegEnhancedCSC1CoeffC1
Definition: ntv2publicinterface.h:864
kVRegBA4MemorySize
@ kVRegBA4MemorySize
Definition: ntv2virtualregisters.h:258
kRegRP188InOut3Bits32_63
@ kRegRP188InOut3Bits32_63
Definition: ntv2publicinterface.h:393
kRegCh6InputFrame
@ kRegCh6InputFrame
Definition: ntv2publicinterface.h:542
kRegCh1PCIAccessFrame
@ kRegCh1PCIAccessFrame
Definition: ntv2publicinterface.h:104
CNTV2RegisterExpert::GetInputCrosspointID
static NTV2InputCrosspointID GetInputCrosspointID(const uint32_t inXptRegNum, const uint32_t inMaskIndex)
Definition: ntv2registerexpert.cpp:4712
regNTV4FS_RasterVTotalLines
@ regNTV4FS_RasterVTotalLines
Definition: ntv2registerexpert.cpp:71
kRegCS7Coefficients1_2
@ kRegCS7Coefficients1_2
Definition: ntv2publicinterface.h:634
kVRegReleaseReferenceCount
@ kVRegReleaseReferenceCount
Definition: ntv2virtualregisters.h:67
NTV2ReferenceSourceToString
std::string NTV2ReferenceSourceToString(const NTV2ReferenceSource inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7301
kVRegHdrInMasterLumMaxCh1
@ kVRegHdrInMasterLumMaxCh1
Definition: ntv2virtualregisters.h:569
kRegSDIOut2VPIDA
@ kRegSDIOut2VPIDA
Definition: ntv2publicinterface.h:359
kRegMaskRP188ModeCh8
@ kRegMaskRP188ModeCh8
Definition: ntv2publicinterface.h:1206
regAncExtField2StartAddress
@ regAncExtField2StartAddress
Definition: ntv2publicinterface.h:5173
RegisterExpert::RegValueToString
string RegValueToString(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID) const
Definition: ntv2registerexpert.cpp:1776
kRegFlatMatte2Value
@ kRegFlatMatte2Value
Definition: ntv2publicinterface.h:372
kRegSDIOut7VPIDA
@ kRegSDIOut7VPIDA
Definition: ntv2publicinterface.h:581
kRegMaskSDIRelayPosition12
@ kRegMaskSDIRelayPosition12
Definition: ntv2publicinterface.h:2017
kRegLTC2AnalogBits0_31
@ kRegLTC2AnalogBits0_31
Definition: ntv2publicinterface.h:377
kRegShiftHDMIHDRRedPrimaryX
@ kRegShiftHDMIHDRRedPrimaryX
Definition: ntv2publicinterface.h:3186
kVRegDriverVersion
@ kVRegDriverVersion
Packed driver version – use NTV2DriverVersionEncode, NTV2DriverVersionDecode* macros to encode/decode...
Definition: ntv2virtualregisters.h:29
AJALabelValuePairs
std::vector< AJALabelValuePair > AJALabelValuePairs
An ordered sequence of label/value pairs.
Definition: info.h:69
regAuxExtTotalStatus
@ regAuxExtTotalStatus
Definition: ntv2publicinterface.h:5281
regAncInsControl
@ regAncInsControl
Definition: ntv2publicinterface.h:5207
kRegAudioMixerMainOutputLevelsPair2
@ kRegAudioMixerMainOutputLevelsPair2
Definition: ntv2publicinterface.h:818
BIT
#define BIT(_x_)
Definition: ajatypes.h:563
kVRegTimeStampLastInput3VerticalLo
@ kVRegTimeStampLastInput3VerticalLo
Definition: ntv2virtualregisters.h:267
xHEX0N
#define xHEX0N(__x__, __n__)
Definition: ntv2publicinterface.h:5605
kRegOutputTimingControl
@ kRegOutputTimingControl
Definition: ntv2publicinterface.h:116
NTV2AudioSystem
NTV2AudioSystem
Used to identify an Audio System on an NTV2 device. See Audio System Operation for more information.
Definition: ntv2enums.h:3848
kVRegRxcSfp1RxMatch1
@ kVRegRxcSfp1RxMatch1
Definition: ntv2virtualregisters.h:365
kRegCS5Coefficients5_6
@ kRegCS5Coefficients5_6
Definition: ntv2publicinterface.h:490
NTV2_AudioChannel1_2
@ NTV2_AudioChannel1_2
This selects audio channels 1 and 2 (Group 1 channels 1 and 2)
Definition: ntv2enums.h:3089
kRegDMAIntControl
@ kRegDMAIntControl
Definition: ntv2publicinterface.h:152
kRegEnhancedCSC1CoeffB0
@ kRegEnhancedCSC1CoeffB0
Definition: ntv2publicinterface.h:860
kVRegSDIInput1ColorSpaceMode
@ kVRegSDIInput1ColorSpaceMode
Definition: ntv2virtualregisters.h:144
kVRegDSKGraphicFileIndex
@ kVRegDSKGraphicFileIndex
Definition: ntv2virtualregisters.h:158
NTV2_XptMixer1BGKeyInput
@ NTV2_XptMixer1BGKeyInput
Definition: ntv2enums.h:2808
kVRegHDMIOutColorSpaceModeCtrl
@ kVRegHDMIOutColorSpaceModeCtrl
Definition: ntv2virtualregisters.h:139
NTV2_XptCSC5VidInput
@ NTV2_XptCSC5VidInput
Definition: ntv2enums.h:2748
kRegShiftHDMIHDRBluePrimaryX
@ kRegShiftHDMIHDRBluePrimaryX
Definition: ntv2publicinterface.h:3184
kRegSDIIn4VPIDB
@ kRegSDIIn4VPIDB
Definition: ntv2publicinterface.h:437
kVRegRxcSfp2RxMatch2
@ kVRegRxcSfp2RxMatch2
Definition: ntv2virtualregisters.h:387
kVRegLUT3Type
@ kVRegLUT3Type
Definition: ntv2virtualregisters.h:224
kRegXptSelectGroup18
@ kRegXptSelectGroup18
Definition: ntv2publicinterface.h:494
kRegAudioMixerMainGain
@ kRegAudioMixerMainGain
Definition: ntv2publicinterface.h:795
kRegMaskRegClocking
@ kRegMaskRegClocking
Definition: ntv2publicinterface.h:1168
kRegXptSelectGroup23
@ kRegXptSelectGroup23
Definition: ntv2publicinterface.h:558
kVRegTxcSfp2RemoteIp4
@ kVRegTxcSfp2RemoteIp4
Definition: ntv2virtualregisters.h:409
NTV2_XptCSC2KeyInput
@ NTV2_XptCSC2KeyInput
Definition: ntv2enums.h:2743
kVRegRxc_2DecodeProgramPID1
@ kVRegRxc_2DecodeProgramPID1
Definition: ntv2virtualregisters.h:419
kRegLTCStatusControl
@ kRegLTCStatusControl
Definition: ntv2publicinterface.h:356
kRegCh8InputFrame
@ kRegCh8InputFrame
Definition: ntv2publicinterface.h:552
kVRegCustomAncInputSelect
@ kVRegCustomAncInputSelect
Definition: ntv2virtualregisters.h:341
kVRegDebugIPConfigTimeMS
@ kVRegDebugIPConfigTimeMS
Definition: ntv2virtualregisters.h:110
kVRegHdrMasterLumMinCh1
@ kVRegHdrMasterLumMinCh1
Definition: ntv2virtualregisters.h:547
kVRegDTVersionAja
@ kVRegDTVersionAja
Definition: ntv2virtualregisters.h:73
kVRegVideoFormatCh5
@ kVRegVideoFormatCh5
Definition: ntv2virtualregisters.h:350
kVRegRestoreHardwareProcampRegisters
@ kVRegRestoreHardwareProcampRegisters
Definition: ntv2virtualregisters.h:65
NTV2_XptFrameBuffer2DS2Input
@ NTV2_XptFrameBuffer2DS2Input
Definition: ntv2enums.h:2727
kVRegAudioInputSelect
@ kVRegAudioInputSelect
Definition: ntv2virtualregisters.h:246
NTV2FrameRateToString
std::string NTV2FrameRateToString(const NTV2FrameRate inValue, const bool inForRetailDisplay=false)
Definition: ntv2utils.cpp:7227
kRegMaskVidProcFGControl
@ kRegMaskVidProcFGControl
Definition: ntv2publicinterface.h:1272
kRegMaskQuadMode2
@ kRegMaskQuadMode2
Definition: ntv2publicinterface.h:1189
ntv2registerexpert.h
Declares the CNTV2RegisterExpert class.
kVRegTimeCodeIn7Delay
@ kVRegTimeCodeIn7Delay
Definition: ntv2virtualregisters.h:104
kRegHDMIV2HBlankingMeasurements1
@ kRegHDMIV2HBlankingMeasurements1
Definition: ntv2publicinterface.h:518
ajarefptr.h
Defines the AJARefPtr template class.
kRegMaskAudioMixerInputRightLevel
@ kRegMaskAudioMixerInputRightLevel
Definition: ntv2publicinterface.h:2187
NTV2_XptCSC2VidInput
@ NTV2_XptCSC2VidInput
Definition: ntv2enums.h:2742
kRegCS7Coefficients3_4
@ kRegCS7Coefficients3_4
Definition: ntv2publicinterface.h:635
kRegShiftMonitorSource
@ kRegShiftMonitorSource
Definition: ntv2publicinterface.h:2952
kRegShiftHDMIOutAudioSource
@ kRegShiftHDMIOutAudioSource
Definition: ntv2publicinterface.h:2953
NTV2_XptAnalogOutInput
@ NTV2_XptAnalogOutInput
Definition: ntv2enums.h:2841
kRegMaskVidProcSplitStd
@ kRegMaskVidProcSplitStd
Definition: ntv2publicinterface.h:1277
kRegShiftAudioMixerAux1InputEnable
@ kRegShiftAudioMixerAux1InputEnable
Definition: ntv2publicinterface.h:3223
regNTV4FS_LAST
@ regNTV4FS_LAST
Definition: ntv2registerexpert.cpp:78
kVRegProcAmpStandardDefCrOffset
@ kVRegProcAmpStandardDefCrOffset
Definition: ntv2virtualregisters.h:202
kRegRP188InOut4Bits32_63_2
@ kRegRP188InOut4Bits32_63_2
Definition: ntv2publicinterface.h:332
kVRegDigitalOutput5Select
@ kVRegDigitalOutput5Select
Definition: ntv2virtualregisters.h:236
kRegMaskRP188ModeCh1
@ kRegMaskRP188ModeCh1
Definition: ntv2publicinterface.h:1173
kVReg8kOutputTransportSelection
@ kVReg8kOutputTransportSelection
Definition: ntv2virtualregisters.h:191
kVRegVideoFormatCh7
@ kVRegVideoFormatCh7
Definition: ntv2virtualregisters.h:352
kVRegHdrGreenYCh1
@ kVRegHdrGreenYCh1
Definition: ntv2virtualregisters.h:539
ActInact
#define ActInact(__x__)
Definition: ntv2registerexpert.h:31
kRegShiftCC3OutputBankSelect
@ kRegShiftCC3OutputBankSelect
Definition: ntv2publicinterface.h:2457
kRegMaskInputStatusFPS
@ kRegMaskInputStatusFPS
Definition: ntv2publicinterface.h:1554
kRegMaskRP188ModeCh4
@ kRegMaskRP188ModeCh4
Definition: ntv2publicinterface.h:1202
kVRegTimeStampLastOutput7VerticalHi
@ kVRegTimeStampLastOutput7VerticalHi
Definition: ntv2virtualregisters.h:294
kRegMaskInputStatusStd
@ kRegMaskInputStatusStd
Definition: ntv2publicinterface.h:1552
NTV2_XptLUT6Input
@ NTV2_XptLUT6Input
Definition: ntv2enums.h:2761
kRegAud2Control
@ kRegAud2Control
Definition: ntv2publicinterface.h:363
kVRegMailBoxRelease
@ kVRegMailBoxRelease
Definition: ntv2virtualregisters.h:413
kVRegDefaultVideoFormat
@ kVRegDefaultVideoFormat
Definition: ntv2virtualregisters.h:235
kVRegDigitalOutput3Select
@ kVRegDigitalOutput3Select
Definition: ntv2virtualregisters.h:226
kVRegIPAddrEth0
@ kVRegIPAddrEth0
Definition: ntv2virtualregisters.h:356
kVRegTxc_2EncodeChromaSubSamp2
@ kVRegTxc_2EncodeChromaSubSamp2
Definition: ntv2virtualregisters.h:442
kVRegRxc_2DecodeAudioNumber2
@ kVRegRxc_2DecodeAudioNumber2
Definition: ntv2virtualregisters.h:425
kRegAud3Delay
@ kRegAud3Delay
Definition: ntv2publicinterface.h:431
NTV2_XptSDIOut1Input
@ NTV2_XptSDIOut1Input
Definition: ntv2enums.h:2768
kRegMixer3Coefficient
@ kRegMixer3Coefficient
Definition: ntv2publicinterface.h:659
kVRegSDIInConfig
@ kVRegSDIInConfig
Definition: ntv2virtualregisters.h:189
kRegLTC5EmbeddedBits32_63
@ kRegLTC5EmbeddedBits32_63
Definition: ntv2publicinterface.h:484
kRegRP188InOut8Bits0_31
@ kRegRP188InOut8Bits0_31
Definition: ntv2publicinterface.h:593
NTV2_XptCSC1KeyInput
@ NTV2_XptCSC1KeyInput
Definition: ntv2enums.h:2741
kVRegTxc_2EncodeMbps1
@ kVRegTxc_2EncodeMbps1
Definition: ntv2virtualregisters.h:431
NTV2_Xpt425Mux1BInput
@ NTV2_Xpt425Mux1BInput
Definition: ntv2enums.h:2834
kVRegHdrInWhiteXCh1
@ kVRegHdrInWhiteXCh1
Definition: ntv2virtualregisters.h:567
kVRegSDIOutput1ColorSpaceMode
@ kVRegSDIOutput1ColorSpaceMode
Definition: ntv2virtualregisters.h:169
kRegAud6Delay
@ kRegAud6Delay
Definition: ntv2publicinterface.h:669
kRegHDMIHDRLightLevel
@ kRegHDMIHDRLightLevel
Definition: ntv2publicinterface.h:470
CNTV2RegisterExpert::GetDisplayValue
static std::string GetDisplayValue(const uint32_t inRegNum, const uint32_t inRegValue, const NTV2DeviceID inDeviceID=DEVICE_ID_NOTFOUND)
Definition: ntv2registerexpert.cpp:4656
kVRegHdrColorimetryCh1
@ kVRegHdrColorimetryCh1
Definition: ntv2virtualregisters.h:535
kRegAudioMixerMainInputLevelsPair4
@ kRegAudioMixerMainInputLevelsPair4
Definition: ntv2publicinterface.h:811
kVRegRxc_2DecodeSelectionMode1
@ kVRegRxc_2DecodeSelectionMode1
Definition: ntv2virtualregisters.h:417
kRegSDIOut8Control
@ kRegSDIOut8Control
Definition: ntv2publicinterface.h:648
kVRegSwizzle4kInput
@ kVRegSwizzle4kInput
Definition: ntv2virtualregisters.h:483
kVRegApplicationCode
@ kVRegApplicationCode
Definition: ntv2virtualregisters.h:184
kRegCh2ColorCorrectionControl
@ kRegCh2ColorCorrectionControl
Definition: ntv2publicinterface.h:172
kRegBitfileTime
@ kRegBitfileTime
Definition: ntv2publicinterface.h:194
kVRegNTV2VPIDRGBRange8
@ kVRegNTV2VPIDRGBRange8
Definition: ntv2virtualregisters.h:582
kRegSDIIn3VPIDA
@ kRegSDIIn3VPIDA
Definition: ntv2publicinterface.h:434
debug.h
Declares the AJADebug class.
kRegMaskBOBGPIOut3Data
@ kRegMaskBOBGPIOut3Data
Definition: ntv2publicinterface.h:2230
kVRegRxcSfp1SourceIp2
@ kVRegRxcSfp1SourceIp2
Definition: ntv2virtualregisters.h:382
NTV2_XptSDIOut6InputDS2
@ NTV2_XptSDIOut6InputDS2
Definition: ntv2enums.h:2779
kRegMaskAudioMixerAux2InputEnable
@ kRegMaskAudioMixerAux2InputEnable
Definition: ntv2publicinterface.h:2163
kRegMaskPWMFanSpeed
@ kRegMaskPWMFanSpeed
Definition: ntv2publicinterface.h:2208
RegisterExpert::GetInputCrosspointID
NTV2InputCrosspointID GetInputCrosspointID(const uint32_t inXptRegNum, const uint32_t inMaskIndex) const
Definition: ntv2registerexpert.cpp:2064
kK2RegShiftUpConvertMode
@ kK2RegShiftUpConvertMode
Definition: ntv2publicinterface.h:2688
kRegCS5Coefficients1_2
@ kRegCS5Coefficients1_2
Definition: ntv2publicinterface.h:488
AJAAtomic::Decrement
static int32_t Decrement(int32_t volatile *pTarget)
Definition: atomic.cpp:95
kVRegProcAmpEndHighDefRange
@ kVRegProcAmpEndHighDefRange
Definition: ntv2virtualregisters.h:213
NTV2_XptSDIOut3Input
@ NTV2_XptSDIOut3Input
Definition: ntv2enums.h:2772
kVRegRxcSfp1SourcePort2
@ kVRegRxcSfp1SourcePort2
Definition: ntv2virtualregisters.h:384
NTV2_XptDualLinkIn1DSInput
@ NTV2_XptDualLinkIn1DSInput
Definition: ntv2enums.h:2785
kRegRP188InOut6DBB
@ kRegRP188InOut6DBB
Definition: ntv2publicinterface.h:575
kVRegUserLuminance
@ kVRegUserLuminance
Definition: ntv2virtualregisters.h:533
kRegMaskFrameBufferMode
@ kRegMaskFrameBufferMode
Definition: ntv2publicinterface.h:1238
kRegMaskAud5PlayCapMode
@ kRegMaskAud5PlayCapMode
Definition: ntv2publicinterface.h:1185
kVRegRGBRangeMode
@ kVRegRGBRangeMode
Definition: ntv2virtualregisters.h:252
kRegPCMControl8765
@ kRegPCMControl8765
Definition: ntv2publicinterface.h:674
kVRegRxcSsrc2
@ kVRegRxcSsrc2
Definition: ntv2virtualregisters.h:393
NTV2_Xpt425Mux2AInput
@ NTV2_Xpt425Mux2AInput
Definition: ntv2enums.h:2835
sSpace
static const string sSpace(" ")
kVRegInput1UserBufferLevel
@ kVRegInput1UserBufferLevel
Definition: ntv2virtualregisters.h:218
kRegDMA2HostAddr
@ kRegDMA2HostAddr
Definition: ntv2publicinterface.h:139
kVRegTxc_2EncodeVideoPid2
@ kVRegTxc_2EncodeVideoPid2
Definition: ntv2virtualregisters.h:447
kRegCh3InputFrame
@ kRegCh3InputFrame
Definition: ntv2publicinterface.h:382
kVRegNumberVideoMappingRegisters
@ kVRegNumberVideoMappingRegisters
Definition: ntv2virtualregisters.h:84
kVRegAudioRecordPinDelay
@ kVRegAudioRecordPinDelay
Definition: ntv2virtualregisters.h:32
kRegCS7Coefficients9_10
@ kRegCS7Coefficients9_10
Definition: ntv2publicinterface.h:638
kRegMaskBOBGPIOut1Data
@ kRegMaskBOBGPIOut1Data
Definition: ntv2publicinterface.h:2228
kRegAud1Detect
@ kRegAud1Detect
Definition: ntv2publicinterface.h:126
NTV2AudioSystemToString
std::string NTV2AudioSystemToString(const NTV2AudioSystem inValue, const bool inCompactDisplay=false)
Definition: ntv2utils.cpp:5805
kRegMaskQuarterSizeMode
@ kRegMaskQuarterSizeMode
Definition: ntv2publicinterface.h:1237
kVRegTimeStampLastInput8VerticalHi
@ kVRegTimeStampLastInput8VerticalHi
Definition: ntv2virtualregisters.h:278
kRegMaskBOBGPIIn3Data
@ kRegMaskBOBGPIIn3Data
Definition: ntv2publicinterface.h:2220
NTV2_XptDualLinkOut1Input
@ NTV2_XptDualLinkOut1Input
Definition: ntv2enums.h:2800
kRegCSCoefficients9_10
@ kRegCSCoefficients9_10
Definition: ntv2publicinterface.h:263
kRegLTCInBits32_63
@ kRegLTCInBits32_63
Definition: ntv2publicinterface.h:226
kK2RegMaskConverterOutStandard
@ kK2RegMaskConverterOutStandard
Definition: ntv2publicinterface.h:1609
kRegAud7SourceSelect
@ kRegAud7SourceSelect
Definition: ntv2publicinterface.h:612
regAncExtFieldVBLStartLine
@ regAncExtFieldVBLStartLine
Definition: ntv2publicinterface.h:5179
kRegGlobalControl
@ kRegGlobalControl
Definition: ntv2publicinterface.h:102
kRegRP188InOut8DBB
@ kRegRP188InOut8DBB
Definition: ntv2publicinterface.h:595
kVRegDTAudioCapturePinConnected
@ kVRegDTAudioCapturePinConnected
Definition: ntv2virtualregisters.h:75
NTV2_XptCSC6VidInput
@ NTV2_XptCSC6VidInput
Definition: ntv2enums.h:2750
kVRegProcAmpHighDefCrOffset
@ kVRegProcAmpHighDefCrOffset
Definition: ntv2virtualregisters.h:212
NTV2_XptDualLinkOut8Input
@ NTV2_XptDualLinkOut8Input
Definition: ntv2enums.h:2807
kRegMaskVidProcFGMatteEnable
@ kRegMaskVidProcFGMatteEnable
Definition: ntv2publicinterface.h:1270
kVRegRxcSfp1SourcePort1
@ kVRegRxcSfp1SourcePort1
Definition: ntv2virtualregisters.h:368
regAuxExtField1Status
@ regAuxExtField1Status
Definition: ntv2publicinterface.h:5282