8 #ifndef REGISTERS_2110_H 9 #define REGISTERS_2110_H 13 #define SAREK_4175_TX_PACKETIZER_1 (0x200000/4) 14 #define SAREK_4175_TX_PACKETIZER_2 (0x201000/4) 15 #define SAREK_4175_TX_PACKETIZER_3 (0x202000/4) 16 #define SAREK_4175_TX_PACKETIZER_4 (0x203000/4) 18 #define SAREK_4175_TX_PACKETIZER_RGB12_1 (0x204000/4) 19 #define SAREK_4175_TX_PACKETIZER_RGB12_2 (0x205000/4) 20 #define SAREK_4175_TX_PACKETIZER_RGB12_3 (0x206000/4) 21 #define SAREK_4175_TX_PACKETIZER_RGB12_4 (0x207000/4) 23 #define SAREK_3190_TX_PACKETIZER_0 (0x220000/4) 24 #define SAREK_3190_TX_PACKETIZER_1 (0x221000/4) 25 #define SAREK_3190_TX_PACKETIZER_2 (0x222000/4) 26 #define SAREK_3190_TX_PACKETIZER_3 (0x223000/4) 28 #define SAREK_4175_RX_DEPACKETIZER_1 (0x208000/4) 29 #define SAREK_4175_RX_DEPACKETIZER_2 (0x209000/4) 30 #define SAREK_4175_RX_DEPACKETIZER_3 (0x20a000/4) 31 #define SAREK_4175_RX_DEPACKETIZER_4 (0x20b000/4) 33 #define SAREK_3190_RX_DEPACKETIZER_1 (0x20c000/4) 34 #define SAREK_3190_RX_DEPACKETIZER_2 (0x20d000/4) 35 #define SAREK_3190_RX_DEPACKETIZER_3 (0x20e000/4) 36 #define SAREK_3190_RX_DEPACKETIZER_4 (0x20f000/4) 38 #define SAREK_2110_VIDEO_FRAMER_0 (0x210000/4) 39 #define SAREK_2110_AUDIO_ANC_FRAMER_0 (0x212000/4) 40 #define SAREK_2110_VIDEO_FRAMER_1 (0x213000/4) 41 #define SAREK_2110_AUDIO_ANC_FRAMER_1 (0x214000/4) 42 #define SAREK_2110_TX_ARBITRATOR (0x215000/4) 43 #define SAREK_2110_DECAPSULATOR_0 (0x211000/4) 44 #define SAREK_2110_DECAPSULATOR_1 (0x216000/4) 45 #define SAREK_2110_VOIPFEC (0x217000/4) 46 #define SAREK_2110_VOIPFEC_CTL (0x218000/4) 47 #define SAREK_2110_FRAMESYNC (0x219000/4) 48 #define SAREK_2110_AUDIO_STREAMSELECT (0x230000/4) 49 #define SAREK_2110_VIDEO_TIMING_CTRLR (0x240000/4) 50 #define SAREK_2110_VIDEO_TIMING_CTRLR2 (0x241000/4) 52 #define SAREK_2110_TEST_GENERATOR (0x308000/4) 53 #define SAREK_AXIS_PCAP (0x309000/4) 62 #define kReg4175_pkt_ctrl 0x00 63 #define kReg4175_pkt_width 0x04 64 #define kReg4175_pkt_height 0x06 65 #define kReg4175_pkt_vid_fmt 0x08 66 #define kReg4175_pkt_pkts_per_line 0x0a 67 #define kReg4175_pkt_payload_len 0x0c 68 #define kReg4175_pkt_payload_len_last 0x0e 69 #define kReg4175_pkt_ssrc 0x10 70 #define kReg4175_pkt_payload_type 0x12 71 #define kReg4175_pkt_bpc_reg 0x14 72 #define kReg4175_pkt_chan_num 0x16 73 #define kReg4175_pkt_tx_pkt_cnt 0x18 74 #define kReg4175_pkt_tx_pkt_cnt_valid 0x19 75 #define kReg4175_pkt_pix_per_pkt 0x1a 76 #define kReg4175_pkt_stat_reset 0x1c 77 #define kReg4175_pkt_interlace_ctrl 0x1e 85 #define kReg4175_depkt_control (0x0000/4) 86 #define kReg4175_depkt_width_o (0x0010/4) 87 #define kReg4175_depkt_height_o (0x0018/4) 88 #define kReg4175_depkt_vid_fmt_o (0x0020/4) 89 #define kReg4175_depkt_pkts_per_line_o (0x0028/4) 90 #define kReg4175_depkt_payload_len_o (0x0030/4) 91 #define kReg4175_depkt_payload_len_last_o (0x0038/4) 92 #define kReg4175_depkt_bpc_reg_o (0x0040/4) 93 #define kReg4175_depkt_rx_pkt_cnt_o (0x0048/4) 94 #define kReg4175_depkt_rx_pkt_cnt_valid_o (0x0050/4) 95 #define kReg4175_depkt_stat_reset_o (0x0054/4) 96 #define kReg4175_depkt_rx_field_cnt (0x0058/4) 97 #define kReg4175_depkt_rx_pkt_cnt (0x005C/4) 98 #define kReg4175_depkt_rx_byte_cnt (0x0060/4) 99 #define kReg4175_depkt_bytes_per_line (0x0064/4) 100 #define kReg4175_depkt_rows_per_field (0x0068/4) 101 #define kReg4175_depkt_version_id (0x006C/4) 102 #define kReg4175_depkt_pixels_per_field (0x0070/4) 103 #define kReg4175_depkt_bytes_per_field (0x0074/4) 104 #define kReg4175_depkt_sequence_err (0x007C/4) 112 #define kReg3190_pkt_ctrl (0x0000/4) 113 #define kReg3190_pkt_num_samples (0x0010/4) 114 #define kReg3190_pkt_num_audio_channels (0x0018/4) 115 #define kReg3190_pkt_payload_len (0x0020/4) 116 #define kReg3190_pkt_chan_num (0x0028/4) 117 #define kReg3190_pkt_payload_type (0x0030/4) 118 #define kReg3190_pkt_ssrc (0x0038/4) 119 #define kReg3190_pkt_tx_pkt_cnt (0x0040/4) 120 #define kReg3190_pkt_stat_reset (0x00B0/4) 129 #define kReg3190_depkt_enable 0 130 #define kReg3190_depkt_config 1 131 #define kReg3190_depkt_rx_pkt_count 2 139 #define kRegFramer_control (0x0000/4) 140 #define kRegFramer_status (0x0004/4) 141 #define kRegFramer_channel_access (0x0008/4) 142 #define kRegFramer_sys_config (0x000c/4) 143 #define kRegFramer_version (0x0010/4) 144 #define kRegFramer_src_mac_lo (0x0014/4) 145 #define kRegFramer_src_mac_hi (0x0018/4) 146 #define kRegFramer_peak_buf_level (0x001c/4) 147 #define kRegFramer_rx_pkt_cnt (0x0020/4) 148 #define kRegFramer_drop_pkt_cnt (0x0024/4) 149 #define kRegFramer_stat_reset (0x0030/4) 152 #define kRegFramer_chan_ctrl (0x0080/4) 153 #define kRegFramer_dest_mac_lo (0x0084/4) 154 #define kRegFramer_dest_mac_hi (0x0088/4) 155 #define kRegFramer_vlan_tag_info (0x008c/4) 156 #define kRegFramer_ip_hdr_media (0x0090/4) 157 #define kRegFramer_ip_hdr_fec (0x0094/4) 158 #define kRegFramer_src_ip (0x0098/4) 159 #define kRegFramer_dst_ip (0x00a8/4) 160 #define kRegFramer_udp_src_port (0x00b8/4) 161 #define kRegFramer_udp_dst_port (0x00bc/4) 162 #define kRegFramer_tk_pkt_cnt (0x00c0/4) 163 #define kRegFramer_chan_stat_reset (0x00c4/4) 171 #define kRegDecap_chan_enable 0x00 172 #define kRegDecap_match_reserved 0x01 173 #define kRegDecap_match_src_ip 0x02 174 #define kRegDecap_match_dst_ip 0x03 175 #define kRegDecap_match_udp_src_port 0x04 176 #define kRegDecap_match_udp_dst_port 0x05 177 #define kRegDecap_match_payload 0x06 178 #define kRegDecap_match_ssrc 0x07 179 #define kRegDecap_match_sel 0x08 180 #define kRegDecap_unused 0x09 181 #define kRegDecap_rx_payload 0x0a 182 #define kRegDecap_rx_ssrc 0x0b 183 #define kRegDecap_rx_pkt_cnt 0x0c 184 #define kRegDecap_reordered_pkt_cnt 0x0d 185 #define kRegDecap_unused2 0x0e 186 #define kRegDecap_descriptiom 0x0f 194 #define kRegVfec_control (0x00/4) 195 #define kRegVfec_status (0x04/4) 196 #define kRegVfec_channel_access (0x08/4) 197 #define kRegVfec_sys_config (0x0c/4) 198 #define kRegVfec_version (0x10/4) 199 #define kRegVfec_fec_processing_delay (0x20/4) 200 #define kRegVfec_fec_packet_drop_cnt (0x24/4) 202 #define kRegVfec_chan_conf (0x80/4) 203 #define kRegVfec_valid_pkt_cnt (0x90/4) 204 #define kRegVfec_unrecv_pkt_cnt (0x94/4) 205 #define kRegVfec_corr_pkt_cnt (0x98/4) 206 #define kRegVfec_dup_pkt_cnt (0x9c/4) 207 #define kRegVfec_channel_status (0xa8/4) 208 #define kRegVfec_curr_buffer_depth (0xac/4) 209 #define kRegVfec_oor_pkt_cnt (0xb0/4) 210 #define kRegVfec_oor_ts_offset (0xb4/4) 211 #define kRegVfec_link_ts_diff (0xb8/4) 213 #define kRegVfec_delay_control (0x00/4) 214 #define kRegVfec_delay_ch0_playout (0x04/4) 215 #define kRegVfec_delay_ch1_playout (0x08/4) 216 #define kRegVfec_delay_ch2_playout (0x0c/4) 217 #define kRegVfec_delay_ch3_playout (0x10/4) 218 #define kRegVfec_audio_pkt_read_intrvl (0x14/4) 219 #define kRegVfec_video_pkt_read_intrvl (0x18/4) 220 #define kRegVfec_delay_status (0x20/4) 221 #define kRegVfec_delay_version (0x3c/4) 229 #define kRegVFS_mm2s_control (0x00/4) 230 #define kRegVFS_mm2s_status (0x04/4) 231 #define kRegVFS_mm2s_index (0x14/4) 232 #define kRegVFS_park_ptr (0x28/4) 233 #define kRegVFS_version (0x2c/4) 234 #define kRegVFS_s2mm_control (0x30/4) 235 #define kRegVFS_s2mm_status (0x34/4) 236 #define kRegVFS_s2mm_irq_mask (0x3c/4) 237 #define kRegVFS_s2mm_index (0x44/4) 238 #define kRegVFS_mm2s_vsize (0x50/4) 239 #define kRegVFS_mm2s_hsize (0x54/4) 240 #define kRegVFS_mm2s_frmdly_stride (0x58/4) 241 #define kRegVFS_mm2s_start_addr01 (0x5c/4) 242 #define kRegVFS_mm2s_start_addr02 (0x60/4) 243 #define kRegVFS_mm2s_start_addr03 (0x64/4) 244 #define kRegVFS_mm2s_start_addr04 (0x68/4) 245 #define kRegVFS_mm2s_start_addr05 (0x6c/4) 246 #define kRegVFS_mm2s_start_addr06 (0x70/4) 247 #define kRegVFS_mm2s_start_addr07 (0x74/4) 248 #define kRegVFS_mm2s_start_addr08 (0x78/4) 249 #define kRegVFS_mm2s_start_addr09 (0x7c/4) 250 #define kRegVFS_mm2s_start_addr10 (0x80/4) 251 #define kRegVFS_mm2s_start_addr11 (0x84/4) 252 #define kRegVFS_mm2s_start_addr12 (0x88/4) 253 #define kRegVFS_mm2s_start_addr13 (0x8c/4) 254 #define kRegVFS_mm2s_start_addr14 (0x90/4) 255 #define kRegVFS_mm2s_start_addr15 (0x94/4) 256 #define kRegVFS_mm2s_start_addr16 (0x98/4) 257 #define kRegVFS_s2mm_vsize (0xa0/4) 258 #define kRegVFS_s2mm_hsize (0xa4/4) 259 #define kRegVFS_s2mm_frmdly_stride (0xa8/4) 260 #define kRegVFS_s2mm_start_addr01 (0xac/4) 261 #define kRegVFS_s2mm_start_addr02 (0xb0/4) 262 #define kRegVFS_s2mm_start_addr03 (0xb4/4) 263 #define kRegVFS_s2mm_start_addr04 (0xb8/4) 264 #define kRegVFS_s2mm_start_addr05 (0xbc/4) 265 #define kRegVFS_s2mm_start_addr06 (0xc0/4) 266 #define kRegVFS_s2mm_start_addr07 (0xc4/4) 267 #define kRegVFS_s2mm_start_addr08 (0xc8/4) 268 #define kRegVFS_s2mm_start_addr09 (0xcc/4) 269 #define kRegVFS_s2mm_start_addr10 (0xd0/4) 270 #define kRegVFS_s2mm_start_addr11 (0xd4/4) 271 #define kRegVFS_s2mm_start_addr12 (0xd8/4) 272 #define kRegVFS_s2mm_start_addr13 (0xdc/4) 273 #define kRegVFS_s2mm_start_addr14 (0xe0/4) 274 #define kRegVFS_s2mm_start_addr15 (0xe4/4) 275 #define kRegVFS_s2mm_start_addr16 (0xe8/4) 283 #define kRegVTC_control (0x000/4) 284 #define kRegVTC_status (0x004/4) 285 #define kRegVTC_error (0x008/4) 286 #define kRegVTC_irq_enable (0x00c/4) 287 #define kRegVTC_version (0x010/4) 288 #define kRegVTC_detector_active_size (0x020/4) 289 #define kRegVTC_detector_timing_status (0x024/4) 290 #define kRegVTC_detector_encoding (0x028/4) 291 #define kRegVTC_detector_polarity (0x02c/4) 292 #define kRegVTC_detector_hsize (0x030/4) 293 #define kRegVTC_detector_vsize (0x034/4) 294 #define kRegVTC_detector_hsync (0x038/4) 295 #define kRegVTC_detector_f0_vblank_h (0x03c/4) 296 #define kRegVTC_detector_f0_vsync_v (0x040/4) 297 #define kRegVTC_detector_f0_vsync_h (0x044/4) 298 #define kRegVTC_generator_active_size (0x060/4) 299 #define kRegVTC_generator_tmng_status (0x064/4) 300 #define kRegVTC_generator_encoding (0x068/4) 301 #define kRegVTC_generator_polarity (0x06c/4) 302 #define kRegVTC_generator_hsize (0x070/4) 303 #define kRegVTC_generator_vsize (0x074/4) 304 #define kRegVTC_generator_hsync (0x078/4) 305 #define kRegVTC_generator_f0_vblank_h (0x07c/4) 306 #define kRegVTC_generator_f0_vsync_v (0x080/4) 307 #define kRegVTC_generator_f0_vsync_h (0x084/4) 308 #define kRegVTC_generator_f1_vblank_h (0x088/4) 309 #define kRegVTC_generator_f1_vsync_v (0x08c/4) 310 #define kRegVTC_generator_f1_vsync_h (0x090/4) 311 #define kRegVTC_frame_sync_cfg_00 (0x100/4) 312 #define kRegVTC_frame_sync_cfg_01 (0x104/4) 313 #define kRegVTC_frame_sync_cfg_02 (0x108/4) 314 #define kRegVTC_frame_sync_cfg_03 (0x10c/4) 315 #define kRegVTC_frame_sync_cfg_04 (0x110/4) 316 #define kRegVTC_frame_sync_cfg_05 (0x114/4) 317 #define kRegVTC_frame_sync_cfg_06 (0x118/4) 318 #define kRegVTC_frame_sync_cfg_07 (0x11c/4) 319 #define kRegVTC_frame_sync_cfg_08 (0x120/4) 320 #define kRegVTC_frame_sync_cfg_09 (0x124/4) 321 #define kRegVTC_frame_sync_cfg_10 (0x128/4) 322 #define kRegVTC_frame_sync_cfg_11 (0x12c/4) 323 #define kRegVTC_frame_sync_cfg_12 (0x130/4) 324 #define kRegVTC_frame_sync_cfg_13 (0x134/4) 325 #define kRegVTC_frame_sync_cfg_14 (0x138/4) 326 #define kRegVTC_frame_sync_cfg_15 (0x13c/4) 327 #define kRegVTC_generator_global_delay (0x140/4) 335 #define kRegArb_video 0x00 336 #define kRegArb_audio 0x01 337 #define kRegArb_4KMode 0x07 338 #define kRegRxVideoDecode1 0x08 339 #define kRegRxVideoDecode2 0x09 340 #define kRegRxVideoDecode3 0x0a 341 #define kRegRxVideoDecode4 0x0b 342 #define kRegTxVideoDecode1 0x0c 343 #define kRegTxVideoDecode2 0x0d 344 #define kRegTxVideoDecode3 0x0e 345 #define kRegTxVideoDecode4 0x0f 347 #define kRegTxAncSSRC1 0x10 348 #define kRegTxAncSSRC2 0x11 349 #define kRegTxAncSSRC3 0x12 350 #define kRegTxAncSSRC4 0x13 351 #define kRegTxAncPayload1 0x14 352 #define kRegTxAncPayload2 0x15 353 #define kRegTxAncPayload3 0x16 354 #define kRegTxAncPayload4 0x17 362 #define kRegRxNtv2VideoDecode1 (S2110_BLOCK_BASE+0) 363 #define kRegRxNtv2VideoDecode2 (S2110_BLOCK_BASE+1) 364 #define kRegRxNtv2VideoDecode3 (S2110_BLOCK_BASE+2) 365 #define kRegRxNtv2VideoDecode4 (S2110_BLOCK_BASE+3) 366 #define kRegTxNtv2VideoDecode1 (S2110_BLOCK_BASE+4) 367 #define kRegTxNtv2VideoDecode2 (S2110_BLOCK_BASE+5) 368 #define kRegTxNtv2VideoDecode3 (S2110_BLOCK_BASE+6) 369 #define kRegTxNtv2VideoDecode4 (S2110_BLOCK_BASE+7) 371 #endif // REGISTERS_2110_H Defines the KonaIP/IoIP registers.
1.8.14